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TARGET_NUCLEO_L053R8/stm32l0xx_hal_rcc_ex.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: 84:0b3ab51c8877
Child:: 92:4fc01daae5a5

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	84:0b3ab51c8877	1	/**
bogdanm	84:0b3ab51c8877	2	******************************************************************************
bogdanm	84:0b3ab51c8877	3	* @file stm32l0xx_hal_rcc_ex.h
bogdanm	84:0b3ab51c8877	4	* @author MCD Application Team
bogdanm	84:0b3ab51c8877	5	* @version V1.0.0
bogdanm	84:0b3ab51c8877	6	* @date 22-April-2014
bogdanm	84:0b3ab51c8877	7	* @brief Header file of RCC HAL Extension module.
bogdanm	84:0b3ab51c8877	8	******************************************************************************
bogdanm	84:0b3ab51c8877	9	* @attention
bogdanm	84:0b3ab51c8877	10	*
bogdanm	84:0b3ab51c8877	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	84:0b3ab51c8877	12	*
bogdanm	84:0b3ab51c8877	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	84:0b3ab51c8877	14	* are permitted provided that the following conditions are met:
bogdanm	84:0b3ab51c8877	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	84:0b3ab51c8877	16	* this list of conditions and the following disclaimer.
bogdanm	84:0b3ab51c8877	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	84:0b3ab51c8877	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	84:0b3ab51c8877	19	* and/or other materials provided with the distribution.
bogdanm	84:0b3ab51c8877	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	84:0b3ab51c8877	21	* may be used to endorse or promote products derived from this software
bogdanm	84:0b3ab51c8877	22	* without specific prior written permission.
bogdanm	84:0b3ab51c8877	23	*
bogdanm	84:0b3ab51c8877	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	84:0b3ab51c8877	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	84:0b3ab51c8877	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	84:0b3ab51c8877	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	84:0b3ab51c8877	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	84:0b3ab51c8877	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	84:0b3ab51c8877	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	84:0b3ab51c8877	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	84:0b3ab51c8877	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	84:0b3ab51c8877	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	84:0b3ab51c8877	34	*
bogdanm	84:0b3ab51c8877	35	******************************************************************************
bogdanm	84:0b3ab51c8877	36	*/
bogdanm	84:0b3ab51c8877	37
bogdanm	84:0b3ab51c8877	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	84:0b3ab51c8877	39	#ifndef __STM32L0xx_HAL_RCC_EX_H
bogdanm	84:0b3ab51c8877	40	#define __STM32L0xx_HAL_RCC_EX_H
bogdanm	84:0b3ab51c8877	41
bogdanm	84:0b3ab51c8877	42	#ifdef __cplusplus
bogdanm	84:0b3ab51c8877	43	extern "C" {
bogdanm	84:0b3ab51c8877	44	#endif
bogdanm	84:0b3ab51c8877	45
bogdanm	84:0b3ab51c8877	46	/* Includes ------------------------------------------------------------------*/
bogdanm	84:0b3ab51c8877	47	#include "stm32l0xx_hal_def.h"
bogdanm	84:0b3ab51c8877	48
bogdanm	84:0b3ab51c8877	49	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	84:0b3ab51c8877	50	* @{
bogdanm	84:0b3ab51c8877	51	*/
bogdanm	84:0b3ab51c8877	52
bogdanm	84:0b3ab51c8877	53	/** @addtogroup RCCEx
bogdanm	84:0b3ab51c8877	54	* @{
bogdanm	84:0b3ab51c8877	55	*/
bogdanm	84:0b3ab51c8877	56
bogdanm	84:0b3ab51c8877	57	/* Exported types ------------------------------------------------------------*/
bogdanm	84:0b3ab51c8877	58	/**
bogdanm	84:0b3ab51c8877	59	* @brief RCC extended clocks structure definition
bogdanm	84:0b3ab51c8877	60	*/
bogdanm	84:0b3ab51c8877	61	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	62	typedef struct
bogdanm	84:0b3ab51c8877	63	{
bogdanm	84:0b3ab51c8877	64	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	84:0b3ab51c8877	65	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	84:0b3ab51c8877	66	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	84:0b3ab51c8877	67	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	84:0b3ab51c8877	68
bogdanm	84:0b3ab51c8877	69	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	84:0b3ab51c8877	70	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	84:0b3ab51c8877	71
bogdanm	84:0b3ab51c8877	72	uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
bogdanm	84:0b3ab51c8877	73	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
bogdanm	84:0b3ab51c8877	74
bogdanm	84:0b3ab51c8877	75	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	84:0b3ab51c8877	76	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
bogdanm	84:0b3ab51c8877	77
bogdanm	84:0b3ab51c8877	78	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	84:0b3ab51c8877	79	This parameter can be a value of @ref RCCEx_RTC_Clock_Source */
bogdanm	84:0b3ab51c8877	80
bogdanm	84:0b3ab51c8877	81	uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection
bogdanm	84:0b3ab51c8877	82	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	84:0b3ab51c8877	83
bogdanm	84:0b3ab51c8877	84	uint32_t LptimClockSelection; /*!< LPTIM1 clock source
bogdanm	84:0b3ab51c8877	85	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
bogdanm	84:0b3ab51c8877	86
bogdanm	84:0b3ab51c8877	87	}RCC_PeriphCLKInitTypeDef;
bogdanm	84:0b3ab51c8877	88	#endif /* !(STM32L051xx) && !(STM32L061xx) */
bogdanm	84:0b3ab51c8877	89
bogdanm	84:0b3ab51c8877	90	#if defined(STM32L051xx) \|\| defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	91	typedef struct
bogdanm	84:0b3ab51c8877	92	{
bogdanm	84:0b3ab51c8877	93	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	84:0b3ab51c8877	94	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	84:0b3ab51c8877	95	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	84:0b3ab51c8877	96	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	84:0b3ab51c8877	97
bogdanm	84:0b3ab51c8877	98	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	84:0b3ab51c8877	99	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	84:0b3ab51c8877	100
bogdanm	84:0b3ab51c8877	101	uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
bogdanm	84:0b3ab51c8877	102	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
bogdanm	84:0b3ab51c8877	103
bogdanm	84:0b3ab51c8877	104	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	84:0b3ab51c8877	105	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
bogdanm	84:0b3ab51c8877	106
bogdanm	84:0b3ab51c8877	107	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	84:0b3ab51c8877	108	This parameter can be a value of @ref RCCEx_RTC_Clock_Source */
bogdanm	84:0b3ab51c8877	109
bogdanm	84:0b3ab51c8877	110	uint32_t LptimClockSelection; /*!< LPTIM1 clock source
bogdanm	84:0b3ab51c8877	111	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
bogdanm	84:0b3ab51c8877	112
bogdanm	84:0b3ab51c8877	113	}RCC_PeriphCLKInitTypeDef;
bogdanm	84:0b3ab51c8877	114	#endif /* STM32L051xx \|\| STM32L061xx */
bogdanm	84:0b3ab51c8877	115
bogdanm	84:0b3ab51c8877	116	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	117	/**
bogdanm	84:0b3ab51c8877	118	* @brief RCC CRS Status structures definition
bogdanm	84:0b3ab51c8877	119	*/
bogdanm	84:0b3ab51c8877	120	typedef enum
bogdanm	84:0b3ab51c8877	121	{
bogdanm	84:0b3ab51c8877	122	RCC_CRS_NONE = 0x00,
bogdanm	84:0b3ab51c8877	123	RCC_CRS_TIMEOUT = 0x01,
bogdanm	84:0b3ab51c8877	124	RCC_CRS_SYNCOK = 0x02,
bogdanm	84:0b3ab51c8877	125	RCC_CRS_SYNCWARM = 0x04,
bogdanm	84:0b3ab51c8877	126	RCC_CRS_SYNCERR = 0x08,
bogdanm	84:0b3ab51c8877	127	RCC_CRS_SYNCMISS = 0x10,
bogdanm	84:0b3ab51c8877	128	RCC_CRS_TRIMOV = 0x20
bogdanm	84:0b3ab51c8877	129	} RCC_CRSStatusTypeDef;
bogdanm	84:0b3ab51c8877	130
bogdanm	84:0b3ab51c8877	131	/**
bogdanm	84:0b3ab51c8877	132	* @brief RCC_CRS Init structure definition
bogdanm	84:0b3ab51c8877	133	*/
bogdanm	84:0b3ab51c8877	134	typedef struct
bogdanm	84:0b3ab51c8877	135	{
bogdanm	84:0b3ab51c8877	136	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
bogdanm	84:0b3ab51c8877	137	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
bogdanm	84:0b3ab51c8877	138
bogdanm	84:0b3ab51c8877	139	uint32_t Source; /*!< Specifies the SYNC signal source.
bogdanm	84:0b3ab51c8877	140	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
bogdanm	84:0b3ab51c8877	141
bogdanm	84:0b3ab51c8877	142	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
bogdanm	84:0b3ab51c8877	143	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
bogdanm	84:0b3ab51c8877	144
bogdanm	84:0b3ab51c8877	145	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
bogdanm	84:0b3ab51c8877	146	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
bogdanm	84:0b3ab51c8877	147	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
bogdanm	84:0b3ab51c8877	148
bogdanm	84:0b3ab51c8877	149	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
bogdanm	84:0b3ab51c8877	150	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
bogdanm	84:0b3ab51c8877	151
bogdanm	84:0b3ab51c8877	152	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
bogdanm	84:0b3ab51c8877	153	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
bogdanm	84:0b3ab51c8877	154
bogdanm	84:0b3ab51c8877	155	}RCC_CRSInitTypeDef;
bogdanm	84:0b3ab51c8877	156
bogdanm	84:0b3ab51c8877	157	/**
bogdanm	84:0b3ab51c8877	158	* @brief RCC_CRS Synchronization structure definition
bogdanm	84:0b3ab51c8877	159	*/
bogdanm	84:0b3ab51c8877	160	typedef struct
bogdanm	84:0b3ab51c8877	161	{
bogdanm	84:0b3ab51c8877	162	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
bogdanm	84:0b3ab51c8877	163	This parameter must be a number between 0 and 0xFFFF*/
bogdanm	84:0b3ab51c8877	164
bogdanm	84:0b3ab51c8877	165	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
bogdanm	84:0b3ab51c8877	166	This parameter must be a number between 0 and 0x3F */
bogdanm	84:0b3ab51c8877	167
bogdanm	84:0b3ab51c8877	168	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
bogdanm	84:0b3ab51c8877	169	value latched in the time of the last SYNC event.
bogdanm	84:0b3ab51c8877	170	This parameter must be a number between 0 and 0xFFFF */
bogdanm	84:0b3ab51c8877	171
bogdanm	84:0b3ab51c8877	172	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
bogdanm	84:0b3ab51c8877	173	frequency error counter latched in the time of the last SYNC event.
bogdanm	84:0b3ab51c8877	174	It shows whether the actual frequency is below or above the target.
bogdanm	84:0b3ab51c8877	175	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
bogdanm	84:0b3ab51c8877	176
bogdanm	84:0b3ab51c8877	177	}RCC_CRSSynchroInfoTypeDef;
bogdanm	84:0b3ab51c8877	178	#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
bogdanm	84:0b3ab51c8877	179
bogdanm	84:0b3ab51c8877	180	/* Exported constants --------------------------------------------------------*/
bogdanm	84:0b3ab51c8877	181	/** @defgroup RCCEx_Exported_Constants
bogdanm	84:0b3ab51c8877	182	* @{
bogdanm	84:0b3ab51c8877	183	*/
bogdanm	84:0b3ab51c8877	184
bogdanm	84:0b3ab51c8877	185	/** @defgroup RCCEx_Periph_Clock_Selection
bogdanm	84:0b3ab51c8877	186	* @{
bogdanm	84:0b3ab51c8877	187	*/
bogdanm	84:0b3ab51c8877	188	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	189	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	84:0b3ab51c8877	190	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	84:0b3ab51c8877	191	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
bogdanm	84:0b3ab51c8877	192	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
bogdanm	84:0b3ab51c8877	193	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
bogdanm	84:0b3ab51c8877	194	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm	84:0b3ab51c8877	195	#define RCC_PERIPHCLK_USB ((uint32_t)0x00000040)
bogdanm	84:0b3ab51c8877	196	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
bogdanm	84:0b3ab51c8877	197
bogdanm	84:0b3ab51c8877	198
bogdanm	84:0b3ab51c8877	199	#define IS_RCC_PERIPHCLK(CLK) ((CLK) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
bogdanm	84:0b3ab51c8877	200	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
bogdanm	84:0b3ab51c8877	201	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1))
bogdanm	84:0b3ab51c8877	202	#endif /* !(STM32L051xx) && !(STM32L061xx) */
bogdanm	84:0b3ab51c8877	203
bogdanm	84:0b3ab51c8877	204	#if defined(STM32L051xx) \|\| defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	205	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	84:0b3ab51c8877	206	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	84:0b3ab51c8877	207	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
bogdanm	84:0b3ab51c8877	208	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
bogdanm	84:0b3ab51c8877	209	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
bogdanm	84:0b3ab51c8877	210	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm	84:0b3ab51c8877	211	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
bogdanm	84:0b3ab51c8877	212
bogdanm	84:0b3ab51c8877	213
bogdanm	84:0b3ab51c8877	214	#define IS_RCC_PERIPHCLK(CLK) ((CLK) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
bogdanm	84:0b3ab51c8877	215	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
bogdanm	84:0b3ab51c8877	216	RCC_PERIPHCLK_LPTIM1))
bogdanm	84:0b3ab51c8877	217	#endif /* !(STM32L051xx) && !(STM32L061xx) */
bogdanm	84:0b3ab51c8877	218	/**
bogdanm	84:0b3ab51c8877	219	* @}
bogdanm	84:0b3ab51c8877	220	*/
bogdanm	84:0b3ab51c8877	221
bogdanm	84:0b3ab51c8877	222	/** @defgroup RCCEx_USART1_Clock_Source
bogdanm	84:0b3ab51c8877	223	* @{
bogdanm	84:0b3ab51c8877	224	*/
bogdanm	84:0b3ab51c8877	225	#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	226	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
bogdanm	84:0b3ab51c8877	227	#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
bogdanm	84:0b3ab51c8877	228	#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 \| RCC_CCIPR_USART1SEL_1)
bogdanm	84:0b3ab51c8877	229	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
bogdanm	84:0b3ab51c8877	230	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
bogdanm	84:0b3ab51c8877	231	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
bogdanm	84:0b3ab51c8877	232	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm	84:0b3ab51c8877	233	/**
bogdanm	84:0b3ab51c8877	234	* @}
bogdanm	84:0b3ab51c8877	235	*/
bogdanm	84:0b3ab51c8877	236
bogdanm	84:0b3ab51c8877	237	/** @defgroup RCCEx_USART2_Clock_Source
bogdanm	84:0b3ab51c8877	238	* @{
bogdanm	84:0b3ab51c8877	239	*/
bogdanm	84:0b3ab51c8877	240	#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	241	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
bogdanm	84:0b3ab51c8877	242	#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
bogdanm	84:0b3ab51c8877	243	#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 \| RCC_CCIPR_USART2SEL_1)
bogdanm	84:0b3ab51c8877	244	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
bogdanm	84:0b3ab51c8877	245	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
bogdanm	84:0b3ab51c8877	246	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
bogdanm	84:0b3ab51c8877	247	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
bogdanm	84:0b3ab51c8877	248	/**
bogdanm	84:0b3ab51c8877	249	* @}
bogdanm	84:0b3ab51c8877	250	*/
bogdanm	84:0b3ab51c8877	251
bogdanm	84:0b3ab51c8877	252	/** @defgroup RCCEx_LPUART_Clock_Source
bogdanm	84:0b3ab51c8877	253	* @{
bogdanm	84:0b3ab51c8877	254	*/
bogdanm	84:0b3ab51c8877	255	#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	256	#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
bogdanm	84:0b3ab51c8877	257	#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
bogdanm	84:0b3ab51c8877	258	#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 \| RCC_CCIPR_LPUART1SEL_1)
bogdanm	84:0b3ab51c8877	259	#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_PCLK1) \|\| \
bogdanm	84:0b3ab51c8877	260	((SOURCE) == RCC_LPUART1CLKSOURCE_SYSCLK) \|\| \
bogdanm	84:0b3ab51c8877	261	((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) \|\| \
bogdanm	84:0b3ab51c8877	262	((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
bogdanm	84:0b3ab51c8877	263	/**
bogdanm	84:0b3ab51c8877	264	* @}
bogdanm	84:0b3ab51c8877	265	*/
bogdanm	84:0b3ab51c8877	266
bogdanm	84:0b3ab51c8877	267	/** @defgroup RCCEx_I2C1_Clock_Source
bogdanm	84:0b3ab51c8877	268	* @{
bogdanm	84:0b3ab51c8877	269	*/
bogdanm	84:0b3ab51c8877	270	#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	271	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
bogdanm	84:0b3ab51c8877	272	#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
bogdanm	84:0b3ab51c8877	273	#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
bogdanm	84:0b3ab51c8877	274	((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
bogdanm	84:0b3ab51c8877	275	((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
bogdanm	84:0b3ab51c8877	276	/**
bogdanm	84:0b3ab51c8877	277	* @}
bogdanm	84:0b3ab51c8877	278	*/
bogdanm	84:0b3ab51c8877	279
bogdanm	84:0b3ab51c8877	280	/** @defgroup RCCEx_TIM_PRescaler_Selection
bogdanm	84:0b3ab51c8877	281	* @{
bogdanm	84:0b3ab51c8877	282	*/
bogdanm	84:0b3ab51c8877	283	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
bogdanm	84:0b3ab51c8877	284	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
bogdanm	84:0b3ab51c8877	285	/**
bogdanm	84:0b3ab51c8877	286	* @}
bogdanm	84:0b3ab51c8877	287	*/
bogdanm	84:0b3ab51c8877	288
bogdanm	84:0b3ab51c8877	289	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	290	/** @defgroup RCCEx_USB_Clock_Source
bogdanm	84:0b3ab51c8877	291	* @{
bogdanm	84:0b3ab51c8877	292	*/
bogdanm	84:0b3ab51c8877	293	#define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
bogdanm	84:0b3ab51c8877	294	#define RCC_USBCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	295
bogdanm	84:0b3ab51c8877	296	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
bogdanm	84:0b3ab51c8877	297	((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
bogdanm	84:0b3ab51c8877	298	/**
bogdanm	84:0b3ab51c8877	299	* @}
bogdanm	84:0b3ab51c8877	300	*/
bogdanm	84:0b3ab51c8877	301
bogdanm	84:0b3ab51c8877	302	/** @defgroup RCCEx_RNG_Clock_Source
bogdanm	84:0b3ab51c8877	303	* @{
bogdanm	84:0b3ab51c8877	304	*/
bogdanm	84:0b3ab51c8877	305	#define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
bogdanm	84:0b3ab51c8877	306	#define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	307
bogdanm	84:0b3ab51c8877	308	#define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48) \|\| \
bogdanm	84:0b3ab51c8877	309	((SOURCE) == RCC_RNGCLKSOURCE_PLLCLK))
bogdanm	84:0b3ab51c8877	310	/**
bogdanm	84:0b3ab51c8877	311	* @}
bogdanm	84:0b3ab51c8877	312	*/
bogdanm	84:0b3ab51c8877	313
bogdanm	84:0b3ab51c8877	314	/** @defgroup RCCEx_HSI48M_Clock_Source
bogdanm	84:0b3ab51c8877	315	* @{
bogdanm	84:0b3ab51c8877	316	*/
bogdanm	84:0b3ab51c8877	317
bogdanm	84:0b3ab51c8877	318	#define RCC_HSI48M_PLL ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	319	#define RCC_HSI48M_RC48 RCC_CCIPR_HSI48SEL
bogdanm	84:0b3ab51c8877	320
bogdanm	84:0b3ab51c8877	321	#define IS_RCC_HSI48MCLKSOURCE(HSI48MCLK) (((HSI48MCLK) == RCC_HSI48M_PLL) \|\| ((HSI48MCLK) == RCC_HSI48M_RC48))
bogdanm	84:0b3ab51c8877	322
bogdanm	84:0b3ab51c8877	323	/**
bogdanm	84:0b3ab51c8877	324	* @}
bogdanm	84:0b3ab51c8877	325	*/
bogdanm	84:0b3ab51c8877	326	#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
bogdanm	84:0b3ab51c8877	327
bogdanm	84:0b3ab51c8877	328	/** @defgroup RCCEx_LPTIM1_Clock_Source
bogdanm	84:0b3ab51c8877	329	* @{
bogdanm	84:0b3ab51c8877	330	*/
bogdanm	84:0b3ab51c8877	331	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	332	#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
bogdanm	84:0b3ab51c8877	333	#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
bogdanm	84:0b3ab51c8877	334	#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
bogdanm	84:0b3ab51c8877	335
bogdanm	84:0b3ab51c8877	336	#define IS_RCC_LPTIMCLK(LPTIMCLK) (((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_PCLK) \|\| \
bogdanm	84:0b3ab51c8877	337	((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
bogdanm	84:0b3ab51c8877	338	((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
bogdanm	84:0b3ab51c8877	339	((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_LSE))
bogdanm	84:0b3ab51c8877	340	/**
bogdanm	84:0b3ab51c8877	341	* @}
bogdanm	84:0b3ab51c8877	342	*/
bogdanm	84:0b3ab51c8877	343
bogdanm	84:0b3ab51c8877	344	/** @defgroup RCCEx_StopWakeUp_Clock
bogdanm	84:0b3ab51c8877	345	* @{
bogdanm	84:0b3ab51c8877	346	*/
bogdanm	84:0b3ab51c8877	347
bogdanm	84:0b3ab51c8877	348	#define RCC_StopWakeUpClock_MSI ((uint32_t)0x00)
bogdanm	84:0b3ab51c8877	349	#define RCC_StopWakeUpClock_HSI RCC_CFGR_STOPWUCK
bogdanm	84:0b3ab51c8877	350
bogdanm	84:0b3ab51c8877	351	#define IS_RCC_STOPWAKEUP_CLOCK(SOURCE) (((SOURCE) == RCC_StopWakeUpClock_MSI) \|\| \
bogdanm	84:0b3ab51c8877	352	((SOURCE) == RCC_StopWakeUpClock_HSI))
bogdanm	84:0b3ab51c8877	353	/**
bogdanm	84:0b3ab51c8877	354	* @}
bogdanm	84:0b3ab51c8877	355	*/
bogdanm	84:0b3ab51c8877	356
bogdanm	84:0b3ab51c8877	357	/** @defgroup RCCEx_LSEDrive_Configuration
bogdanm	84:0b3ab51c8877	358	* @{
bogdanm	84:0b3ab51c8877	359	*/
bogdanm	84:0b3ab51c8877	360
bogdanm	84:0b3ab51c8877	361	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	362	#define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
bogdanm	84:0b3ab51c8877	363	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
bogdanm	84:0b3ab51c8877	364	#define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
bogdanm	84:0b3ab51c8877	365	#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) \|\| ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
bogdanm	84:0b3ab51c8877	366	((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| ((DRIVE) == RCC_LSEDRIVE_HIGH))
bogdanm	84:0b3ab51c8877	367	/**
bogdanm	84:0b3ab51c8877	368	* @}
bogdanm	84:0b3ab51c8877	369	*/
bogdanm	84:0b3ab51c8877	370
bogdanm	84:0b3ab51c8877	371	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	372	/** @defgroup RCCEx_CRS_SynchroSource
bogdanm	84:0b3ab51c8877	373	* @{
bogdanm	84:0b3ab51c8877	374	*/
bogdanm	84:0b3ab51c8877	375	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal source GPIO /
bogdanm	84:0b3ab51c8877	376	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
bogdanm	84:0b3ab51c8877	377	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
bogdanm	84:0b3ab51c8877	378
bogdanm	84:0b3ab51c8877	379	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
bogdanm	84:0b3ab51c8877	380	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\|\
bogdanm	84:0b3ab51c8877	381	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
bogdanm	84:0b3ab51c8877	382	/**
bogdanm	84:0b3ab51c8877	383	* @}
bogdanm	84:0b3ab51c8877	384	*/
bogdanm	84:0b3ab51c8877	385
bogdanm	84:0b3ab51c8877	386	/** @defgroup RCCEx_CRS_SynchroDivider
bogdanm	84:0b3ab51c8877	387	* @{
bogdanm	84:0b3ab51c8877	388	*/
bogdanm	84:0b3ab51c8877	389	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
bogdanm	84:0b3ab51c8877	390	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
bogdanm	84:0b3ab51c8877	391	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
bogdanm	84:0b3ab51c8877	392	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
bogdanm	84:0b3ab51c8877	393	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
bogdanm	84:0b3ab51c8877	394	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
bogdanm	84:0b3ab51c8877	395	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
bogdanm	84:0b3ab51c8877	396	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
bogdanm	84:0b3ab51c8877	397
bogdanm	84:0b3ab51c8877	398	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\|\
bogdanm	84:0b3ab51c8877	399	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
bogdanm	84:0b3ab51c8877	400	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
bogdanm	84:0b3ab51c8877	401	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
bogdanm	84:0b3ab51c8877	402	/**
bogdanm	84:0b3ab51c8877	403	* @}
bogdanm	84:0b3ab51c8877	404	*/
bogdanm	84:0b3ab51c8877	405
bogdanm	84:0b3ab51c8877	406	/** @defgroup RCCEx_CRS_SynchroPolarity
bogdanm	84:0b3ab51c8877	407	* @{
bogdanm	84:0b3ab51c8877	408	*/
bogdanm	84:0b3ab51c8877	409	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
bogdanm	84:0b3ab51c8877	410	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
bogdanm	84:0b3ab51c8877	411
bogdanm	84:0b3ab51c8877	412	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
bogdanm	84:0b3ab51c8877	413	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
bogdanm	84:0b3ab51c8877	414	/**
bogdanm	84:0b3ab51c8877	415	* @}
bogdanm	84:0b3ab51c8877	416	*/
bogdanm	84:0b3ab51c8877	417
bogdanm	84:0b3ab51c8877	418	/** @defgroup RCCEx_CRS_ReloadValueDefault
bogdanm	84:0b3ab51c8877	419	* @{
bogdanm	84:0b3ab51c8877	420	*/
bogdanm	84:0b3ab51c8877	421	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
bogdanm	84:0b3ab51c8877	422	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
bogdanm	84:0b3ab51c8877	423
bogdanm	84:0b3ab51c8877	424	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
bogdanm	84:0b3ab51c8877	425	/**
bogdanm	84:0b3ab51c8877	426	* @}
bogdanm	84:0b3ab51c8877	427	*/
bogdanm	84:0b3ab51c8877	428
bogdanm	84:0b3ab51c8877	429	/** @defgroup RCCEx_CRS_ErrorLimitDefault
bogdanm	84:0b3ab51c8877	430	* @{
bogdanm	84:0b3ab51c8877	431	*/
bogdanm	84:0b3ab51c8877	432	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
bogdanm	84:0b3ab51c8877	433
bogdanm	84:0b3ab51c8877	434	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
bogdanm	84:0b3ab51c8877	435	/**
bogdanm	84:0b3ab51c8877	436	* @}
bogdanm	84:0b3ab51c8877	437	*/
bogdanm	84:0b3ab51c8877	438
bogdanm	84:0b3ab51c8877	439	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault
bogdanm	84:0b3ab51c8877	440	* @{
bogdanm	84:0b3ab51c8877	441	*/
bogdanm	84:0b3ab51c8877	442	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
bogdanm	84:0b3ab51c8877	443	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
bogdanm	84:0b3ab51c8877	444	corresponds to a higher output frequency */
bogdanm	84:0b3ab51c8877	445
bogdanm	84:0b3ab51c8877	446	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
bogdanm	84:0b3ab51c8877	447	/**
bogdanm	84:0b3ab51c8877	448	* @}
bogdanm	84:0b3ab51c8877	449	*/
bogdanm	84:0b3ab51c8877	450
bogdanm	84:0b3ab51c8877	451	/** @defgroup RCCEx_CRS_FreqErrorDirection
bogdanm	84:0b3ab51c8877	452	* @{
bogdanm	84:0b3ab51c8877	453	*/
bogdanm	84:0b3ab51c8877	454	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
bogdanm	84:0b3ab51c8877	455	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
bogdanm	84:0b3ab51c8877	456
bogdanm	84:0b3ab51c8877	457	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
bogdanm	84:0b3ab51c8877	458	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
bogdanm	84:0b3ab51c8877	459	/**
bogdanm	84:0b3ab51c8877	460	* @}
bogdanm	84:0b3ab51c8877	461	*/
bogdanm	84:0b3ab51c8877	462
bogdanm	84:0b3ab51c8877	463	/** @defgroup RCCEx_CRS_Interrupt_Sources
bogdanm	84:0b3ab51c8877	464	* @{
bogdanm	84:0b3ab51c8877	465	*/
bogdanm	84:0b3ab51c8877	466	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
bogdanm	84:0b3ab51c8877	467	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
bogdanm	84:0b3ab51c8877	468	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
bogdanm	84:0b3ab51c8877	469	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
bogdanm	84:0b3ab51c8877	470	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	84:0b3ab51c8877	471	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	84:0b3ab51c8877	472	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	84:0b3ab51c8877	473
bogdanm	84:0b3ab51c8877	474	/**
bogdanm	84:0b3ab51c8877	475	* @}
bogdanm	84:0b3ab51c8877	476	*/
bogdanm	84:0b3ab51c8877	477
bogdanm	84:0b3ab51c8877	478	/** @defgroup RCCEx_CRS_Flags
bogdanm	84:0b3ab51c8877	479	* @{
bogdanm	84:0b3ab51c8877	480	*/
bogdanm	84:0b3ab51c8877	481	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
bogdanm	84:0b3ab51c8877	482	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
bogdanm	84:0b3ab51c8877	483	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
bogdanm	84:0b3ab51c8877	484	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
bogdanm	84:0b3ab51c8877	485	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	84:0b3ab51c8877	486	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	84:0b3ab51c8877	487	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	84:0b3ab51c8877	488
bogdanm	84:0b3ab51c8877	489	/**
bogdanm	84:0b3ab51c8877	490	* @}
bogdanm	84:0b3ab51c8877	491	*/
bogdanm	84:0b3ab51c8877	492
bogdanm	84:0b3ab51c8877	493	#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
bogdanm	84:0b3ab51c8877	494	/**
bogdanm	84:0b3ab51c8877	495	* @}
bogdanm	84:0b3ab51c8877	496	*/
bogdanm	84:0b3ab51c8877	497
bogdanm	84:0b3ab51c8877	498	/* Exported macro ------------------------------------------------------------*/
bogdanm	84:0b3ab51c8877	499	/** @defgroup RCCEx_Exported_Macros
bogdanm	84:0b3ab51c8877	500	* @{
bogdanm	84:0b3ab51c8877	501	*/
bogdanm	84:0b3ab51c8877	502
bogdanm	84:0b3ab51c8877	503	/** @brief Enable or disable the AHB peripheral clock.
bogdanm	84:0b3ab51c8877	504	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	84:0b3ab51c8877	505	* is disabled and the application software has to enable this clock before
bogdanm	84:0b3ab51c8877	506	* using it.
bogdanm	84:0b3ab51c8877	507	*/
bogdanm	84:0b3ab51c8877	508
bogdanm	84:0b3ab51c8877	509	#if defined(STM32L062xx) \|\| defined(STM32L063xx)
bogdanm	84:0b3ab51c8877	510	#define __CRYP_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRYPEN))
bogdanm	84:0b3ab51c8877	511	#define __CRYP_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRYPEN))
bogdanm	84:0b3ab51c8877	512	#endif /* STM32L062xx \|\| STM32L063xx */
bogdanm	84:0b3ab51c8877	513
bogdanm	84:0b3ab51c8877	514	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	515	#define __TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
bogdanm	84:0b3ab51c8877	516	#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_TSCEN))
bogdanm	84:0b3ab51c8877	517
bogdanm	84:0b3ab51c8877	518	#define __RNG_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_RNGEN))
bogdanm	84:0b3ab51c8877	519	#define __RNG_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_RNGEN))
bogdanm	84:0b3ab51c8877	520	#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
bogdanm	84:0b3ab51c8877	521
bogdanm	84:0b3ab51c8877	522	/** @brief Enable or disable the APB1 peripheral clock.
bogdanm	84:0b3ab51c8877	523	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	84:0b3ab51c8877	524	* is disabled and the application software has to enable this clock before
bogdanm	84:0b3ab51c8877	525	* using it.
bogdanm	84:0b3ab51c8877	526	*/
bogdanm	84:0b3ab51c8877	527
bogdanm	84:0b3ab51c8877	528	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	529	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
bogdanm	84:0b3ab51c8877	530	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN))
bogdanm	84:0b3ab51c8877	531	#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
bogdanm	84:0b3ab51c8877	532
bogdanm	84:0b3ab51c8877	533	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	534	#define __CRS_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CRSEN))
bogdanm	84:0b3ab51c8877	535	#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
bogdanm	84:0b3ab51c8877	536	#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
bogdanm	84:0b3ab51c8877	537
bogdanm	84:0b3ab51c8877	538
bogdanm	84:0b3ab51c8877	539	#if defined(STM32L053xx) \|\| defined(STM32L063xx)
bogdanm	84:0b3ab51c8877	540	#define __LCD_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LCDEN))
bogdanm	84:0b3ab51c8877	541	#define __LCD_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN))
bogdanm	84:0b3ab51c8877	542	#endif /* STM32L053xx \|\| STM32L063xx */
bogdanm	84:0b3ab51c8877	543
bogdanm	84:0b3ab51c8877	544	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	84:0b3ab51c8877	545	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	84:0b3ab51c8877	546	defined(STM32L051xx) \|\| defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	547	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
bogdanm	84:0b3ab51c8877	548	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
bogdanm	84:0b3ab51c8877	549	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
bogdanm	84:0b3ab51c8877	550	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
bogdanm	84:0b3ab51c8877	551	#define __LPUART1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPUART1EN))
bogdanm	84:0b3ab51c8877	552	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
bogdanm	84:0b3ab51c8877	553	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
bogdanm	84:0b3ab51c8877	554	#define __DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
bogdanm	84:0b3ab51c8877	555	#define __LPTIM1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPTIM1EN))
bogdanm	84:0b3ab51c8877	556
bogdanm	84:0b3ab51c8877	557	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
bogdanm	84:0b3ab51c8877	558	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
bogdanm	84:0b3ab51c8877	559	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
bogdanm	84:0b3ab51c8877	560	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
bogdanm	84:0b3ab51c8877	561	#define __LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
bogdanm	84:0b3ab51c8877	562	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
bogdanm	84:0b3ab51c8877	563	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
bogdanm	84:0b3ab51c8877	564	#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
bogdanm	84:0b3ab51c8877	565	#define __LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
bogdanm	84:0b3ab51c8877	566	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	84:0b3ab51c8877	567	/* STM32L052xx \|\| STM32L062xx \|\| */
bogdanm	84:0b3ab51c8877	568	/* STM32L053xx \|\| STM32L063xx \|\| */
bogdanm	84:0b3ab51c8877	569
bogdanm	84:0b3ab51c8877	570	/** @brief Enable or disable the APB2 peripheral clock.
bogdanm	84:0b3ab51c8877	571	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	84:0b3ab51c8877	572	* is disabled and the application software has to enable this clock before
bogdanm	84:0b3ab51c8877	573	* using it.
bogdanm	84:0b3ab51c8877	574	*/
bogdanm	84:0b3ab51c8877	575
bogdanm	84:0b3ab51c8877	576	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	84:0b3ab51c8877	577	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	84:0b3ab51c8877	578	defined(STM32L051xx) \|\| defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	579	#define __TIM21_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM21EN))
bogdanm	84:0b3ab51c8877	580	#define __TIM22_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM22EN))
bogdanm	84:0b3ab51c8877	581	#define __FIREWALL_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_MIFIEN))
bogdanm	84:0b3ab51c8877	582	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
bogdanm	84:0b3ab51c8877	583	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
bogdanm	84:0b3ab51c8877	584	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
bogdanm	84:0b3ab51c8877	585
bogdanm	84:0b3ab51c8877	586	#define __TIM21_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM21EN))
bogdanm	84:0b3ab51c8877	587	#define __TIM22_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM22EN))
bogdanm	84:0b3ab51c8877	588	#define __FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_MIFIEN))
bogdanm	84:0b3ab51c8877	589	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_ADC1EN))
bogdanm	84:0b3ab51c8877	590	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SPI1EN))
bogdanm	84:0b3ab51c8877	591	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_USART1EN))
bogdanm	84:0b3ab51c8877	592	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	84:0b3ab51c8877	593	/* STM32L052xx \|\| STM32L062xx \|\| */
bogdanm	84:0b3ab51c8877	594	/* STM32L053xx \|\| STM32L063xx \|\| */
bogdanm	84:0b3ab51c8877	595
bogdanm	84:0b3ab51c8877	596	/** @brief Force or release AHB peripheral reset.
bogdanm	84:0b3ab51c8877	597	*/
bogdanm	84:0b3ab51c8877	598	#if defined(STM32L062xx) \|\| defined(STM32L063xx)
bogdanm	84:0b3ab51c8877	599	#define __CRYP_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRYPRST))
bogdanm	84:0b3ab51c8877	600	#define __CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST))
bogdanm	84:0b3ab51c8877	601	#endif /* STM32L062xx \|\| STM32L063xx */
bogdanm	84:0b3ab51c8877	602
bogdanm	84:0b3ab51c8877	603	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	604	#define __TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
bogdanm	84:0b3ab51c8877	605	#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST))
bogdanm	84:0b3ab51c8877	606	#define __RNG_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_RNGRST))
bogdanm	84:0b3ab51c8877	607	#define __RNG_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST))
bogdanm	84:0b3ab51c8877	608	#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
bogdanm	84:0b3ab51c8877	609
bogdanm	84:0b3ab51c8877	610	/** @brief Force or release APB1 peripheral reset.
bogdanm	84:0b3ab51c8877	611	*/
bogdanm	84:0b3ab51c8877	612	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	84:0b3ab51c8877	613	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	84:0b3ab51c8877	614	defined(STM32L051xx) \|\| defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	615	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	84:0b3ab51c8877	616	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	84:0b3ab51c8877	617	#define __LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
bogdanm	84:0b3ab51c8877	618	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
bogdanm	84:0b3ab51c8877	619	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	84:0b3ab51c8877	620	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	84:0b3ab51c8877	621	#define __LPUART1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPUART1RST))
bogdanm	84:0b3ab51c8877	622	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	84:0b3ab51c8877	623	#define __DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	84:0b3ab51c8877	624
bogdanm	84:0b3ab51c8877	625	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
bogdanm	84:0b3ab51c8877	626	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
bogdanm	84:0b3ab51c8877	627	#define __LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
bogdanm	84:0b3ab51c8877	628	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
bogdanm	84:0b3ab51c8877	629	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
bogdanm	84:0b3ab51c8877	630	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
bogdanm	84:0b3ab51c8877	631	#define __LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
bogdanm	84:0b3ab51c8877	632	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
bogdanm	84:0b3ab51c8877	633	#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
bogdanm	84:0b3ab51c8877	634	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	84:0b3ab51c8877	635	/* STM32L052xx \|\| STM32L062xx \|\| */
bogdanm	84:0b3ab51c8877	636	/* STM32L053xx \|\| STM32L063xx \|\| */
bogdanm	84:0b3ab51c8877	637
bogdanm	84:0b3ab51c8877	638	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	639	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
bogdanm	84:0b3ab51c8877	640	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST))
bogdanm	84:0b3ab51c8877	641	#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
bogdanm	84:0b3ab51c8877	642
bogdanm	84:0b3ab51c8877	643	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	644	#define __CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
bogdanm	84:0b3ab51c8877	645	#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
bogdanm	84:0b3ab51c8877	646	#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
bogdanm	84:0b3ab51c8877	647
bogdanm	84:0b3ab51c8877	648	#if defined(STM32L053xx) \|\| defined(STM32L063xx)
bogdanm	84:0b3ab51c8877	649	#define __LCD_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LCDRST))
bogdanm	84:0b3ab51c8877	650	#define __LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST))
bogdanm	84:0b3ab51c8877	651	#endif /* STM32L053xx \|\| STM32L063xx */
bogdanm	84:0b3ab51c8877	652
bogdanm	84:0b3ab51c8877	653	/** @brief Force or release APB2 peripheral reset.
bogdanm	84:0b3ab51c8877	654	*/
bogdanm	84:0b3ab51c8877	655	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	84:0b3ab51c8877	656	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	84:0b3ab51c8877	657	defined(STM32L051xx) \|\| defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	658	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
bogdanm	84:0b3ab51c8877	659	#define __ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
bogdanm	84:0b3ab51c8877	660	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
bogdanm	84:0b3ab51c8877	661	#define __TIM21_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM21RST))
bogdanm	84:0b3ab51c8877	662	#define __TIM22_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM22RST))
bogdanm	84:0b3ab51c8877	663
bogdanm	84:0b3ab51c8877	664	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST))
bogdanm	84:0b3ab51c8877	665	#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST))
bogdanm	84:0b3ab51c8877	666	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST))
bogdanm	84:0b3ab51c8877	667	#define __TIM21_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST))
bogdanm	84:0b3ab51c8877	668	#define __TIM22_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST))
bogdanm	84:0b3ab51c8877	669	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	84:0b3ab51c8877	670	/* STM32L052xx \|\| STM32L062xx \|\| */
bogdanm	84:0b3ab51c8877	671	/* STM32L053xx \|\| STM32L063xx \|\| */
bogdanm	84:0b3ab51c8877	672
bogdanm	84:0b3ab51c8877	673	/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
bogdanm	84:0b3ab51c8877	674	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	84:0b3ab51c8877	675	* power consumption.
bogdanm	84:0b3ab51c8877	676	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	84:0b3ab51c8877	677	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	84:0b3ab51c8877	678	*/
bogdanm	84:0b3ab51c8877	679
bogdanm	84:0b3ab51c8877	680	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	681	#define __TSC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_TSCSMEN))
bogdanm	84:0b3ab51c8877	682	#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_RNGSMEN))
bogdanm	84:0b3ab51c8877	683	#define __TSC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_TSCSMEN))
bogdanm	84:0b3ab51c8877	684	#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_RNGSMEN))
bogdanm	84:0b3ab51c8877	685	#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
bogdanm	84:0b3ab51c8877	686
bogdanm	84:0b3ab51c8877	687	#if defined(STM32L062xx) \|\| defined(STM32L063xx)
bogdanm	84:0b3ab51c8877	688	#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBSMENR_CRYPSMEN))
bogdanm	84:0b3ab51c8877	689	#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~ (RCC_AHBSMENR_CRYPSMEN))
bogdanm	84:0b3ab51c8877	690	#endif /* STM32L062xx \|\| STM32L063xx */
bogdanm	84:0b3ab51c8877	691
bogdanm	84:0b3ab51c8877	692
bogdanm	84:0b3ab51c8877	693	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	84:0b3ab51c8877	694	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	84:0b3ab51c8877	695	* power consumption.
bogdanm	84:0b3ab51c8877	696	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	84:0b3ab51c8877	697	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	84:0b3ab51c8877	698	*/
bogdanm	84:0b3ab51c8877	699
bogdanm	84:0b3ab51c8877	700	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	84:0b3ab51c8877	701	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	84:0b3ab51c8877	702	defined(STM32L051xx) \|\| defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	703	#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM2SMEN))
bogdanm	84:0b3ab51c8877	704	#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM6SMEN))
bogdanm	84:0b3ab51c8877	705	#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_SPI2SMEN))
bogdanm	84:0b3ab51c8877	706	#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART2SMEN))
bogdanm	84:0b3ab51c8877	707	#define __LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPUART1SMEN))
bogdanm	84:0b3ab51c8877	708	#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C1SMEN))
bogdanm	84:0b3ab51c8877	709	#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C2SMEN))
bogdanm	84:0b3ab51c8877	710	#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_DACSMEN))
bogdanm	84:0b3ab51c8877	711	#define __LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	84:0b3ab51c8877	712
bogdanm	84:0b3ab51c8877	713	#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
bogdanm	84:0b3ab51c8877	714	#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
bogdanm	84:0b3ab51c8877	715	#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
bogdanm	84:0b3ab51c8877	716	#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
bogdanm	84:0b3ab51c8877	717	#define __LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
bogdanm	84:0b3ab51c8877	718	#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
bogdanm	84:0b3ab51c8877	719	#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
bogdanm	84:0b3ab51c8877	720	#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
bogdanm	84:0b3ab51c8877	721	#define __LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	84:0b3ab51c8877	722	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	84:0b3ab51c8877	723	/* STM32L052xx \|\| STM32L062xx \|\| */
bogdanm	84:0b3ab51c8877	724	/* STM32L053xx \|\| STM32L063xx \|\| */
bogdanm	84:0b3ab51c8877	725
bogdanm	84:0b3ab51c8877	726	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	727	#define __USB_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USBSMEN))
bogdanm	84:0b3ab51c8877	728	#define __USB_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN))
bogdanm	84:0b3ab51c8877	729
bogdanm	84:0b3ab51c8877	730	#define __CRS_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_CRSSMEN))
bogdanm	84:0b3ab51c8877	731	#define __CRS_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN))
bogdanm	84:0b3ab51c8877	732	#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
bogdanm	84:0b3ab51c8877	733
bogdanm	84:0b3ab51c8877	734	#if defined(STM32L053xx) \|\| defined(STM32L063xx)
bogdanm	84:0b3ab51c8877	735	#define __LCD_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LCDSMEN))
bogdanm	84:0b3ab51c8877	736	#define __LCD_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN))
bogdanm	84:0b3ab51c8877	737	#endif /* STM32L053xx \|\| STM32L063xx */
bogdanm	84:0b3ab51c8877	738
bogdanm	84:0b3ab51c8877	739	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	84:0b3ab51c8877	740	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	84:0b3ab51c8877	741	* power consumption.
bogdanm	84:0b3ab51c8877	742	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	84:0b3ab51c8877	743	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	84:0b3ab51c8877	744	*/
bogdanm	84:0b3ab51c8877	745	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	84:0b3ab51c8877	746	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	84:0b3ab51c8877	747	defined(STM32L051xx) \|\| defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	748	#define __TIM21_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_TIM21SMEN))
bogdanm	84:0b3ab51c8877	749	#define __TIM22_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_TIM22SMEN))
bogdanm	84:0b3ab51c8877	750	#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_ADC1SMEN))
bogdanm	84:0b3ab51c8877	751	#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_SPI1SMEN))
bogdanm	84:0b3ab51c8877	752	#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_USART1SMEN))
bogdanm	84:0b3ab51c8877	753
bogdanm	84:0b3ab51c8877	754	#define __TIM21_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM21SMEN))
bogdanm	84:0b3ab51c8877	755	#define __TIM22_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM22SMEN))
bogdanm	84:0b3ab51c8877	756	#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_ADC1SMEN))
bogdanm	84:0b3ab51c8877	757	#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SPI1SMEN))
bogdanm	84:0b3ab51c8877	758	#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_USART1SMEN))
bogdanm	84:0b3ab51c8877	759	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	84:0b3ab51c8877	760	/* STM32L052xx \|\| STM32L062xx \|\| */
bogdanm	84:0b3ab51c8877	761	/* STM32L053xx \|\| STM32L063xx \|\| */
bogdanm	84:0b3ab51c8877	762
bogdanm	84:0b3ab51c8877	763	/** @brief macro to configure the I2C1 clock (I2C1CLK).
bogdanm	84:0b3ab51c8877	764	*
bogdanm	84:0b3ab51c8877	765	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
bogdanm	84:0b3ab51c8877	766	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	767	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
bogdanm	84:0b3ab51c8877	768	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	84:0b3ab51c8877	769	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	84:0b3ab51c8877	770	*/
bogdanm	84:0b3ab51c8877	771	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
bogdanm	84:0b3ab51c8877	772	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1CLKSource__))
bogdanm	84:0b3ab51c8877	773
bogdanm	84:0b3ab51c8877	774	/** @brief macro to get the I2C1 clock source.
bogdanm	84:0b3ab51c8877	775	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	776	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
bogdanm	84:0b3ab51c8877	777	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	84:0b3ab51c8877	778	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	84:0b3ab51c8877	779	*/
bogdanm	84:0b3ab51c8877	780	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
bogdanm	84:0b3ab51c8877	781
bogdanm	84:0b3ab51c8877	782	/** @brief macro to configure the USART1 clock (USART1CLK).
bogdanm	84:0b3ab51c8877	783	*
bogdanm	84:0b3ab51c8877	784	* @param __USART1CLKSource__: specifies the USART1 clock source.
bogdanm	84:0b3ab51c8877	785	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	786	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
bogdanm	84:0b3ab51c8877	787	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	84:0b3ab51c8877	788	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	84:0b3ab51c8877	789	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	84:0b3ab51c8877	790	*/
bogdanm	84:0b3ab51c8877	791	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
bogdanm	84:0b3ab51c8877	792	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1CLKSource__))
bogdanm	84:0b3ab51c8877	793
bogdanm	84:0b3ab51c8877	794	/** @brief macro to get the USART1 clock source.
bogdanm	84:0b3ab51c8877	795	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	796	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
bogdanm	84:0b3ab51c8877	797	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	84:0b3ab51c8877	798	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	84:0b3ab51c8877	799	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	84:0b3ab51c8877	800	*/
bogdanm	84:0b3ab51c8877	801	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
bogdanm	84:0b3ab51c8877	802
bogdanm	84:0b3ab51c8877	803	/** @brief macro to configure the USART2 clock (USART2CLK).
bogdanm	84:0b3ab51c8877	804	*
bogdanm	84:0b3ab51c8877	805	* @param __USART2CLKSource__: specifies the USART2 clock source.
bogdanm	84:0b3ab51c8877	806	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	807	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	84:0b3ab51c8877	808	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	84:0b3ab51c8877	809	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	84:0b3ab51c8877	810	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	84:0b3ab51c8877	811	*/
bogdanm	84:0b3ab51c8877	812	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
bogdanm	84:0b3ab51c8877	813	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2CLKSource__))
bogdanm	84:0b3ab51c8877	814
bogdanm	84:0b3ab51c8877	815	/** @brief macro to get the USART2 clock source.
bogdanm	84:0b3ab51c8877	816	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	817	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	84:0b3ab51c8877	818	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	84:0b3ab51c8877	819	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	84:0b3ab51c8877	820	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	84:0b3ab51c8877	821	*/
bogdanm	84:0b3ab51c8877	822	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
bogdanm	84:0b3ab51c8877	823
bogdanm	84:0b3ab51c8877	824	/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
bogdanm	84:0b3ab51c8877	825	*
bogdanm	84:0b3ab51c8877	826	* @param __LPUART1CLKSource__: specifies the LPUART1 clock source.
bogdanm	84:0b3ab51c8877	827	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	828	* @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	829	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	830	* @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	831	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	832	*/
bogdanm	84:0b3ab51c8877	833	#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
bogdanm	84:0b3ab51c8877	834	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
bogdanm	84:0b3ab51c8877	835
bogdanm	84:0b3ab51c8877	836	/** @brief macro to get the LPUART1 clock source.
bogdanm	84:0b3ab51c8877	837	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	838	* @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	839	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	840	* @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	841	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	842	*/
bogdanm	84:0b3ab51c8877	843	#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
bogdanm	84:0b3ab51c8877	844
bogdanm	84:0b3ab51c8877	845	/** @brief macro to configure the LPTIM1 clock (LPTIM1CLK).
bogdanm	84:0b3ab51c8877	846	*
bogdanm	84:0b3ab51c8877	847	* @param __LPTIM1CLKSource__: specifies the LPTIM1 clock source.
bogdanm	84:0b3ab51c8877	848	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	849	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
bogdanm	84:0b3ab51c8877	850	* @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock
bogdanm	84:0b3ab51c8877	851	* @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock
bogdanm	84:0b3ab51c8877	852	* @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock
bogdanm	84:0b3ab51c8877	853	*/
bogdanm	84:0b3ab51c8877	854	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
bogdanm	84:0b3ab51c8877	855	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
bogdanm	84:0b3ab51c8877	856
bogdanm	84:0b3ab51c8877	857	/** @brief macro to get the LPTIM1 clock source.
bogdanm	84:0b3ab51c8877	858	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	859	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	860	* @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	861	* @arg RCC_LPTIM1CLKSOURCE_HSI : System Clock selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	862	* @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	863	*/
bogdanm	84:0b3ab51c8877	864	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
bogdanm	84:0b3ab51c8877	865
bogdanm	84:0b3ab51c8877	866	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	867	/** @brief Macro to configure the USB clock (USBCLK).
bogdanm	84:0b3ab51c8877	868	* @param __USBCLKSource__: specifies the USB clock source.
bogdanm	84:0b3ab51c8877	869	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	870	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
bogdanm	84:0b3ab51c8877	871	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	84:0b3ab51c8877	872	*/
bogdanm	84:0b3ab51c8877	873	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
bogdanm	84:0b3ab51c8877	874	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USBCLKSource__))
bogdanm	84:0b3ab51c8877	875
bogdanm	84:0b3ab51c8877	876	/** @brief Macro to get the USB clock source.
bogdanm	84:0b3ab51c8877	877	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	878	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
bogdanm	84:0b3ab51c8877	879	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	84:0b3ab51c8877	880	*/
bogdanm	84:0b3ab51c8877	881	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
bogdanm	84:0b3ab51c8877	882
bogdanm	84:0b3ab51c8877	883	/** @brief Macro to configure the RNG clock (RNGCLK).
bogdanm	84:0b3ab51c8877	884	* @param __RNGCLKSource__: specifies the USB clock source.
bogdanm	84:0b3ab51c8877	885	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	886	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
bogdanm	84:0b3ab51c8877	887	* @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
bogdanm	84:0b3ab51c8877	888	*/
bogdanm	84:0b3ab51c8877	889	#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
bogdanm	84:0b3ab51c8877	890	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNGCLKSource__))
bogdanm	84:0b3ab51c8877	891
bogdanm	84:0b3ab51c8877	892	/** @brief Macro to get the RNG clock source.
bogdanm	84:0b3ab51c8877	893	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	894	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
bogdanm	84:0b3ab51c8877	895	* @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
bogdanm	84:0b3ab51c8877	896	*/
bogdanm	84:0b3ab51c8877	897	#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
bogdanm	84:0b3ab51c8877	898
bogdanm	84:0b3ab51c8877	899	/** @brief macro to select the HSI48M clock source
bogdanm	84:0b3ab51c8877	900	* @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or
bogdanm	84:0b3ab51c8877	901	* __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources.
bogdanm	84:0b3ab51c8877	902	*
bogdanm	84:0b3ab51c8877	903	* @param __HSI48MCLKSource__: specifies the HSI48M clock source dedicated for
bogdanm	84:0b3ab51c8877	904	* USB an RNG peripherals.
bogdanm	84:0b3ab51c8877	905	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	906	* @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
bogdanm	84:0b3ab51c8877	907	* @arg RCC_HSI48M_RC48: 48MHZ issued from internal HSI48 oscillator.
bogdanm	84:0b3ab51c8877	908	*/
bogdanm	84:0b3ab51c8877	909	#define __HAL_RCC_HSI48M_CONFIG(__HSI48MCLKSource__) \
bogdanm	84:0b3ab51c8877	910	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48MCLKSource__))
bogdanm	84:0b3ab51c8877	911
bogdanm	84:0b3ab51c8877	912	/** @brief macro to get the HSI48M clock source.
bogdanm	84:0b3ab51c8877	913	* @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or
bogdanm	84:0b3ab51c8877	914	* __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources.
bogdanm	84:0b3ab51c8877	915	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	916	* @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
bogdanm	84:0b3ab51c8877	917	* @arg RCC_HSI48M_RC48: 48MHZ issued from internal HSI48 oscillator.
bogdanm	84:0b3ab51c8877	918	*/
bogdanm	84:0b3ab51c8877	919	#define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
bogdanm	84:0b3ab51c8877	920	#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
bogdanm	84:0b3ab51c8877	921
bogdanm	84:0b3ab51c8877	922	/**
bogdanm	84:0b3ab51c8877	923	* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
bogdanm	84:0b3ab51c8877	924	* in STOP mode to be quickly available as kernel clock for USART and I2C.
bogdanm	84:0b3ab51c8877	925	* @note The Enable of this function has not effect on the HSION bit.
bogdanm	84:0b3ab51c8877	926	* This parameter can be: ENABLE or DISABLE.
bogdanm	84:0b3ab51c8877	927	* @retval None
bogdanm	84:0b3ab51c8877	928	*/
bogdanm	84:0b3ab51c8877	929	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
bogdanm	84:0b3ab51c8877	930	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
bogdanm	84:0b3ab51c8877	931
bogdanm	84:0b3ab51c8877	932	/**
bogdanm	84:0b3ab51c8877	933	* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
bogdanm	84:0b3ab51c8877	934	* @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
bogdanm	84:0b3ab51c8877	935	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	936	* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
bogdanm	84:0b3ab51c8877	937	* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
bogdanm	84:0b3ab51c8877	938	* @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
bogdanm	84:0b3ab51c8877	939	* @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
bogdanm	84:0b3ab51c8877	940	* @retval None
bogdanm	84:0b3ab51c8877	941	*/
bogdanm	84:0b3ab51c8877	942	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDrive__) (MODIFY_REG(RCC->CSR,\
bogdanm	84:0b3ab51c8877	943	RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDrive__) ))
bogdanm	84:0b3ab51c8877	944
bogdanm	84:0b3ab51c8877	945	/**
bogdanm	84:0b3ab51c8877	946	* @brief Macro to configures the wake up from stop clock.
bogdanm	84:0b3ab51c8877	947	* @param RCC_STOPWUCLK: specifies the clock source used after wake up from stop
bogdanm	84:0b3ab51c8877	948	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	949	* @arg RCC_StopWakeUpClock_MSI: MSI selected as system clock source
bogdanm	84:0b3ab51c8877	950	* @arg RCC_StopWakeUpClock_HSI: HSI selected as system clock source
bogdanm	84:0b3ab51c8877	951	* @retval None
bogdanm	84:0b3ab51c8877	952	*/
bogdanm	84:0b3ab51c8877	953	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
bogdanm	84:0b3ab51c8877	954	RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
bogdanm	84:0b3ab51c8877	955
bogdanm	84:0b3ab51c8877	956	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	957	/**
bogdanm	84:0b3ab51c8877	958	* @brief Enables the specified CRS interrupts.
bogdanm	84:0b3ab51c8877	959	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
bogdanm	84:0b3ab51c8877	960	* This parameter can be any combination of the following values:
bogdanm	84:0b3ab51c8877	961	* @arg RCC_CRS_IT_SYNCOK
bogdanm	84:0b3ab51c8877	962	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	84:0b3ab51c8877	963	* @arg RCC_CRS_IT_ERR
bogdanm	84:0b3ab51c8877	964	* @arg RCC_CRS_IT_ESYNC
bogdanm	84:0b3ab51c8877	965	* @retval None
bogdanm	84:0b3ab51c8877	966	*/
bogdanm	84:0b3ab51c8877	967	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
bogdanm	84:0b3ab51c8877	968
bogdanm	84:0b3ab51c8877	969	/**
bogdanm	84:0b3ab51c8877	970	* @brief Disables the specified CRS interrupts.
bogdanm	84:0b3ab51c8877	971	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
bogdanm	84:0b3ab51c8877	972	* This parameter can be any combination of the following values:
bogdanm	84:0b3ab51c8877	973	* @arg RCC_CRS_IT_SYNCOK
bogdanm	84:0b3ab51c8877	974	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	84:0b3ab51c8877	975	* @arg RCC_CRS_IT_ERR
bogdanm	84:0b3ab51c8877	976	* @arg RCC_CRS_IT_ESYNC
bogdanm	84:0b3ab51c8877	977	* @retval None
bogdanm	84:0b3ab51c8877	978	*/
bogdanm	84:0b3ab51c8877	979	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
bogdanm	84:0b3ab51c8877	980
bogdanm	84:0b3ab51c8877	981	/** @brief Check the CRS's interrupt has occurred or not.
bogdanm	84:0b3ab51c8877	982	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
bogdanm	84:0b3ab51c8877	983	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	984	* @arg RCC_CRS_IT_SYNCOK
bogdanm	84:0b3ab51c8877	985	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	84:0b3ab51c8877	986	* @arg RCC_CRS_IT_ERR
bogdanm	84:0b3ab51c8877	987	* @arg RCC_CRS_IT_ESYNC
bogdanm	84:0b3ab51c8877	988	* @retval The new state of __INTERRUPT__ (SET or RESET).
bogdanm	84:0b3ab51c8877	989	*/
bogdanm	84:0b3ab51c8877	990	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
bogdanm	84:0b3ab51c8877	991
bogdanm	84:0b3ab51c8877	992	/** @brief Clear the CRS's interrupt pending bits
bogdanm	84:0b3ab51c8877	993	* bits to clear the selected interrupt pending bits.
bogdanm	84:0b3ab51c8877	994	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	84:0b3ab51c8877	995	* This parameter can be any combination of the following values:
bogdanm	84:0b3ab51c8877	996	* @arg RCC_CRS_IT_SYNCOK
bogdanm	84:0b3ab51c8877	997	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	84:0b3ab51c8877	998	* @arg RCC_CRS_IT_ERR
bogdanm	84:0b3ab51c8877	999	* @arg RCC_CRS_IT_ESYNC
bogdanm	84:0b3ab51c8877	1000	* @arg RCC_CRS_IT_TRIMOVF
bogdanm	84:0b3ab51c8877	1001	* @arg RCC_CRS_IT_SYNCERR
bogdanm	84:0b3ab51c8877	1002	* @arg RCC_CRS_IT_SYNCMISS
bogdanm	84:0b3ab51c8877	1003	*/
bogdanm	84:0b3ab51c8877	1004	/* CRS IT Error Mask */
bogdanm	84:0b3ab51c8877	1005	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
bogdanm	84:0b3ab51c8877	1006
bogdanm	84:0b3ab51c8877	1007	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	84:0b3ab51c8877	1008	(CRS->ICR \|= (__INTERRUPT__)))
bogdanm	84:0b3ab51c8877	1009
bogdanm	84:0b3ab51c8877	1010	/**
bogdanm	84:0b3ab51c8877	1011	* @brief Checks whether the specified CRS flag is set or not.
bogdanm	84:0b3ab51c8877	1012	* @param _FLAG_: specifies the flag to check.
bogdanm	84:0b3ab51c8877	1013	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1014	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	84:0b3ab51c8877	1015	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	84:0b3ab51c8877	1016	* @arg RCC_CRS_FLAG_ERR
bogdanm	84:0b3ab51c8877	1017	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	84:0b3ab51c8877	1018	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	84:0b3ab51c8877	1019	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	84:0b3ab51c8877	1020	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	84:0b3ab51c8877	1021	* @retval The new state of _FLAG_ (TRUE or FALSE).
bogdanm	84:0b3ab51c8877	1022	*/
bogdanm	84:0b3ab51c8877	1023	#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
bogdanm	84:0b3ab51c8877	1024
bogdanm	84:0b3ab51c8877	1025	/**
bogdanm	84:0b3ab51c8877	1026	* @brief Clears the CRS specified FLAG.
bogdanm	84:0b3ab51c8877	1027	* @param _FLAG_: specifies the flag to clear.
bogdanm	84:0b3ab51c8877	1028	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1029	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	84:0b3ab51c8877	1030	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	84:0b3ab51c8877	1031	* @arg RCC_CRS_FLAG_ERR
bogdanm	84:0b3ab51c8877	1032	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	84:0b3ab51c8877	1033	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	84:0b3ab51c8877	1034	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	84:0b3ab51c8877	1035	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	84:0b3ab51c8877	1036	* @retval None
bogdanm	84:0b3ab51c8877	1037	*/
bogdanm	84:0b3ab51c8877	1038
bogdanm	84:0b3ab51c8877	1039	/* CRS Flag Error Mask */
bogdanm	84:0b3ab51c8877	1040	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
bogdanm	84:0b3ab51c8877	1041
bogdanm	84:0b3ab51c8877	1042	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	84:0b3ab51c8877	1043	(CRS->ICR \|= (__FLAG__)))
bogdanm	84:0b3ab51c8877	1044
bogdanm	84:0b3ab51c8877	1045
bogdanm	84:0b3ab51c8877	1046	/**
bogdanm	84:0b3ab51c8877	1047	* @brief Enables the oscillator clock for frequency error counter.
bogdanm	84:0b3ab51c8877	1048	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	84:0b3ab51c8877	1049	* @param None
bogdanm	84:0b3ab51c8877	1050	* @retval None
bogdanm	84:0b3ab51c8877	1051	*/
bogdanm	84:0b3ab51c8877	1052	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
bogdanm	84:0b3ab51c8877	1053
bogdanm	84:0b3ab51c8877	1054	/**
bogdanm	84:0b3ab51c8877	1055	* @brief Disables the oscillator clock for frequency error counter.
bogdanm	84:0b3ab51c8877	1056	* @param None
bogdanm	84:0b3ab51c8877	1057	* @retval None
bogdanm	84:0b3ab51c8877	1058	*/
bogdanm	84:0b3ab51c8877	1059	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
bogdanm	84:0b3ab51c8877	1060
bogdanm	84:0b3ab51c8877	1061	/**
bogdanm	84:0b3ab51c8877	1062	* @brief Enables the automatic hardware adjustment of TRIM bits.
bogdanm	84:0b3ab51c8877	1063	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	84:0b3ab51c8877	1064	* @param None
bogdanm	84:0b3ab51c8877	1065	* @retval None
bogdanm	84:0b3ab51c8877	1066	*/
bogdanm	84:0b3ab51c8877	1067	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
bogdanm	84:0b3ab51c8877	1068
bogdanm	84:0b3ab51c8877	1069	/**
bogdanm	84:0b3ab51c8877	1070	* @brief Enables or disables the automatic hardware adjustment of TRIM bits.
bogdanm	84:0b3ab51c8877	1071	* @param None
bogdanm	84:0b3ab51c8877	1072	* @retval None
bogdanm	84:0b3ab51c8877	1073	*/
bogdanm	84:0b3ab51c8877	1074	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
bogdanm	84:0b3ab51c8877	1075
bogdanm	84:0b3ab51c8877	1076	/**
bogdanm	84:0b3ab51c8877	1077	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
bogdanm	84:0b3ab51c8877	1078	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
bogdanm	84:0b3ab51c8877	1079	* of the synchronization source after prescaling. It is then decreased by one in order to
bogdanm	84:0b3ab51c8877	1080	* reach the expected synchronization on the zero value. The formula is the following:
bogdanm	84:0b3ab51c8877	1081	* RELOAD = (fTARGET / fSYNC) -1
bogdanm	84:0b3ab51c8877	1082	* @param _FTARGET_ Target frequency (value in Hz)
bogdanm	84:0b3ab51c8877	1083	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
bogdanm	84:0b3ab51c8877	1084	* @retval None
bogdanm	84:0b3ab51c8877	1085	*/
bogdanm	84:0b3ab51c8877	1086	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
bogdanm	84:0b3ab51c8877	1087
bogdanm	84:0b3ab51c8877	1088	#endif /* !(STM32L051xx) && !(STM32L061xx) */
bogdanm	84:0b3ab51c8877	1089
bogdanm	84:0b3ab51c8877	1090	/**
bogdanm	84:0b3ab51c8877	1091	* @}
bogdanm	84:0b3ab51c8877	1092	*/
bogdanm	84:0b3ab51c8877	1093
bogdanm	84:0b3ab51c8877	1094
bogdanm	84:0b3ab51c8877	1095	/* Exported functions --------------------------------------------------------*/
bogdanm	84:0b3ab51c8877	1096	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	84:0b3ab51c8877	1097	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	84:0b3ab51c8877	1098	void HAL_RCCEx_EnableLSECSS(void);
bogdanm	84:0b3ab51c8877	1099	void HAL_RCCEx_DisableLSECSS(void);
bogdanm	84:0b3ab51c8877	1100	#if !defined(STM32L051xx) && !defined(STM32L061xx)
bogdanm	84:0b3ab51c8877	1101	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
bogdanm	84:0b3ab51c8877	1102	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
bogdanm	84:0b3ab51c8877	1103	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
bogdanm	84:0b3ab51c8877	1104	RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
bogdanm	84:0b3ab51c8877	1105	#endif /* !(STM32L051xx) && !(STM32L061xx) */
bogdanm	84:0b3ab51c8877	1106
bogdanm	84:0b3ab51c8877	1107	/**
bogdanm	84:0b3ab51c8877	1108	* @}
bogdanm	84:0b3ab51c8877	1109	*/
bogdanm	84:0b3ab51c8877	1110
bogdanm	84:0b3ab51c8877	1111	/**
bogdanm	84:0b3ab51c8877	1112	* @}
bogdanm	84:0b3ab51c8877	1113	*/
bogdanm	84:0b3ab51c8877	1114
bogdanm	84:0b3ab51c8877	1115	#ifdef __cplusplus
bogdanm	84:0b3ab51c8877	1116	}
bogdanm	84:0b3ab51c8877	1117	#endif
bogdanm	84:0b3ab51c8877	1118
bogdanm	84:0b3ab51c8877	1119	#endif /* __STM32L0xx_HAL_RCC_EX_H */
bogdanm	84:0b3ab51c8877	1120
bogdanm	84:0b3ab51c8877	1121	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/