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TARGET_NUCLEO_F411RE/stm32f4xx_ll_fsmc.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: 86:04dd9b1680ae
Child:: 99:dbbf35b96557

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	86:04dd9b1680ae	1	/**
bogdanm	86:04dd9b1680ae	2	******************************************************************************
bogdanm	86:04dd9b1680ae	3	* @file stm32f4xx_ll_fsmc.h
bogdanm	86:04dd9b1680ae	4	* @author MCD Application Team
bogdanm	86:04dd9b1680ae	5	* @version V1.1.0
bogdanm	86:04dd9b1680ae	6	* @date 19-June-2014
bogdanm	86:04dd9b1680ae	7	* @brief Header file of FSMC HAL module.
bogdanm	86:04dd9b1680ae	8	******************************************************************************
bogdanm	86:04dd9b1680ae	9	* @attention
bogdanm	86:04dd9b1680ae	10	*
bogdanm	86:04dd9b1680ae	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	86:04dd9b1680ae	12	*
bogdanm	86:04dd9b1680ae	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	86:04dd9b1680ae	14	* are permitted provided that the following conditions are met:
bogdanm	86:04dd9b1680ae	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	86:04dd9b1680ae	16	* this list of conditions and the following disclaimer.
bogdanm	86:04dd9b1680ae	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	86:04dd9b1680ae	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	86:04dd9b1680ae	19	* and/or other materials provided with the distribution.
bogdanm	86:04dd9b1680ae	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	86:04dd9b1680ae	21	* may be used to endorse or promote products derived from this software
bogdanm	86:04dd9b1680ae	22	* without specific prior written permission.
bogdanm	86:04dd9b1680ae	23	*
bogdanm	86:04dd9b1680ae	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	86:04dd9b1680ae	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	86:04dd9b1680ae	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	86:04dd9b1680ae	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	86:04dd9b1680ae	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	86:04dd9b1680ae	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	86:04dd9b1680ae	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	86:04dd9b1680ae	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	86:04dd9b1680ae	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	86:04dd9b1680ae	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	86:04dd9b1680ae	34	*
bogdanm	86:04dd9b1680ae	35	******************************************************************************
bogdanm	86:04dd9b1680ae	36	*/
bogdanm	86:04dd9b1680ae	37
bogdanm	86:04dd9b1680ae	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	86:04dd9b1680ae	39	#ifndef __STM32F4xx_LL_FSMC_H
bogdanm	86:04dd9b1680ae	40	#define __STM32F4xx_LL_FSMC_H
bogdanm	86:04dd9b1680ae	41
bogdanm	86:04dd9b1680ae	42	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	43	extern "C" {
bogdanm	86:04dd9b1680ae	44	#endif
bogdanm	86:04dd9b1680ae	45
bogdanm	86:04dd9b1680ae	46	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
bogdanm	86:04dd9b1680ae	47
bogdanm	86:04dd9b1680ae	48	/* Includes ------------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	49	#include "stm32f4xx_hal_def.h"
bogdanm	86:04dd9b1680ae	50
bogdanm	86:04dd9b1680ae	51	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	86:04dd9b1680ae	52	* @{
bogdanm	86:04dd9b1680ae	53	*/
bogdanm	86:04dd9b1680ae	54
bogdanm	86:04dd9b1680ae	55	/** @addtogroup FSMC
bogdanm	86:04dd9b1680ae	56	* @{
bogdanm	86:04dd9b1680ae	57	*/
bogdanm	86:04dd9b1680ae	58
bogdanm	86:04dd9b1680ae	59	/* Exported typedef ----------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	60	#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
bogdanm	86:04dd9b1680ae	61	#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
bogdanm	86:04dd9b1680ae	62	#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
bogdanm	86:04dd9b1680ae	63	#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
bogdanm	86:04dd9b1680ae	64
bogdanm	86:04dd9b1680ae	65	#define FSMC_NORSRAM_DEVICE FSMC_Bank1
bogdanm	86:04dd9b1680ae	66	#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
bogdanm	86:04dd9b1680ae	67	#define FSMC_NAND_DEVICE FSMC_Bank2_3
bogdanm	86:04dd9b1680ae	68	#define FSMC_PCCARD_DEVICE FSMC_Bank4
bogdanm	86:04dd9b1680ae	69
bogdanm	86:04dd9b1680ae	70	/**
bogdanm	86:04dd9b1680ae	71	* @brief FSMC_NORSRAM Configuration Structure definition
bogdanm	86:04dd9b1680ae	72	*/
bogdanm	86:04dd9b1680ae	73	typedef struct
bogdanm	86:04dd9b1680ae	74	{
bogdanm	86:04dd9b1680ae	75	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm	86:04dd9b1680ae	76	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
bogdanm	86:04dd9b1680ae	77
bogdanm	86:04dd9b1680ae	78	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm	86:04dd9b1680ae	79	multiplexed on the data bus or not.
bogdanm	86:04dd9b1680ae	80	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
bogdanm	86:04dd9b1680ae	81
bogdanm	86:04dd9b1680ae	82	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm	86:04dd9b1680ae	83	the corresponding memory device.
bogdanm	86:04dd9b1680ae	84	This parameter can be a value of @ref FSMC_Memory_Type */
bogdanm	86:04dd9b1680ae	85
bogdanm	86:04dd9b1680ae	86	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm	86:04dd9b1680ae	87	This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
bogdanm	86:04dd9b1680ae	88
bogdanm	86:04dd9b1680ae	89	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm	86:04dd9b1680ae	90	valid only with synchronous burst Flash memories.
bogdanm	86:04dd9b1680ae	91	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
bogdanm	86:04dd9b1680ae	92
bogdanm	86:04dd9b1680ae	93	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm	86:04dd9b1680ae	94	the Flash memory in burst mode.
bogdanm	86:04dd9b1680ae	95	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
bogdanm	86:04dd9b1680ae	96
bogdanm	86:04dd9b1680ae	97	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm	86:04dd9b1680ae	98	memory, valid only when accessing Flash memories in burst mode.
bogdanm	86:04dd9b1680ae	99	This parameter can be a value of @ref FSMC_Wrap_Mode */
bogdanm	86:04dd9b1680ae	100
bogdanm	86:04dd9b1680ae	101	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm	86:04dd9b1680ae	102	clock cycle before the wait state or during the wait state,
bogdanm	86:04dd9b1680ae	103	valid only when accessing memories in burst mode.
bogdanm	86:04dd9b1680ae	104	This parameter can be a value of @ref FSMC_Wait_Timing */
bogdanm	86:04dd9b1680ae	105
bogdanm	86:04dd9b1680ae	106	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
bogdanm	86:04dd9b1680ae	107	This parameter can be a value of @ref FSMC_Write_Operation */
bogdanm	86:04dd9b1680ae	108
bogdanm	86:04dd9b1680ae	109	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
bogdanm	86:04dd9b1680ae	110	signal, valid for Flash memory access in burst mode.
bogdanm	86:04dd9b1680ae	111	This parameter can be a value of @ref FSMC_Wait_Signal */
bogdanm	86:04dd9b1680ae	112
bogdanm	86:04dd9b1680ae	113	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm	86:04dd9b1680ae	114	This parameter can be a value of @ref FSMC_Extended_Mode */
bogdanm	86:04dd9b1680ae	115
bogdanm	86:04dd9b1680ae	116	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm	86:04dd9b1680ae	117	valid only with asynchronous Flash memories.
bogdanm	86:04dd9b1680ae	118	This parameter can be a value of @ref FSMC_AsynchronousWait */
bogdanm	86:04dd9b1680ae	119
bogdanm	86:04dd9b1680ae	120	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm	86:04dd9b1680ae	121	This parameter can be a value of @ref FSMC_Write_Burst */
bogdanm	86:04dd9b1680ae	122
bogdanm	86:04dd9b1680ae	123	}FSMC_NORSRAM_InitTypeDef;
bogdanm	86:04dd9b1680ae	124
bogdanm	86:04dd9b1680ae	125	/**
bogdanm	86:04dd9b1680ae	126	* @brief FSMC_NORSRAM Timing parameters structure definition
bogdanm	86:04dd9b1680ae	127	*/
bogdanm	86:04dd9b1680ae	128	typedef struct
bogdanm	86:04dd9b1680ae	129	{
bogdanm	86:04dd9b1680ae	130	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	86:04dd9b1680ae	131	the duration of the address setup time.
bogdanm	86:04dd9b1680ae	132	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm	86:04dd9b1680ae	133	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	86:04dd9b1680ae	134
bogdanm	86:04dd9b1680ae	135	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	86:04dd9b1680ae	136	the duration of the address hold time.
bogdanm	86:04dd9b1680ae	137	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm	86:04dd9b1680ae	138	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	86:04dd9b1680ae	139
bogdanm	86:04dd9b1680ae	140	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	86:04dd9b1680ae	141	the duration of the data setup time.
bogdanm	86:04dd9b1680ae	142	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
bogdanm	86:04dd9b1680ae	143	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm	86:04dd9b1680ae	144	NOR Flash memories. */
bogdanm	86:04dd9b1680ae	145
bogdanm	86:04dd9b1680ae	146	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm	86:04dd9b1680ae	147	the duration of the bus turnaround.
bogdanm	86:04dd9b1680ae	148	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm	86:04dd9b1680ae	149	@note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm	86:04dd9b1680ae	150
bogdanm	86:04dd9b1680ae	151	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm	86:04dd9b1680ae	152	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
bogdanm	86:04dd9b1680ae	153	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm	86:04dd9b1680ae	154	accesses. */
bogdanm	86:04dd9b1680ae	155
bogdanm	86:04dd9b1680ae	156	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm	86:04dd9b1680ae	157	to the memory before getting the first data.
bogdanm	86:04dd9b1680ae	158	The parameter value depends on the memory type as shown below:
bogdanm	86:04dd9b1680ae	159	- It must be set to 0 in case of a CRAM
bogdanm	86:04dd9b1680ae	160	- It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm	86:04dd9b1680ae	161	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm	86:04dd9b1680ae	162	with synchronous burst mode enable */
bogdanm	86:04dd9b1680ae	163
bogdanm	86:04dd9b1680ae	164	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm	86:04dd9b1680ae	165	This parameter can be a value of @ref FSMC_Access_Mode */
bogdanm	86:04dd9b1680ae	166
bogdanm	86:04dd9b1680ae	167	}FSMC_NORSRAM_TimingTypeDef;
bogdanm	86:04dd9b1680ae	168
bogdanm	86:04dd9b1680ae	169	/**
bogdanm	86:04dd9b1680ae	170	* @brief FSMC_NAND Configuration Structure definition
bogdanm	86:04dd9b1680ae	171	*/
bogdanm	86:04dd9b1680ae	172	typedef struct
bogdanm	86:04dd9b1680ae	173	{
bogdanm	86:04dd9b1680ae	174	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm	86:04dd9b1680ae	175	This parameter can be a value of @ref FSMC_NAND_Bank */
bogdanm	86:04dd9b1680ae	176
bogdanm	86:04dd9b1680ae	177	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
bogdanm	86:04dd9b1680ae	178	This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm	86:04dd9b1680ae	179
bogdanm	86:04dd9b1680ae	180	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm	86:04dd9b1680ae	181	This parameter can be any value of @ref FSMC_NAND_Data_Width */
bogdanm	86:04dd9b1680ae	182
bogdanm	86:04dd9b1680ae	183	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
bogdanm	86:04dd9b1680ae	184	This parameter can be any value of @ref FSMC_ECC */
bogdanm	86:04dd9b1680ae	185
bogdanm	86:04dd9b1680ae	186	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm	86:04dd9b1680ae	187	This parameter can be any value of @ref FSMC_ECC_Page_Size */
bogdanm	86:04dd9b1680ae	188
bogdanm	86:04dd9b1680ae	189	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	86:04dd9b1680ae	190	delay between CLE low and RE low.
bogdanm	86:04dd9b1680ae	191	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	86:04dd9b1680ae	192
bogdanm	86:04dd9b1680ae	193	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	86:04dd9b1680ae	194	delay between ALE low and RE low.
bogdanm	86:04dd9b1680ae	195	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	86:04dd9b1680ae	196
bogdanm	86:04dd9b1680ae	197	}FSMC_NAND_InitTypeDef;
bogdanm	86:04dd9b1680ae	198
bogdanm	86:04dd9b1680ae	199	/**
bogdanm	86:04dd9b1680ae	200	* @brief FSMC_NAND_PCCARD Timing parameters structure definition
bogdanm	86:04dd9b1680ae	201	*/
bogdanm	86:04dd9b1680ae	202	typedef struct
bogdanm	86:04dd9b1680ae	203	{
bogdanm	86:04dd9b1680ae	204	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm	86:04dd9b1680ae	205	the command assertion for NAND-Flash read or write access
bogdanm	86:04dd9b1680ae	206	to common/Attribute or I/O memory space (depending on
bogdanm	86:04dd9b1680ae	207	the memory space timing to be configured).
bogdanm	86:04dd9b1680ae	208	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	86:04dd9b1680ae	209
bogdanm	86:04dd9b1680ae	210	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm	86:04dd9b1680ae	211	command for NAND-Flash read or write access to
bogdanm	86:04dd9b1680ae	212	common/Attribute or I/O memory space (depending on the
bogdanm	86:04dd9b1680ae	213	memory space timing to be configured).
bogdanm	86:04dd9b1680ae	214	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	86:04dd9b1680ae	215
bogdanm	86:04dd9b1680ae	216	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm	86:04dd9b1680ae	217	(and data for write access) after the command de-assertion
bogdanm	86:04dd9b1680ae	218	for NAND-Flash read or write access to common/Attribute
bogdanm	86:04dd9b1680ae	219	or I/O memory space (depending on the memory space timing
bogdanm	86:04dd9b1680ae	220	to be configured).
bogdanm	86:04dd9b1680ae	221	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	86:04dd9b1680ae	222
bogdanm	86:04dd9b1680ae	223	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm	86:04dd9b1680ae	224	data bus is kept in HiZ after the start of a NAND-Flash
bogdanm	86:04dd9b1680ae	225	write access to common/Attribute or I/O memory space (depending
bogdanm	86:04dd9b1680ae	226	on the memory space timing to be configured).
bogdanm	86:04dd9b1680ae	227	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	86:04dd9b1680ae	228
bogdanm	86:04dd9b1680ae	229	}FSMC_NAND_PCC_TimingTypeDef;
bogdanm	86:04dd9b1680ae	230
bogdanm	86:04dd9b1680ae	231	/**
bogdanm	86:04dd9b1680ae	232	* @brief FSMC_NAND Configuration Structure definition
bogdanm	86:04dd9b1680ae	233	*/
bogdanm	86:04dd9b1680ae	234	typedef struct
bogdanm	86:04dd9b1680ae	235	{
bogdanm	86:04dd9b1680ae	236	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
bogdanm	86:04dd9b1680ae	237	This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm	86:04dd9b1680ae	238
bogdanm	86:04dd9b1680ae	239	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	86:04dd9b1680ae	240	delay between CLE low and RE low.
bogdanm	86:04dd9b1680ae	241	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	86:04dd9b1680ae	242
bogdanm	86:04dd9b1680ae	243	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	86:04dd9b1680ae	244	delay between ALE low and RE low.
bogdanm	86:04dd9b1680ae	245	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	86:04dd9b1680ae	246
bogdanm	86:04dd9b1680ae	247	}FSMC_PCCARD_InitTypeDef;
bogdanm	86:04dd9b1680ae	248
bogdanm	86:04dd9b1680ae	249	/* Exported constants --------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	250
bogdanm	86:04dd9b1680ae	251	/** @defgroup FSMC_NOR_SRAM_Controller
bogdanm	86:04dd9b1680ae	252	* @{
bogdanm	86:04dd9b1680ae	253	*/
bogdanm	86:04dd9b1680ae	254
bogdanm	86:04dd9b1680ae	255	/** @defgroup FSMC_NORSRAM_Bank
bogdanm	86:04dd9b1680ae	256	* @{
bogdanm	86:04dd9b1680ae	257	*/
bogdanm	86:04dd9b1680ae	258	#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	259	#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	260	#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	261	#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
bogdanm	86:04dd9b1680ae	262
bogdanm	86:04dd9b1680ae	263	#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_NORSRAM_BANK1) \|\| \
bogdanm	86:04dd9b1680ae	264	((BANK) == FSMC_NORSRAM_BANK2) \|\| \
bogdanm	86:04dd9b1680ae	265	((BANK) == FSMC_NORSRAM_BANK3) \|\| \
bogdanm	86:04dd9b1680ae	266	((BANK) == FSMC_NORSRAM_BANK4))
bogdanm	86:04dd9b1680ae	267	/**
bogdanm	86:04dd9b1680ae	268	* @}
bogdanm	86:04dd9b1680ae	269	*/
bogdanm	86:04dd9b1680ae	270
bogdanm	86:04dd9b1680ae	271	/** @defgroup FSMC_Data_Address_Bus_Multiplexing
bogdanm	86:04dd9b1680ae	272	* @{
bogdanm	86:04dd9b1680ae	273	*/
bogdanm	86:04dd9b1680ae	274
bogdanm	86:04dd9b1680ae	275	#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	276	#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	277
bogdanm	86:04dd9b1680ae	278	#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
bogdanm	86:04dd9b1680ae	279	((MUX) == FSMC_DATA_ADDRESS_MUX_ENABLE))
bogdanm	86:04dd9b1680ae	280	/**
bogdanm	86:04dd9b1680ae	281	* @}
bogdanm	86:04dd9b1680ae	282	*/
bogdanm	86:04dd9b1680ae	283
bogdanm	86:04dd9b1680ae	284	/** @defgroup FSMC_Memory_Type
bogdanm	86:04dd9b1680ae	285	* @{
bogdanm	86:04dd9b1680ae	286	*/
bogdanm	86:04dd9b1680ae	287
bogdanm	86:04dd9b1680ae	288	#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	289	#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	290	#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	291
bogdanm	86:04dd9b1680ae	292
bogdanm	86:04dd9b1680ae	293	#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MEMORY_TYPE_SRAM) \|\| \
bogdanm	86:04dd9b1680ae	294	((MEMORY) == FSMC_MEMORY_TYPE_PSRAM)\|\| \
bogdanm	86:04dd9b1680ae	295	((MEMORY) == FSMC_MEMORY_TYPE_NOR))
bogdanm	86:04dd9b1680ae	296	/**
bogdanm	86:04dd9b1680ae	297	* @}
bogdanm	86:04dd9b1680ae	298	*/
bogdanm	86:04dd9b1680ae	299
bogdanm	86:04dd9b1680ae	300	/** @defgroup FSMC_NORSRAM_Data_Width
bogdanm	86:04dd9b1680ae	301	* @{
bogdanm	86:04dd9b1680ae	302	*/
bogdanm	86:04dd9b1680ae	303
bogdanm	86:04dd9b1680ae	304	#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	305	#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	86:04dd9b1680ae	306	#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	307
bogdanm	86:04dd9b1680ae	308	#define IS_FSMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
bogdanm	86:04dd9b1680ae	309	((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
bogdanm	86:04dd9b1680ae	310	((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
bogdanm	86:04dd9b1680ae	311	/**
bogdanm	86:04dd9b1680ae	312	* @}
bogdanm	86:04dd9b1680ae	313	*/
bogdanm	86:04dd9b1680ae	314
bogdanm	86:04dd9b1680ae	315	/** @defgroup FSMC_NORSRAM_Flash_Access
bogdanm	86:04dd9b1680ae	316	* @{
bogdanm	86:04dd9b1680ae	317	*/
bogdanm	86:04dd9b1680ae	318	#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
bogdanm	86:04dd9b1680ae	319	#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	320	/**
bogdanm	86:04dd9b1680ae	321	* @}
bogdanm	86:04dd9b1680ae	322	*/
bogdanm	86:04dd9b1680ae	323
bogdanm	86:04dd9b1680ae	324	/** @defgroup FSMC_Burst_Access_Mode
bogdanm	86:04dd9b1680ae	325	* @{
bogdanm	86:04dd9b1680ae	326	*/
bogdanm	86:04dd9b1680ae	327
bogdanm	86:04dd9b1680ae	328	#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	329	#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
bogdanm	86:04dd9b1680ae	330
bogdanm	86:04dd9b1680ae	331	#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BURST_ACCESS_MODE_DISABLE) \|\| \
bogdanm	86:04dd9b1680ae	332	((STATE) == FSMC_BURST_ACCESS_MODE_ENABLE))
bogdanm	86:04dd9b1680ae	333	/**
bogdanm	86:04dd9b1680ae	334	* @}
bogdanm	86:04dd9b1680ae	335	*/
bogdanm	86:04dd9b1680ae	336
bogdanm	86:04dd9b1680ae	337
bogdanm	86:04dd9b1680ae	338	/** @defgroup FSMC_Wait_Signal_Polarity
bogdanm	86:04dd9b1680ae	339	* @{
bogdanm	86:04dd9b1680ae	340	*/
bogdanm	86:04dd9b1680ae	341	#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	342	#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
bogdanm	86:04dd9b1680ae	343
bogdanm	86:04dd9b1680ae	344	#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
bogdanm	86:04dd9b1680ae	345	((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
bogdanm	86:04dd9b1680ae	346	/**
bogdanm	86:04dd9b1680ae	347	* @}
bogdanm	86:04dd9b1680ae	348	*/
bogdanm	86:04dd9b1680ae	349
bogdanm	86:04dd9b1680ae	350	/** @defgroup FSMC_Wrap_Mode
bogdanm	86:04dd9b1680ae	351	* @{
bogdanm	86:04dd9b1680ae	352	*/
bogdanm	86:04dd9b1680ae	353	#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	354	#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
bogdanm	86:04dd9b1680ae	355
bogdanm	86:04dd9b1680ae	356	#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WRAP_MODE_DISABLE) \|\| \
bogdanm	86:04dd9b1680ae	357	((MODE) == FSMC_WRAP_MODE_ENABLE))
bogdanm	86:04dd9b1680ae	358	/**
bogdanm	86:04dd9b1680ae	359	* @}
bogdanm	86:04dd9b1680ae	360	*/
bogdanm	86:04dd9b1680ae	361
bogdanm	86:04dd9b1680ae	362	/** @defgroup FSMC_Wait_Timing
bogdanm	86:04dd9b1680ae	363	* @{
bogdanm	86:04dd9b1680ae	364	*/
bogdanm	86:04dd9b1680ae	365	#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	366	#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
bogdanm	86:04dd9b1680ae	367
bogdanm	86:04dd9b1680ae	368	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WAIT_TIMING_BEFORE_WS) \|\| \
bogdanm	86:04dd9b1680ae	369	((ACTIVE) == FSMC_WAIT_TIMING_DURING_WS))
bogdanm	86:04dd9b1680ae	370	/**
bogdanm	86:04dd9b1680ae	371	* @}
bogdanm	86:04dd9b1680ae	372	*/
bogdanm	86:04dd9b1680ae	373
bogdanm	86:04dd9b1680ae	374	/** @defgroup FSMC_Write_Operation
bogdanm	86:04dd9b1680ae	375	* @{
bogdanm	86:04dd9b1680ae	376	*/
bogdanm	86:04dd9b1680ae	377	#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	378	#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
bogdanm	86:04dd9b1680ae	379
bogdanm	86:04dd9b1680ae	380	#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) \|\| \
bogdanm	86:04dd9b1680ae	381	((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
bogdanm	86:04dd9b1680ae	382	/**
bogdanm	86:04dd9b1680ae	383	* @}
bogdanm	86:04dd9b1680ae	384	*/
bogdanm	86:04dd9b1680ae	385
bogdanm	86:04dd9b1680ae	386	/** @defgroup FSMC_Wait_Signal
bogdanm	86:04dd9b1680ae	387	* @{
bogdanm	86:04dd9b1680ae	388	*/
bogdanm	86:04dd9b1680ae	389	#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	390	#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
bogdanm	86:04dd9b1680ae	391
bogdanm	86:04dd9b1680ae	392	#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WAIT_SIGNAL_DISABLE) \|\| \
bogdanm	86:04dd9b1680ae	393	((SIGNAL) == FSMC_WAIT_SIGNAL_ENABLE))
bogdanm	86:04dd9b1680ae	394
bogdanm	86:04dd9b1680ae	395	/**
bogdanm	86:04dd9b1680ae	396	* @}
bogdanm	86:04dd9b1680ae	397	*/
bogdanm	86:04dd9b1680ae	398
bogdanm	86:04dd9b1680ae	399	/** @defgroup FSMC_Extended_Mode
bogdanm	86:04dd9b1680ae	400	* @{
bogdanm	86:04dd9b1680ae	401	*/
bogdanm	86:04dd9b1680ae	402	#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	403	#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
bogdanm	86:04dd9b1680ae	404
bogdanm	86:04dd9b1680ae	405	#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_EXTENDED_MODE_DISABLE) \|\| \
bogdanm	86:04dd9b1680ae	406	((MODE) == FSMC_EXTENDED_MODE_ENABLE))
bogdanm	86:04dd9b1680ae	407	/**
bogdanm	86:04dd9b1680ae	408	* @}
bogdanm	86:04dd9b1680ae	409	*/
bogdanm	86:04dd9b1680ae	410
bogdanm	86:04dd9b1680ae	411	/** @defgroup FSMC_AsynchronousWait
bogdanm	86:04dd9b1680ae	412	* @{
bogdanm	86:04dd9b1680ae	413	*/
bogdanm	86:04dd9b1680ae	414	#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	415	#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
bogdanm	86:04dd9b1680ae	416
bogdanm	86:04dd9b1680ae	417	#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
bogdanm	86:04dd9b1680ae	418	((STATE) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
bogdanm	86:04dd9b1680ae	419
bogdanm	86:04dd9b1680ae	420	/**
bogdanm	86:04dd9b1680ae	421	* @}
bogdanm	86:04dd9b1680ae	422	*/
bogdanm	86:04dd9b1680ae	423
bogdanm	86:04dd9b1680ae	424	/** @defgroup FSMC_Write_Burst
bogdanm	86:04dd9b1680ae	425	* @{
bogdanm	86:04dd9b1680ae	426	*/
bogdanm	86:04dd9b1680ae	427
bogdanm	86:04dd9b1680ae	428	#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	429	#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
bogdanm	86:04dd9b1680ae	430
bogdanm	86:04dd9b1680ae	431	#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WRITE_BURST_DISABLE) \|\| \
bogdanm	86:04dd9b1680ae	432	((BURST) == FSMC_WRITE_BURST_ENABLE))
bogdanm	86:04dd9b1680ae	433
bogdanm	86:04dd9b1680ae	434	/**
bogdanm	86:04dd9b1680ae	435	* @}
bogdanm	86:04dd9b1680ae	436	*/
bogdanm	86:04dd9b1680ae	437
bogdanm	86:04dd9b1680ae	438	/** @defgroup FSMC_Continous_Clock
bogdanm	86:04dd9b1680ae	439	* @{
bogdanm	86:04dd9b1680ae	440	*/
bogdanm	86:04dd9b1680ae	441
bogdanm	86:04dd9b1680ae	442	#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	443	#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
bogdanm	86:04dd9b1680ae	444
bogdanm	86:04dd9b1680ae	445	#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
bogdanm	86:04dd9b1680ae	446	((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
bogdanm	86:04dd9b1680ae	447
bogdanm	86:04dd9b1680ae	448	/**
bogdanm	86:04dd9b1680ae	449	* @}
bogdanm	86:04dd9b1680ae	450	*/
bogdanm	86:04dd9b1680ae	451
bogdanm	86:04dd9b1680ae	452	/** @defgroup FSMC_Address_Setup_Time
bogdanm	86:04dd9b1680ae	453	* @{
bogdanm	86:04dd9b1680ae	454	*/
bogdanm	86:04dd9b1680ae	455	#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
bogdanm	86:04dd9b1680ae	456	/**
bogdanm	86:04dd9b1680ae	457	* @}
bogdanm	86:04dd9b1680ae	458	*/
bogdanm	86:04dd9b1680ae	459
bogdanm	86:04dd9b1680ae	460	/** @defgroup FSMC_Address_Hold_Time
bogdanm	86:04dd9b1680ae	461	* @{
bogdanm	86:04dd9b1680ae	462	*/
bogdanm	86:04dd9b1680ae	463	#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
bogdanm	86:04dd9b1680ae	464	/**
bogdanm	86:04dd9b1680ae	465	* @}
bogdanm	86:04dd9b1680ae	466	*/
bogdanm	86:04dd9b1680ae	467
bogdanm	86:04dd9b1680ae	468	/** @defgroup FSMC_Data_Setup_Time
bogdanm	86:04dd9b1680ae	469	* @{
bogdanm	86:04dd9b1680ae	470	*/
bogdanm	86:04dd9b1680ae	471	#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
bogdanm	86:04dd9b1680ae	472	/**
bogdanm	86:04dd9b1680ae	473	* @}
bogdanm	86:04dd9b1680ae	474	*/
bogdanm	86:04dd9b1680ae	475
bogdanm	86:04dd9b1680ae	476	/** @defgroup FSMC_Bus_Turn_around_Duration
bogdanm	86:04dd9b1680ae	477	* @{
bogdanm	86:04dd9b1680ae	478	*/
bogdanm	86:04dd9b1680ae	479	#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
bogdanm	86:04dd9b1680ae	480	/**
bogdanm	86:04dd9b1680ae	481	* @}
bogdanm	86:04dd9b1680ae	482	*/
bogdanm	86:04dd9b1680ae	483
bogdanm	86:04dd9b1680ae	484	/** @defgroup FSMC_CLK_Division
bogdanm	86:04dd9b1680ae	485	* @{
bogdanm	86:04dd9b1680ae	486	*/
bogdanm	86:04dd9b1680ae	487	#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
bogdanm	86:04dd9b1680ae	488	/**
bogdanm	86:04dd9b1680ae	489	* @}
bogdanm	86:04dd9b1680ae	490	*/
bogdanm	86:04dd9b1680ae	491
bogdanm	86:04dd9b1680ae	492	/** @defgroup FSMC_Data_Latency
bogdanm	86:04dd9b1680ae	493	* @{
bogdanm	86:04dd9b1680ae	494	*/
bogdanm	86:04dd9b1680ae	495	#define IS_FSMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
bogdanm	86:04dd9b1680ae	496	/**
bogdanm	86:04dd9b1680ae	497	* @}
bogdanm	86:04dd9b1680ae	498	*/
bogdanm	86:04dd9b1680ae	499
bogdanm	86:04dd9b1680ae	500	/** @defgroup FSMC_Access_Mode
bogdanm	86:04dd9b1680ae	501	* @{
bogdanm	86:04dd9b1680ae	502	*/
bogdanm	86:04dd9b1680ae	503	#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	504	#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
bogdanm	86:04dd9b1680ae	505	#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
bogdanm	86:04dd9b1680ae	506	#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
bogdanm	86:04dd9b1680ae	507
bogdanm	86:04dd9b1680ae	508	#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_ACCESS_MODE_A) \|\| \
bogdanm	86:04dd9b1680ae	509	((MODE) == FSMC_ACCESS_MODE_B) \|\| \
bogdanm	86:04dd9b1680ae	510	((MODE) == FSMC_ACCESS_MODE_C) \|\| \
bogdanm	86:04dd9b1680ae	511	((MODE) == FSMC_ACCESS_MODE_D))
bogdanm	86:04dd9b1680ae	512	/**
bogdanm	86:04dd9b1680ae	513	* @}
bogdanm	86:04dd9b1680ae	514	*/
bogdanm	86:04dd9b1680ae	515
bogdanm	86:04dd9b1680ae	516	/**
bogdanm	86:04dd9b1680ae	517	* @}
bogdanm	86:04dd9b1680ae	518	*/
bogdanm	86:04dd9b1680ae	519
bogdanm	86:04dd9b1680ae	520	/** @defgroup FSMC_NAND_Controller
bogdanm	86:04dd9b1680ae	521	* @{
bogdanm	86:04dd9b1680ae	522	*/
bogdanm	86:04dd9b1680ae	523
bogdanm	86:04dd9b1680ae	524	/** @defgroup FSMC_NAND_Bank
bogdanm	86:04dd9b1680ae	525	* @{
bogdanm	86:04dd9b1680ae	526	*/
bogdanm	86:04dd9b1680ae	527	#define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
bogdanm	86:04dd9b1680ae	528	#define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
bogdanm	86:04dd9b1680ae	529
bogdanm	86:04dd9b1680ae	530	#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) \|\| \
bogdanm	86:04dd9b1680ae	531	((BANK) == FSMC_NAND_BANK3))
bogdanm	86:04dd9b1680ae	532
bogdanm	86:04dd9b1680ae	533	/**
bogdanm	86:04dd9b1680ae	534	* @}
bogdanm	86:04dd9b1680ae	535	*/
bogdanm	86:04dd9b1680ae	536
bogdanm	86:04dd9b1680ae	537	/** @defgroup FSMC_Wait_feature
bogdanm	86:04dd9b1680ae	538	* @{
bogdanm	86:04dd9b1680ae	539	*/
bogdanm	86:04dd9b1680ae	540	#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	541	#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	542
bogdanm	86:04dd9b1680ae	543	#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
bogdanm	86:04dd9b1680ae	544	((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
bogdanm	86:04dd9b1680ae	545	/**
bogdanm	86:04dd9b1680ae	546	* @}
bogdanm	86:04dd9b1680ae	547	*/
bogdanm	86:04dd9b1680ae	548
bogdanm	86:04dd9b1680ae	549	/** @defgroup FSMC_PCR_Memory_Type
bogdanm	86:04dd9b1680ae	550	* @{
bogdanm	86:04dd9b1680ae	551	*/
bogdanm	86:04dd9b1680ae	552	#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	553	#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	554	/**
bogdanm	86:04dd9b1680ae	555	* @}
bogdanm	86:04dd9b1680ae	556	*/
bogdanm	86:04dd9b1680ae	557
bogdanm	86:04dd9b1680ae	558	/** @defgroup FSMC_NAND_Data_Width
bogdanm	86:04dd9b1680ae	559	* @{
bogdanm	86:04dd9b1680ae	560	*/
bogdanm	86:04dd9b1680ae	561	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	562	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	86:04dd9b1680ae	563
bogdanm	86:04dd9b1680ae	564	#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
bogdanm	86:04dd9b1680ae	565	((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
bogdanm	86:04dd9b1680ae	566	/**
bogdanm	86:04dd9b1680ae	567	* @}
bogdanm	86:04dd9b1680ae	568	*/
bogdanm	86:04dd9b1680ae	569
bogdanm	86:04dd9b1680ae	570	/** @defgroup FSMC_ECC
bogdanm	86:04dd9b1680ae	571	* @{
bogdanm	86:04dd9b1680ae	572	*/
bogdanm	86:04dd9b1680ae	573	#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	574	#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
bogdanm	86:04dd9b1680ae	575
bogdanm	86:04dd9b1680ae	576	#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) \|\| \
bogdanm	86:04dd9b1680ae	577	((STATE) == FSMC_NAND_ECC_ENABLE))
bogdanm	86:04dd9b1680ae	578	/**
bogdanm	86:04dd9b1680ae	579	* @}
bogdanm	86:04dd9b1680ae	580	*/
bogdanm	86:04dd9b1680ae	581
bogdanm	86:04dd9b1680ae	582	/** @defgroup FSMC_ECC_Page_Size
bogdanm	86:04dd9b1680ae	583	* @{
bogdanm	86:04dd9b1680ae	584	*/
bogdanm	86:04dd9b1680ae	585	#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	586	#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
bogdanm	86:04dd9b1680ae	587	#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
bogdanm	86:04dd9b1680ae	588	#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
bogdanm	86:04dd9b1680ae	589	#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
bogdanm	86:04dd9b1680ae	590	#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
bogdanm	86:04dd9b1680ae	591
bogdanm	86:04dd9b1680ae	592	#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
bogdanm	86:04dd9b1680ae	593	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
bogdanm	86:04dd9b1680ae	594	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
bogdanm	86:04dd9b1680ae	595	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
bogdanm	86:04dd9b1680ae	596	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
bogdanm	86:04dd9b1680ae	597	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
bogdanm	86:04dd9b1680ae	598	/**
bogdanm	86:04dd9b1680ae	599	* @}
bogdanm	86:04dd9b1680ae	600	*/
bogdanm	86:04dd9b1680ae	601
bogdanm	86:04dd9b1680ae	602	/** @defgroup FSMC_TCLR_Setup_Time
bogdanm	86:04dd9b1680ae	603	* @{
bogdanm	86:04dd9b1680ae	604	*/
bogdanm	86:04dd9b1680ae	605	#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
bogdanm	86:04dd9b1680ae	606	/**
bogdanm	86:04dd9b1680ae	607	* @}
bogdanm	86:04dd9b1680ae	608	*/
bogdanm	86:04dd9b1680ae	609
bogdanm	86:04dd9b1680ae	610	/** @defgroup FSMC_TAR_Setup_Time
bogdanm	86:04dd9b1680ae	611	* @{
bogdanm	86:04dd9b1680ae	612	*/
bogdanm	86:04dd9b1680ae	613	#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
bogdanm	86:04dd9b1680ae	614	/**
bogdanm	86:04dd9b1680ae	615	* @}
bogdanm	86:04dd9b1680ae	616	*/
bogdanm	86:04dd9b1680ae	617
bogdanm	86:04dd9b1680ae	618	/** @defgroup FSMC_Setup_Time
bogdanm	86:04dd9b1680ae	619	* @{
bogdanm	86:04dd9b1680ae	620	*/
bogdanm	86:04dd9b1680ae	621	#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
bogdanm	86:04dd9b1680ae	622	/**
bogdanm	86:04dd9b1680ae	623	* @}
bogdanm	86:04dd9b1680ae	624	*/
bogdanm	86:04dd9b1680ae	625
bogdanm	86:04dd9b1680ae	626	/** @defgroup FSMC_Wait_Setup_Time
bogdanm	86:04dd9b1680ae	627	* @{
bogdanm	86:04dd9b1680ae	628	*/
bogdanm	86:04dd9b1680ae	629	#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
bogdanm	86:04dd9b1680ae	630	/**
bogdanm	86:04dd9b1680ae	631	* @}
bogdanm	86:04dd9b1680ae	632	*/
bogdanm	86:04dd9b1680ae	633
bogdanm	86:04dd9b1680ae	634	/** @defgroup FSMC_Hold_Setup_Time
bogdanm	86:04dd9b1680ae	635	* @{
bogdanm	86:04dd9b1680ae	636	*/
bogdanm	86:04dd9b1680ae	637	#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
bogdanm	86:04dd9b1680ae	638	/**
bogdanm	86:04dd9b1680ae	639	* @}
bogdanm	86:04dd9b1680ae	640	*/
bogdanm	86:04dd9b1680ae	641
bogdanm	86:04dd9b1680ae	642	/** @defgroup FSMC_HiZ_Setup_Time
bogdanm	86:04dd9b1680ae	643	* @{
bogdanm	86:04dd9b1680ae	644	*/
bogdanm	86:04dd9b1680ae	645	#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
bogdanm	86:04dd9b1680ae	646	/**
bogdanm	86:04dd9b1680ae	647	* @}
bogdanm	86:04dd9b1680ae	648	*/
bogdanm	86:04dd9b1680ae	649
bogdanm	86:04dd9b1680ae	650	/**
bogdanm	86:04dd9b1680ae	651	* @}
bogdanm	86:04dd9b1680ae	652	*/
bogdanm	86:04dd9b1680ae	653
bogdanm	86:04dd9b1680ae	654
bogdanm	86:04dd9b1680ae	655	/** @defgroup FSMC_NORSRAM_Device_Instance
bogdanm	86:04dd9b1680ae	656	* @{
bogdanm	86:04dd9b1680ae	657	*/
bogdanm	86:04dd9b1680ae	658	#define IS_FSMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_DEVICE)
bogdanm	86:04dd9b1680ae	659
bogdanm	86:04dd9b1680ae	660	/**
bogdanm	86:04dd9b1680ae	661	* @}
bogdanm	86:04dd9b1680ae	662	*/
bogdanm	86:04dd9b1680ae	663
bogdanm	86:04dd9b1680ae	664	/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance
bogdanm	86:04dd9b1680ae	665	* @{
bogdanm	86:04dd9b1680ae	666	*/
bogdanm	86:04dd9b1680ae	667	#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_EXTENDED_DEVICE)
bogdanm	86:04dd9b1680ae	668
bogdanm	86:04dd9b1680ae	669	/**
bogdanm	86:04dd9b1680ae	670	* @}
bogdanm	86:04dd9b1680ae	671	*/
bogdanm	86:04dd9b1680ae	672
bogdanm	86:04dd9b1680ae	673	/** @defgroup FSMC_NAND_Device_Instance
bogdanm	86:04dd9b1680ae	674	* @{
bogdanm	86:04dd9b1680ae	675	*/
bogdanm	86:04dd9b1680ae	676	#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
bogdanm	86:04dd9b1680ae	677
bogdanm	86:04dd9b1680ae	678	/**
bogdanm	86:04dd9b1680ae	679	* @}
bogdanm	86:04dd9b1680ae	680	*/
bogdanm	86:04dd9b1680ae	681
bogdanm	86:04dd9b1680ae	682	/** @defgroup FSMC_PCCARD_Device_Instance
bogdanm	86:04dd9b1680ae	683	* @{
bogdanm	86:04dd9b1680ae	684	*/
bogdanm	86:04dd9b1680ae	685	#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
bogdanm	86:04dd9b1680ae	686
bogdanm	86:04dd9b1680ae	687	/**
bogdanm	86:04dd9b1680ae	688	* @}
bogdanm	86:04dd9b1680ae	689	*/
bogdanm	86:04dd9b1680ae	690
bogdanm	86:04dd9b1680ae	691	/** @defgroup FSMC_Interrupt_definition
bogdanm	86:04dd9b1680ae	692	* @brief FSMC Interrupt definition
bogdanm	86:04dd9b1680ae	693	* @{
bogdanm	86:04dd9b1680ae	694	*/
bogdanm	86:04dd9b1680ae	695	#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	696	#define FSMC_IT_LEVEL ((uint32_t)0x00000010)
bogdanm	86:04dd9b1680ae	697	#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	698	#define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
bogdanm	86:04dd9b1680ae	699
bogdanm	86:04dd9b1680ae	700	#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
bogdanm	86:04dd9b1680ae	701	#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RISING_EDGE) \|\| \
bogdanm	86:04dd9b1680ae	702	((IT) == FSMC_IT_LEVEL) \|\| \
bogdanm	86:04dd9b1680ae	703	((IT) == FSMC_IT_FALLING_EDGE) \|\| \
bogdanm	86:04dd9b1680ae	704	((IT) == FSMC_IT_REFRESH_ERROR))
bogdanm	86:04dd9b1680ae	705	/**
bogdanm	86:04dd9b1680ae	706	* @}
bogdanm	86:04dd9b1680ae	707	*/
bogdanm	86:04dd9b1680ae	708
bogdanm	86:04dd9b1680ae	709	/** @defgroup FSMC_Flag_definition
bogdanm	86:04dd9b1680ae	710	* @brief FSMC Flag definition
bogdanm	86:04dd9b1680ae	711	* @{
bogdanm	86:04dd9b1680ae	712	*/
bogdanm	86:04dd9b1680ae	713	#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	714	#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	715	#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	716	#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
bogdanm	86:04dd9b1680ae	717
bogdanm	86:04dd9b1680ae	718	#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RISING_EDGE) \|\| \
bogdanm	86:04dd9b1680ae	719	((FLAG) == FSMC_FLAG_LEVEL) \|\| \
bogdanm	86:04dd9b1680ae	720	((FLAG) == FSMC_FLAG_FALLING_EDGE) \|\| \
bogdanm	86:04dd9b1680ae	721	((FLAG) == FSMC_FLAG_FEMPT))
bogdanm	86:04dd9b1680ae	722
bogdanm	86:04dd9b1680ae	723	#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
bogdanm	86:04dd9b1680ae	724
bogdanm	86:04dd9b1680ae	725
bogdanm	86:04dd9b1680ae	726	/**
bogdanm	86:04dd9b1680ae	727	* @}
bogdanm	86:04dd9b1680ae	728	*/
bogdanm	86:04dd9b1680ae	729
bogdanm	86:04dd9b1680ae	730
bogdanm	86:04dd9b1680ae	731	/* Exported macro ------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	732
bogdanm	86:04dd9b1680ae	733
bogdanm	86:04dd9b1680ae	734	/** @defgroup FSMC_NOR_Macros
bogdanm	86:04dd9b1680ae	735	* @brief macros to handle NOR device enable/disable and read/write operations
bogdanm	86:04dd9b1680ae	736	* @{
bogdanm	86:04dd9b1680ae	737	*/
bogdanm	86:04dd9b1680ae	738
bogdanm	86:04dd9b1680ae	739	/**
bogdanm	86:04dd9b1680ae	740	* @brief Enable the NORSRAM device access.
bogdanm	86:04dd9b1680ae	741	* @param __INSTANCE__: FSMC_NORSRAM Instance
bogdanm	86:04dd9b1680ae	742	* @param __BANK__: FSMC_NORSRAM Bank
bogdanm	86:04dd9b1680ae	743	* @retval none
bogdanm	86:04dd9b1680ae	744	*/
bogdanm	86:04dd9b1680ae	745	#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FSMC_BCR1_MBKEN)
bogdanm	86:04dd9b1680ae	746
bogdanm	86:04dd9b1680ae	747	/**
bogdanm	86:04dd9b1680ae	748	* @brief Disable the NORSRAM device access.
bogdanm	86:04dd9b1680ae	749	* @param __INSTANCE__: FSMC_NORSRAM Instance
bogdanm	86:04dd9b1680ae	750	* @param __BANK__: FSMC_NORSRAM Bank
bogdanm	86:04dd9b1680ae	751	* @retval none
bogdanm	86:04dd9b1680ae	752	*/
bogdanm	86:04dd9b1680ae	753	#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
bogdanm	86:04dd9b1680ae	754
bogdanm	86:04dd9b1680ae	755	/**
bogdanm	86:04dd9b1680ae	756	* @}
bogdanm	86:04dd9b1680ae	757	*/
bogdanm	86:04dd9b1680ae	758
bogdanm	86:04dd9b1680ae	759
bogdanm	86:04dd9b1680ae	760	/** @defgroup FSMC_NAND_Macros
bogdanm	86:04dd9b1680ae	761	* @brief macros to handle NAND device enable/disable
bogdanm	86:04dd9b1680ae	762	* @{
bogdanm	86:04dd9b1680ae	763	*/
bogdanm	86:04dd9b1680ae	764
bogdanm	86:04dd9b1680ae	765	/**
bogdanm	86:04dd9b1680ae	766	* @brief Enable the NAND device access.
bogdanm	86:04dd9b1680ae	767	* @param __INSTANCE__: FSMC_NAND Instance
bogdanm	86:04dd9b1680ae	768	* @param __BANK__: FSMC_NAND Bank
bogdanm	86:04dd9b1680ae	769	* @retval none
bogdanm	86:04dd9b1680ae	770	*/
bogdanm	86:04dd9b1680ae	771	#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FSMC_PCR2_PBKEN): \
bogdanm	86:04dd9b1680ae	772	((__INSTANCE__)->PCR3 \|= FSMC_PCR3_PBKEN))
bogdanm	86:04dd9b1680ae	773
bogdanm	86:04dd9b1680ae	774
bogdanm	86:04dd9b1680ae	775	/**
bogdanm	86:04dd9b1680ae	776	* @brief Disable the NAND device access.
bogdanm	86:04dd9b1680ae	777	* @param __INSTANCE__: FSMC_NAND Instance
bogdanm	86:04dd9b1680ae	778	* @param __BANK__: FSMC_NAND Bank
bogdanm	86:04dd9b1680ae	779	* @retval none
bogdanm	86:04dd9b1680ae	780	*/
bogdanm	86:04dd9b1680ae	781	#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
bogdanm	86:04dd9b1680ae	782	((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
bogdanm	86:04dd9b1680ae	783
bogdanm	86:04dd9b1680ae	784
bogdanm	86:04dd9b1680ae	785	/**
bogdanm	86:04dd9b1680ae	786	* @}
bogdanm	86:04dd9b1680ae	787	*/
bogdanm	86:04dd9b1680ae	788
bogdanm	86:04dd9b1680ae	789	/** @defgroup FSMC_PCCARD_Macros
bogdanm	86:04dd9b1680ae	790	* @brief macros to handle SRAM read/write operations
bogdanm	86:04dd9b1680ae	791	* @{
bogdanm	86:04dd9b1680ae	792	*/
bogdanm	86:04dd9b1680ae	793
bogdanm	86:04dd9b1680ae	794	/**
bogdanm	86:04dd9b1680ae	795	* @brief Enable the PCCARD device access.
bogdanm	86:04dd9b1680ae	796	* @param __INSTANCE__: FSMC_PCCARD Instance
bogdanm	86:04dd9b1680ae	797	* @retval none
bogdanm	86:04dd9b1680ae	798	*/
bogdanm	86:04dd9b1680ae	799	#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FSMC_PCR4_PBKEN)
bogdanm	86:04dd9b1680ae	800
bogdanm	86:04dd9b1680ae	801	/**
bogdanm	86:04dd9b1680ae	802	* @brief Disable the PCCARD device access.
bogdanm	86:04dd9b1680ae	803	* @param __INSTANCE__: FSMC_PCCARD Instance
bogdanm	86:04dd9b1680ae	804	* @retval none
bogdanm	86:04dd9b1680ae	805	*/
bogdanm	86:04dd9b1680ae	806	#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
bogdanm	86:04dd9b1680ae	807
bogdanm	86:04dd9b1680ae	808	/**
bogdanm	86:04dd9b1680ae	809	* @}
bogdanm	86:04dd9b1680ae	810	*/
bogdanm	86:04dd9b1680ae	811
bogdanm	86:04dd9b1680ae	812	/** @defgroup FSMC_Interrupt
bogdanm	86:04dd9b1680ae	813	* @brief macros to handle FSMC interrupts
bogdanm	86:04dd9b1680ae	814	* @{
bogdanm	86:04dd9b1680ae	815	*/
bogdanm	86:04dd9b1680ae	816
bogdanm	86:04dd9b1680ae	817	/**
bogdanm	86:04dd9b1680ae	818	* @brief Enable the NAND device interrupt.
bogdanm	86:04dd9b1680ae	819	* @param __INSTANCE__: FSMC_NAND Instance
bogdanm	86:04dd9b1680ae	820	* @param __BANK__: FSMC_NAND Bank
bogdanm	86:04dd9b1680ae	821	* @param __INTERRUPT__: FSMC_NAND interrupt
bogdanm	86:04dd9b1680ae	822	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	823	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	86:04dd9b1680ae	824	* @arg FSMC_IT_LEVEL: Interrupt level.
bogdanm	86:04dd9b1680ae	825	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	86:04dd9b1680ae	826	* @retval None
bogdanm	86:04dd9b1680ae	827	*/
bogdanm	86:04dd9b1680ae	828	#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
bogdanm	86:04dd9b1680ae	829	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
bogdanm	86:04dd9b1680ae	830
bogdanm	86:04dd9b1680ae	831	/**
bogdanm	86:04dd9b1680ae	832	* @brief Disable the NAND device interrupt.
bogdanm	86:04dd9b1680ae	833	* @param __INSTANCE__: FSMC_NAND Instance
bogdanm	86:04dd9b1680ae	834	* @param __BANK__: FSMC_NAND Bank
bogdanm	86:04dd9b1680ae	835	* @param __INTERRUPT__: FSMC_NAND interrupt
bogdanm	86:04dd9b1680ae	836	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	837	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	86:04dd9b1680ae	838	* @arg FSMC_IT_LEVEL: Interrupt level.
bogdanm	86:04dd9b1680ae	839	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	86:04dd9b1680ae	840	* @retval None
bogdanm	86:04dd9b1680ae	841	*/
bogdanm	86:04dd9b1680ae	842	#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
bogdanm	86:04dd9b1680ae	843	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
bogdanm	86:04dd9b1680ae	844
bogdanm	86:04dd9b1680ae	845	/**
bogdanm	86:04dd9b1680ae	846	* @brief Get flag status of the NAND device.
bogdanm	86:04dd9b1680ae	847	* @param __INSTANCE__: FSMC_NAND Instance
bogdanm	86:04dd9b1680ae	848	* @param __BANK__: FSMC_NAND Bank
bogdanm	86:04dd9b1680ae	849	* @param __FLAG__: FSMC_NAND flag
bogdanm	86:04dd9b1680ae	850	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	851	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	86:04dd9b1680ae	852	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	86:04dd9b1680ae	853	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	86:04dd9b1680ae	854	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	86:04dd9b1680ae	855	* @retval The state of FLAG (SET or RESET).
bogdanm	86:04dd9b1680ae	856	*/
bogdanm	86:04dd9b1680ae	857	#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
bogdanm	86:04dd9b1680ae	858	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
bogdanm	86:04dd9b1680ae	859	/**
bogdanm	86:04dd9b1680ae	860	* @brief Clear flag status of the NAND device.
bogdanm	86:04dd9b1680ae	861	* @param __INSTANCE__: FSMC_NAND Instance
bogdanm	86:04dd9b1680ae	862	* @param __BANK__: FSMC_NAND Bank
bogdanm	86:04dd9b1680ae	863	* @param __FLAG__: FSMC_NAND flag
bogdanm	86:04dd9b1680ae	864	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	865	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	86:04dd9b1680ae	866	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	86:04dd9b1680ae	867	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	86:04dd9b1680ae	868	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	86:04dd9b1680ae	869	* @retval None
bogdanm	86:04dd9b1680ae	870	*/
bogdanm	86:04dd9b1680ae	871	#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
bogdanm	86:04dd9b1680ae	872	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
bogdanm	86:04dd9b1680ae	873	/**
bogdanm	86:04dd9b1680ae	874	* @brief Enable the PCCARD device interrupt.
bogdanm	86:04dd9b1680ae	875	* @param __INSTANCE__: FSMC_PCCARD Instance
bogdanm	86:04dd9b1680ae	876	* @param __INTERRUPT__: FSMC_PCCARD interrupt
bogdanm	86:04dd9b1680ae	877	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	878	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	86:04dd9b1680ae	879	* @arg FSMC_IT_LEVEL: Interrupt level.
bogdanm	86:04dd9b1680ae	880	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	86:04dd9b1680ae	881	* @retval None
bogdanm	86:04dd9b1680ae	882	*/
bogdanm	86:04dd9b1680ae	883	#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
bogdanm	86:04dd9b1680ae	884
bogdanm	86:04dd9b1680ae	885	/**
bogdanm	86:04dd9b1680ae	886	* @brief Disable the PCCARD device interrupt.
bogdanm	86:04dd9b1680ae	887	* @param __INSTANCE__: FSMC_PCCARD Instance
bogdanm	86:04dd9b1680ae	888	* @param __INTERRUPT__: FSMC_PCCARD interrupt
bogdanm	86:04dd9b1680ae	889	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	890	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	86:04dd9b1680ae	891	* @arg FSMC_IT_LEVEL: Interrupt level.
bogdanm	86:04dd9b1680ae	892	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	86:04dd9b1680ae	893	* @retval None
bogdanm	86:04dd9b1680ae	894	*/
bogdanm	86:04dd9b1680ae	895	#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
bogdanm	86:04dd9b1680ae	896
bogdanm	86:04dd9b1680ae	897	/**
bogdanm	86:04dd9b1680ae	898	* @brief Get flag status of the PCCARD device.
bogdanm	86:04dd9b1680ae	899	* @param __INSTANCE__: FSMC_PCCARD Instance
bogdanm	86:04dd9b1680ae	900	* @param __FLAG__: FSMC_PCCARD flag
bogdanm	86:04dd9b1680ae	901	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	902	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	86:04dd9b1680ae	903	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	86:04dd9b1680ae	904	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	86:04dd9b1680ae	905	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	86:04dd9b1680ae	906	* @retval The state of FLAG (SET or RESET).
bogdanm	86:04dd9b1680ae	907	*/
bogdanm	86:04dd9b1680ae	908	#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
bogdanm	86:04dd9b1680ae	909
bogdanm	86:04dd9b1680ae	910	/**
bogdanm	86:04dd9b1680ae	911	* @brief Clear flag status of the PCCARD device.
bogdanm	86:04dd9b1680ae	912	* @param __INSTANCE__: FSMC_PCCARD Instance
bogdanm	86:04dd9b1680ae	913	* @param __FLAG__: FSMC_PCCARD flag
bogdanm	86:04dd9b1680ae	914	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	915	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	86:04dd9b1680ae	916	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	86:04dd9b1680ae	917	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	86:04dd9b1680ae	918	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	86:04dd9b1680ae	919	* @retval None
bogdanm	86:04dd9b1680ae	920	*/
bogdanm	86:04dd9b1680ae	921	#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
bogdanm	86:04dd9b1680ae	922
bogdanm	86:04dd9b1680ae	923	/**
bogdanm	86:04dd9b1680ae	924	* @}
bogdanm	86:04dd9b1680ae	925	*/
bogdanm	86:04dd9b1680ae	926
bogdanm	86:04dd9b1680ae	927	/* Exported functions --------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	928
bogdanm	86:04dd9b1680ae	929	/* FSMC_NORSRAM Controller functions ******************************************/
bogdanm	86:04dd9b1680ae	930	/* Initialization/de-initialization functions */
bogdanm	86:04dd9b1680ae	931	HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_InitTypeDef Init);
bogdanm	86:04dd9b1680ae	932	HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
bogdanm	86:04dd9b1680ae	933	HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
bogdanm	86:04dd9b1680ae	934	HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
bogdanm	86:04dd9b1680ae	935
bogdanm	86:04dd9b1680ae	936	/* FSMC_NORSRAM Control functions */
bogdanm	86:04dd9b1680ae	937	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm	86:04dd9b1680ae	938	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm	86:04dd9b1680ae	939
bogdanm	86:04dd9b1680ae	940	/* FSMC_NAND Controller functions *********************************************/
bogdanm	86:04dd9b1680ae	941	/* Initialization/de-initialization functions */
bogdanm	86:04dd9b1680ae	942	HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_InitTypeDef Init);
bogdanm	86:04dd9b1680ae	943	HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
bogdanm	86:04dd9b1680ae	944	HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
bogdanm	86:04dd9b1680ae	945	HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	86:04dd9b1680ae	946
bogdanm	86:04dd9b1680ae	947	/* FSMC_NAND Control functions */
bogdanm	86:04dd9b1680ae	948	HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	86:04dd9b1680ae	949	HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	86:04dd9b1680ae	950	HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
bogdanm	86:04dd9b1680ae	951
bogdanm	86:04dd9b1680ae	952	/* FSMC_PCCARD Controller functions *******************************************/
bogdanm	86:04dd9b1680ae	953	/* Initialization/de-initialization functions */
bogdanm	86:04dd9b1680ae	954	HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef Device, FSMC_PCCARD_InitTypeDef Init);
bogdanm	86:04dd9b1680ae	955	HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	86:04dd9b1680ae	956	HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	86:04dd9b1680ae	957	HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	86:04dd9b1680ae	958	HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
bogdanm	86:04dd9b1680ae	959
bogdanm	86:04dd9b1680ae	960	/* FSMC APIs, macros and typedefs redefinition */
bogdanm	86:04dd9b1680ae	961	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
bogdanm	86:04dd9b1680ae	962	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
bogdanm	86:04dd9b1680ae	963	#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
bogdanm	86:04dd9b1680ae	964	#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
bogdanm	86:04dd9b1680ae	965
bogdanm	86:04dd9b1680ae	966	#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
bogdanm	86:04dd9b1680ae	967	#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
bogdanm	86:04dd9b1680ae	968	#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
bogdanm	86:04dd9b1680ae	969	#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
bogdanm	86:04dd9b1680ae	970	#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
bogdanm	86:04dd9b1680ae	971	#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
bogdanm	86:04dd9b1680ae	972
bogdanm	86:04dd9b1680ae	973	#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
bogdanm	86:04dd9b1680ae	974	#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
bogdanm	86:04dd9b1680ae	975
bogdanm	86:04dd9b1680ae	976	#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
bogdanm	86:04dd9b1680ae	977	#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
bogdanm	86:04dd9b1680ae	978	#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
bogdanm	86:04dd9b1680ae	979
bogdanm	86:04dd9b1680ae	980	#define FMC_NAND_Init FSMC_NAND_Init
bogdanm	86:04dd9b1680ae	981	#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
bogdanm	86:04dd9b1680ae	982	#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
bogdanm	86:04dd9b1680ae	983	#define FMC_NAND_DeInit FSMC_NAND_DeInit
bogdanm	86:04dd9b1680ae	984	#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
bogdanm	86:04dd9b1680ae	985	#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
bogdanm	86:04dd9b1680ae	986	#define FMC_NAND_GetECC FSMC_NAND_GetECC
bogdanm	86:04dd9b1680ae	987	#define FMC_PCCARD_Init FSMC_PCCARD_Init
bogdanm	86:04dd9b1680ae	988	#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
bogdanm	86:04dd9b1680ae	989	#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
bogdanm	86:04dd9b1680ae	990	#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
bogdanm	86:04dd9b1680ae	991	#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
bogdanm	86:04dd9b1680ae	992
bogdanm	86:04dd9b1680ae	993	#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
bogdanm	86:04dd9b1680ae	994	#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
bogdanm	86:04dd9b1680ae	995	#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
bogdanm	86:04dd9b1680ae	996	#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
bogdanm	86:04dd9b1680ae	997	#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
bogdanm	86:04dd9b1680ae	998	#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
bogdanm	86:04dd9b1680ae	999	#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
bogdanm	86:04dd9b1680ae	1000	#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
bogdanm	86:04dd9b1680ae	1001	#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
bogdanm	86:04dd9b1680ae	1002	#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
bogdanm	86:04dd9b1680ae	1003	#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
bogdanm	86:04dd9b1680ae	1004	#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
bogdanm	86:04dd9b1680ae	1005
bogdanm	86:04dd9b1680ae	1006	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
bogdanm	86:04dd9b1680ae	1007	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
bogdanm	86:04dd9b1680ae	1008	#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
bogdanm	86:04dd9b1680ae	1009	#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
bogdanm	86:04dd9b1680ae	1010
bogdanm	86:04dd9b1680ae	1011	#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
bogdanm	86:04dd9b1680ae	1012	#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
bogdanm	86:04dd9b1680ae	1013	#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
bogdanm	86:04dd9b1680ae	1014	#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
bogdanm	86:04dd9b1680ae	1015
bogdanm	86:04dd9b1680ae	1016	#define FMC_NAND_BANK2 FSMC_NAND_BANK2
bogdanm	86:04dd9b1680ae	1017
bogdanm	86:04dd9b1680ae	1018	#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
bogdanm	86:04dd9b1680ae	1019	#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
bogdanm	86:04dd9b1680ae	1020	#define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
bogdanm	86:04dd9b1680ae	1021
bogdanm	86:04dd9b1680ae	1022	#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
bogdanm	86:04dd9b1680ae	1023	#define FMC_IT_LEVEL FSMC_IT_LEVEL
bogdanm	86:04dd9b1680ae	1024	#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
bogdanm	86:04dd9b1680ae	1025	#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
bogdanm	86:04dd9b1680ae	1026
bogdanm	86:04dd9b1680ae	1027	#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
bogdanm	86:04dd9b1680ae	1028	#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
bogdanm	86:04dd9b1680ae	1029	#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
bogdanm	86:04dd9b1680ae	1030	#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
bogdanm	86:04dd9b1680ae	1031
bogdanm	86:04dd9b1680ae	1032	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
bogdanm	86:04dd9b1680ae	1033
bogdanm	86:04dd9b1680ae	1034	/**
bogdanm	86:04dd9b1680ae	1035	* @}
bogdanm	86:04dd9b1680ae	1036	*/
bogdanm	86:04dd9b1680ae	1037
bogdanm	86:04dd9b1680ae	1038	/**
bogdanm	86:04dd9b1680ae	1039	* @}
bogdanm	86:04dd9b1680ae	1040	*/
bogdanm	86:04dd9b1680ae	1041
bogdanm	86:04dd9b1680ae	1042	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	1043	}
bogdanm	86:04dd9b1680ae	1044	#endif
bogdanm	86:04dd9b1680ae	1045
bogdanm	86:04dd9b1680ae	1046	#endif /* __STM32F4xx_LL_FSMC_H */
bogdanm	86:04dd9b1680ae	1047
bogdanm	86:04dd9b1680ae	1048	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/