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TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: 85:024bf7f99721
Child:: 90:cb3d968589d8

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_ll_sdmmc.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
bogdanm	85:024bf7f99721	5	* @version V1.1.0RC2
bogdanm	85:024bf7f99721	6	* @date 14-May-2014
emilmont	77:869cf507173a	7	* @brief Header file of SDMMC HAL module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
emilmont	77:869cf507173a	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_LL_SDMMC_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_LL_SDMMC_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	47	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	48
emilmont	77:869cf507173a	49	/** @addtogroup STM32F4xx_Driver
emilmont	77:869cf507173a	50	* @{
emilmont	77:869cf507173a	51	*/
emilmont	77:869cf507173a	52
emilmont	77:869cf507173a	53	/** @addtogroup SDMMC
emilmont	77:869cf507173a	54	* @{
emilmont	77:869cf507173a	55	*/
emilmont	77:869cf507173a	56
emilmont	77:869cf507173a	57	/* Exported types ------------------------------------------------------------*/
emilmont	77:869cf507173a	58
emilmont	77:869cf507173a	59	/**
emilmont	77:869cf507173a	60	* @brief SDMMC Configuration Structure definition
emilmont	77:869cf507173a	61	*/
emilmont	77:869cf507173a	62	typedef struct
emilmont	77:869cf507173a	63	{
emilmont	77:869cf507173a	64	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
emilmont	77:869cf507173a	65	This parameter can be a value of @ref SDIO_Clock_Edge */
emilmont	77:869cf507173a	66
emilmont	77:869cf507173a	67	uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
emilmont	77:869cf507173a	68	enabled or disabled.
emilmont	77:869cf507173a	69	This parameter can be a value of @ref SDIO_Clock_Bypass */
emilmont	77:869cf507173a	70
emilmont	77:869cf507173a	71	uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
emilmont	77:869cf507173a	72	disabled when the bus is idle.
emilmont	77:869cf507173a	73	This parameter can be a value of @ref SDIO_Clock_Power_Save */
emilmont	77:869cf507173a	74
emilmont	77:869cf507173a	75	uint32_t BusWide; /*!< Specifies the SDIO bus width.
emilmont	77:869cf507173a	76	This parameter can be a value of @ref SDIO_Bus_Wide */
emilmont	77:869cf507173a	77
emilmont	77:869cf507173a	78	uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
emilmont	77:869cf507173a	79	This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
emilmont	77:869cf507173a	80
emilmont	77:869cf507173a	81	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
emilmont	77:869cf507173a	82	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
emilmont	77:869cf507173a	83
emilmont	77:869cf507173a	84	}SDIO_InitTypeDef;
emilmont	77:869cf507173a	85
emilmont	77:869cf507173a	86
emilmont	77:869cf507173a	87	/**
emilmont	77:869cf507173a	88	* @brief SDIO Command Control structure
emilmont	77:869cf507173a	89	*/
emilmont	77:869cf507173a	90	typedef struct
emilmont	77:869cf507173a	91	{
emilmont	77:869cf507173a	92	uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
emilmont	77:869cf507173a	93	to a card as part of a command message. If a command
emilmont	77:869cf507173a	94	contains an argument, it must be loaded into this register
emilmont	77:869cf507173a	95	before writing the command to the command register. */
emilmont	77:869cf507173a	96
emilmont	77:869cf507173a	97	uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
emilmont	77:869cf507173a	98	Max_Data = 64 */
emilmont	77:869cf507173a	99
emilmont	77:869cf507173a	100	uint32_t Response; /*!< Specifies the SDIO response type.
emilmont	77:869cf507173a	101	This parameter can be a value of @ref SDIO_Response_Type */
emilmont	77:869cf507173a	102
emilmont	77:869cf507173a	103	uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
emilmont	77:869cf507173a	104	enabled or disabled.
emilmont	77:869cf507173a	105	This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
emilmont	77:869cf507173a	106
emilmont	77:869cf507173a	107	uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
emilmont	77:869cf507173a	108	is enabled or disabled.
emilmont	77:869cf507173a	109	This parameter can be a value of @ref SDIO_CPSM_State */
emilmont	77:869cf507173a	110	}SDIO_CmdInitTypeDef;
emilmont	77:869cf507173a	111
emilmont	77:869cf507173a	112
emilmont	77:869cf507173a	113	/**
emilmont	77:869cf507173a	114	* @brief SDIO Data Control structure
emilmont	77:869cf507173a	115	*/
emilmont	77:869cf507173a	116	typedef struct
emilmont	77:869cf507173a	117	{
emilmont	77:869cf507173a	118	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
emilmont	77:869cf507173a	119
emilmont	77:869cf507173a	120	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
emilmont	77:869cf507173a	121
emilmont	77:869cf507173a	122	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
emilmont	77:869cf507173a	123	This parameter can be a value of @ref SDIO_Data_Block_Size */
emilmont	77:869cf507173a	124
emilmont	77:869cf507173a	125	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
emilmont	77:869cf507173a	126	is a read or write.
emilmont	77:869cf507173a	127	This parameter can be a value of @ref SDIO_Transfer_Direction */
emilmont	77:869cf507173a	128
emilmont	77:869cf507173a	129	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
emilmont	77:869cf507173a	130	This parameter can be a value of @ref SDIO_Transfer_Type */
emilmont	77:869cf507173a	131
emilmont	77:869cf507173a	132	uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
emilmont	77:869cf507173a	133	is enabled or disabled.
emilmont	77:869cf507173a	134	This parameter can be a value of @ref SDIO_DPSM_State */
emilmont	77:869cf507173a	135	}SDIO_DataInitTypeDef;
emilmont	77:869cf507173a	136
emilmont	77:869cf507173a	137	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	138
emilmont	77:869cf507173a	139	/** @defgroup SDIO_Exported_Constants
emilmont	77:869cf507173a	140	* @{
emilmont	77:869cf507173a	141	*/
emilmont	77:869cf507173a	142
emilmont	77:869cf507173a	143	/** @defgroup SDIO_Clock_Edge
emilmont	77:869cf507173a	144	* @{
emilmont	77:869cf507173a	145	*/
emilmont	77:869cf507173a	146	#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
emilmont	77:869cf507173a	147	#define SDIO_CLOCK_EDGE_FALLING ((uint32_t)0x00002000)
emilmont	77:869cf507173a	148
emilmont	77:869cf507173a	149	#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) \|\| \
emilmont	77:869cf507173a	150	((EDGE) == SDIO_CLOCK_EDGE_FALLING))
emilmont	77:869cf507173a	151	/**
emilmont	77:869cf507173a	152	* @}
emilmont	77:869cf507173a	153	*/
emilmont	77:869cf507173a	154
emilmont	77:869cf507173a	155	/** @defgroup SDIO_Clock_Bypass
emilmont	77:869cf507173a	156	* @{
emilmont	77:869cf507173a	157	*/
emilmont	77:869cf507173a	158	#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	159	#define SDIO_CLOCK_BYPASS_ENABLE ((uint32_t)0x00000400)
emilmont	77:869cf507173a	160
emilmont	77:869cf507173a	161	#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) \|\| \
emilmont	77:869cf507173a	162	((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
emilmont	77:869cf507173a	163	/**
emilmont	77:869cf507173a	164	* @}
emilmont	77:869cf507173a	165	*/
emilmont	77:869cf507173a	166
emilmont	77:869cf507173a	167	/** @defgroup SDIO_Clock_Power_Save
emilmont	77:869cf507173a	168	* @{
emilmont	77:869cf507173a	169	*/
emilmont	77:869cf507173a	170	#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	171	#define SDIO_CLOCK_POWER_SAVE_ENABLE ((uint32_t)0x00000200)
emilmont	77:869cf507173a	172
emilmont	77:869cf507173a	173	#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) \|\| \
emilmont	77:869cf507173a	174	((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
emilmont	77:869cf507173a	175	/**
emilmont	77:869cf507173a	176	* @}
emilmont	77:869cf507173a	177	*/
emilmont	77:869cf507173a	178
emilmont	77:869cf507173a	179	/** @defgroup SDIO_Bus_Wide
emilmont	77:869cf507173a	180	* @{
emilmont	77:869cf507173a	181	*/
emilmont	77:869cf507173a	182	#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
emilmont	77:869cf507173a	183	#define SDIO_BUS_WIDE_4B ((uint32_t)0x00000800)
emilmont	77:869cf507173a	184	#define SDIO_BUS_WIDE_8B ((uint32_t)0x00001000)
emilmont	77:869cf507173a	185
emilmont	77:869cf507173a	186	#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) \|\| \
emilmont	77:869cf507173a	187	((WIDE) == SDIO_BUS_WIDE_4B) \|\| \
emilmont	77:869cf507173a	188	((WIDE) == SDIO_BUS_WIDE_8B))
emilmont	77:869cf507173a	189	/**
emilmont	77:869cf507173a	190	* @}
emilmont	77:869cf507173a	191	*/
emilmont	77:869cf507173a	192
emilmont	77:869cf507173a	193	/** @defgroup SDIO_Hardware_Flow_Control
emilmont	77:869cf507173a	194	* @{
emilmont	77:869cf507173a	195	*/
emilmont	77:869cf507173a	196	#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	197	#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE ((uint32_t)0x00004000)
emilmont	77:869cf507173a	198
emilmont	77:869cf507173a	199	#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
emilmont	77:869cf507173a	200	((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
emilmont	77:869cf507173a	201	/**
emilmont	77:869cf507173a	202	* @}
emilmont	77:869cf507173a	203	*/
emilmont	77:869cf507173a	204
emilmont	77:869cf507173a	205	/** @defgroup SDIO_Clock_Division
emilmont	77:869cf507173a	206	* @{
emilmont	77:869cf507173a	207	*/
emilmont	77:869cf507173a	208	#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
emilmont	77:869cf507173a	209	/**
emilmont	77:869cf507173a	210	* @}
emilmont	77:869cf507173a	211	*/
emilmont	77:869cf507173a	212
emilmont	77:869cf507173a	213	/**
emilmont	77:869cf507173a	214	* @}
emilmont	77:869cf507173a	215	*/
emilmont	77:869cf507173a	216
emilmont	77:869cf507173a	217	/** @defgroup SDIO_Command_Index
emilmont	77:869cf507173a	218	* @{
emilmont	77:869cf507173a	219	*/
emilmont	77:869cf507173a	220	#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
emilmont	77:869cf507173a	221	/**
emilmont	77:869cf507173a	222	* @}
emilmont	77:869cf507173a	223	*/
emilmont	77:869cf507173a	224
emilmont	77:869cf507173a	225	/** @defgroup SDIO_Response_Type
emilmont	77:869cf507173a	226	* @{
emilmont	77:869cf507173a	227	*/
emilmont	77:869cf507173a	228	#define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
emilmont	77:869cf507173a	229	#define SDIO_RESPONSE_SHORT ((uint32_t)0x00000040)
emilmont	77:869cf507173a	230	#define SDIO_RESPONSE_LONG ((uint32_t)0x000000C0)
emilmont	77:869cf507173a	231
emilmont	77:869cf507173a	232	#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) \|\| \
emilmont	77:869cf507173a	233	((RESPONSE) == SDIO_RESPONSE_SHORT) \|\| \
emilmont	77:869cf507173a	234	((RESPONSE) == SDIO_RESPONSE_LONG))
emilmont	77:869cf507173a	235	/**
emilmont	77:869cf507173a	236	* @}
emilmont	77:869cf507173a	237	*/
emilmont	77:869cf507173a	238
emilmont	77:869cf507173a	239	/** @defgroup SDIO_Wait_Interrupt_State
emilmont	77:869cf507173a	240	* @{
emilmont	77:869cf507173a	241	*/
emilmont	77:869cf507173a	242	#define SDIO_WAIT_NO ((uint32_t)0x00000000)
emilmont	77:869cf507173a	243	#define SDIO_WAIT_IT ((uint32_t)0x00000100)
emilmont	77:869cf507173a	244	#define SDIO_WAIT_PEND ((uint32_t)0x00000200)
emilmont	77:869cf507173a	245
emilmont	77:869cf507173a	246	#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) \|\| \
emilmont	77:869cf507173a	247	((WAIT) == SDIO_WAIT_IT) \|\| \
emilmont	77:869cf507173a	248	((WAIT) == SDIO_WAIT_PEND))
emilmont	77:869cf507173a	249	/**
emilmont	77:869cf507173a	250	* @}
emilmont	77:869cf507173a	251	*/
emilmont	77:869cf507173a	252
emilmont	77:869cf507173a	253	/** @defgroup SDIO_CPSM_State
emilmont	77:869cf507173a	254	* @{
emilmont	77:869cf507173a	255	*/
emilmont	77:869cf507173a	256	#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	257	#define SDIO_CPSM_ENABLE ((uint32_t)0x00000400)
emilmont	77:869cf507173a	258
emilmont	77:869cf507173a	259	#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) \|\| \
emilmont	77:869cf507173a	260	((CPSM) == SDIO_CPSM_ENABLE))
emilmont	77:869cf507173a	261	/**
emilmont	77:869cf507173a	262	* @}
emilmont	77:869cf507173a	263	*/
emilmont	77:869cf507173a	264
emilmont	77:869cf507173a	265	/** @defgroup SDIO_Response_Registers
emilmont	77:869cf507173a	266	* @{
emilmont	77:869cf507173a	267	*/
emilmont	77:869cf507173a	268	#define SDIO_RESP1 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	269	#define SDIO_RESP2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	270	#define SDIO_RESP3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	271	#define SDIO_RESP4 ((uint32_t)0x0000000C)
emilmont	77:869cf507173a	272
emilmont	77:869cf507173a	273	#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) \|\| \
emilmont	77:869cf507173a	274	((RESP) == SDIO_RESP2) \|\| \
emilmont	77:869cf507173a	275	((RESP) == SDIO_RESP3) \|\| \
emilmont	77:869cf507173a	276	((RESP) == SDIO_RESP4))
emilmont	77:869cf507173a	277	/**
emilmont	77:869cf507173a	278	* @}
emilmont	77:869cf507173a	279	*/
emilmont	77:869cf507173a	280
emilmont	77:869cf507173a	281	/** @defgroup SDIO_Data_Length
emilmont	77:869cf507173a	282	* @{
emilmont	77:869cf507173a	283	*/
emilmont	77:869cf507173a	284	#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
emilmont	77:869cf507173a	285	/**
emilmont	77:869cf507173a	286	* @}
emilmont	77:869cf507173a	287	*/
emilmont	77:869cf507173a	288
emilmont	77:869cf507173a	289	/** @defgroup SDIO_Data_Block_Size
emilmont	77:869cf507173a	290	* @{
emilmont	77:869cf507173a	291	*/
emilmont	77:869cf507173a	292	#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
emilmont	77:869cf507173a	293	#define SDIO_DATABLOCK_SIZE_2B ((uint32_t)0x00000010)
emilmont	77:869cf507173a	294	#define SDIO_DATABLOCK_SIZE_4B ((uint32_t)0x00000020)
emilmont	77:869cf507173a	295	#define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
emilmont	77:869cf507173a	296	#define SDIO_DATABLOCK_SIZE_16B ((uint32_t)0x00000040)
emilmont	77:869cf507173a	297	#define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
emilmont	77:869cf507173a	298	#define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
emilmont	77:869cf507173a	299	#define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
emilmont	77:869cf507173a	300	#define SDIO_DATABLOCK_SIZE_256B ((uint32_t)0x00000080)
emilmont	77:869cf507173a	301	#define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
emilmont	77:869cf507173a	302	#define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
emilmont	77:869cf507173a	303	#define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
emilmont	77:869cf507173a	304	#define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
emilmont	77:869cf507173a	305	#define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
emilmont	77:869cf507173a	306	#define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
emilmont	77:869cf507173a	307
emilmont	77:869cf507173a	308	#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) \|\| \
emilmont	77:869cf507173a	309	((SIZE) == SDIO_DATABLOCK_SIZE_2B) \|\| \
emilmont	77:869cf507173a	310	((SIZE) == SDIO_DATABLOCK_SIZE_4B) \|\| \
emilmont	77:869cf507173a	311	((SIZE) == SDIO_DATABLOCK_SIZE_8B) \|\| \
emilmont	77:869cf507173a	312	((SIZE) == SDIO_DATABLOCK_SIZE_16B) \|\| \
emilmont	77:869cf507173a	313	((SIZE) == SDIO_DATABLOCK_SIZE_32B) \|\| \
emilmont	77:869cf507173a	314	((SIZE) == SDIO_DATABLOCK_SIZE_64B) \|\| \
emilmont	77:869cf507173a	315	((SIZE) == SDIO_DATABLOCK_SIZE_128B) \|\| \
emilmont	77:869cf507173a	316	((SIZE) == SDIO_DATABLOCK_SIZE_256B) \|\| \
emilmont	77:869cf507173a	317	((SIZE) == SDIO_DATABLOCK_SIZE_512B) \|\| \
emilmont	77:869cf507173a	318	((SIZE) == SDIO_DATABLOCK_SIZE_1024B) \|\| \
emilmont	77:869cf507173a	319	((SIZE) == SDIO_DATABLOCK_SIZE_2048B) \|\| \
emilmont	77:869cf507173a	320	((SIZE) == SDIO_DATABLOCK_SIZE_4096B) \|\| \
emilmont	77:869cf507173a	321	((SIZE) == SDIO_DATABLOCK_SIZE_8192B) \|\| \
emilmont	77:869cf507173a	322	((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
emilmont	77:869cf507173a	323	/**
emilmont	77:869cf507173a	324	* @}
emilmont	77:869cf507173a	325	*/
emilmont	77:869cf507173a	326
emilmont	77:869cf507173a	327	/** @defgroup SDIO_Transfer_Direction
emilmont	77:869cf507173a	328	* @{
emilmont	77:869cf507173a	329	*/
emilmont	77:869cf507173a	330	#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
emilmont	77:869cf507173a	331	#define SDIO_TRANSFER_DIR_TO_SDIO ((uint32_t)0x00000002)
emilmont	77:869cf507173a	332
emilmont	77:869cf507173a	333	#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) \|\| \
emilmont	77:869cf507173a	334	((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
emilmont	77:869cf507173a	335	/**
emilmont	77:869cf507173a	336	* @}
emilmont	77:869cf507173a	337	*/
emilmont	77:869cf507173a	338
emilmont	77:869cf507173a	339	/** @defgroup SDIO_Transfer_Type
emilmont	77:869cf507173a	340	* @{
emilmont	77:869cf507173a	341	*/
emilmont	77:869cf507173a	342	#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
emilmont	77:869cf507173a	343	#define SDIO_TRANSFER_MODE_STREAM ((uint32_t)0x00000004)
emilmont	77:869cf507173a	344
emilmont	77:869cf507173a	345	#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) \|\| \
emilmont	77:869cf507173a	346	((MODE) == SDIO_TRANSFER_MODE_STREAM))
emilmont	77:869cf507173a	347	/**
emilmont	77:869cf507173a	348	* @}
emilmont	77:869cf507173a	349	*/
emilmont	77:869cf507173a	350
emilmont	77:869cf507173a	351	/** @defgroup SDIO_DPSM_State
emilmont	77:869cf507173a	352	* @{
emilmont	77:869cf507173a	353	*/
emilmont	77:869cf507173a	354	#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	355	#define SDIO_DPSM_ENABLE ((uint32_t)0x00000001)
emilmont	77:869cf507173a	356
emilmont	77:869cf507173a	357	#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) \|\|\
emilmont	77:869cf507173a	358	((DPSM) == SDIO_DPSM_ENABLE))
emilmont	77:869cf507173a	359	/**
emilmont	77:869cf507173a	360	* @}
emilmont	77:869cf507173a	361	*/
emilmont	77:869cf507173a	362
emilmont	77:869cf507173a	363	/** @defgroup SDIO_Read_Wait_Mode
emilmont	77:869cf507173a	364	* @{
emilmont	77:869cf507173a	365	*/
emilmont	77:869cf507173a	366	#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
emilmont	77:869cf507173a	367	#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	368
emilmont	77:869cf507173a	369	#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) \|\| \
emilmont	77:869cf507173a	370	((MODE) == SDIO_READ_WAIT_MODE_DATA2))
emilmont	77:869cf507173a	371	/**
emilmont	77:869cf507173a	372	* @}
emilmont	77:869cf507173a	373	*/
emilmont	77:869cf507173a	374
emilmont	77:869cf507173a	375	/** @defgroup SDIO_Interrupt_sources
emilmont	77:869cf507173a	376	* @{
emilmont	77:869cf507173a	377	*/
emilmont	77:869cf507173a	378	#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
emilmont	77:869cf507173a	379	#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
emilmont	77:869cf507173a	380	#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
emilmont	77:869cf507173a	381	#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
emilmont	77:869cf507173a	382	#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
emilmont	77:869cf507173a	383	#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
emilmont	77:869cf507173a	384	#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
emilmont	77:869cf507173a	385	#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
emilmont	77:869cf507173a	386	#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
emilmont	77:869cf507173a	387	#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
emilmont	77:869cf507173a	388	#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
emilmont	77:869cf507173a	389	#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
emilmont	77:869cf507173a	390	#define SDIO_IT_TXACT ((uint32_t)0x00001000)
emilmont	77:869cf507173a	391	#define SDIO_IT_RXACT ((uint32_t)0x00002000)
emilmont	77:869cf507173a	392	#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
emilmont	77:869cf507173a	393	#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
emilmont	77:869cf507173a	394	#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
emilmont	77:869cf507173a	395	#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
emilmont	77:869cf507173a	396	#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
emilmont	77:869cf507173a	397	#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
emilmont	77:869cf507173a	398	#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
emilmont	77:869cf507173a	399	#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
emilmont	77:869cf507173a	400	#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
emilmont	77:869cf507173a	401	#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
emilmont	77:869cf507173a	402
emilmont	77:869cf507173a	403	#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
emilmont	77:869cf507173a	404	/**
emilmont	77:869cf507173a	405	* @}
emilmont	77:869cf507173a	406	*/
emilmont	77:869cf507173a	407
emilmont	77:869cf507173a	408	/** @defgroup SDIO_Flags
emilmont	77:869cf507173a	409	* @{
emilmont	77:869cf507173a	410	*/
emilmont	77:869cf507173a	411	#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
emilmont	77:869cf507173a	412	#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
emilmont	77:869cf507173a	413	#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
emilmont	77:869cf507173a	414	#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
emilmont	77:869cf507173a	415	#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
emilmont	77:869cf507173a	416	#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
emilmont	77:869cf507173a	417	#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
emilmont	77:869cf507173a	418	#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
emilmont	77:869cf507173a	419	#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
emilmont	77:869cf507173a	420	#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
emilmont	77:869cf507173a	421	#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
emilmont	77:869cf507173a	422	#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
emilmont	77:869cf507173a	423	#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
emilmont	77:869cf507173a	424	#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
emilmont	77:869cf507173a	425	#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
emilmont	77:869cf507173a	426	#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
emilmont	77:869cf507173a	427	#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
emilmont	77:869cf507173a	428	#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
emilmont	77:869cf507173a	429	#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
emilmont	77:869cf507173a	430	#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
emilmont	77:869cf507173a	431	#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
emilmont	77:869cf507173a	432	#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
emilmont	77:869cf507173a	433	#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
emilmont	77:869cf507173a	434	#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
emilmont	77:869cf507173a	435
emilmont	77:869cf507173a	436	#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) \|\| \
emilmont	77:869cf507173a	437	((FLAG) == SDIO_FLAG_DCRCFAIL) \|\| \
emilmont	77:869cf507173a	438	((FLAG) == SDIO_FLAG_CTIMEOUT) \|\| \
emilmont	77:869cf507173a	439	((FLAG) == SDIO_FLAG_DTIMEOUT) \|\| \
emilmont	77:869cf507173a	440	((FLAG) == SDIO_FLAG_TXUNDERR) \|\| \
emilmont	77:869cf507173a	441	((FLAG) == SDIO_FLAG_RXOVERR) \|\| \
emilmont	77:869cf507173a	442	((FLAG) == SDIO_FLAG_CMDREND) \|\| \
emilmont	77:869cf507173a	443	((FLAG) == SDIO_FLAG_CMDSENT) \|\| \
emilmont	77:869cf507173a	444	((FLAG) == SDIO_FLAG_DATAEND) \|\| \
emilmont	77:869cf507173a	445	((FLAG) == SDIO_FLAG_STBITERR) \|\| \
emilmont	77:869cf507173a	446	((FLAG) == SDIO_FLAG_DBCKEND) \|\| \
emilmont	77:869cf507173a	447	((FLAG) == SDIO_FLAG_CMDACT) \|\| \
emilmont	77:869cf507173a	448	((FLAG) == SDIO_FLAG_TXACT) \|\| \
emilmont	77:869cf507173a	449	((FLAG) == SDIO_FLAG_RXACT) \|\| \
emilmont	77:869cf507173a	450	((FLAG) == SDIO_FLAG_TXFIFOHE) \|\| \
emilmont	77:869cf507173a	451	((FLAG) == SDIO_FLAG_RXFIFOHF) \|\| \
emilmont	77:869cf507173a	452	((FLAG) == SDIO_FLAG_TXFIFOF) \|\| \
emilmont	77:869cf507173a	453	((FLAG) == SDIO_FLAG_RXFIFOF) \|\| \
emilmont	77:869cf507173a	454	((FLAG) == SDIO_FLAG_TXFIFOE) \|\| \
emilmont	77:869cf507173a	455	((FLAG) == SDIO_FLAG_RXFIFOE) \|\| \
emilmont	77:869cf507173a	456	((FLAG) == SDIO_FLAG_TXDAVL) \|\| \
emilmont	77:869cf507173a	457	((FLAG) == SDIO_FLAG_RXDAVL) \|\| \
emilmont	77:869cf507173a	458	((FLAG) == SDIO_FLAG_SDIOIT) \|\| \
emilmont	77:869cf507173a	459	((FLAG) == SDIO_FLAG_CEATAEND))
emilmont	77:869cf507173a	460
emilmont	77:869cf507173a	461	#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
emilmont	77:869cf507173a	462
emilmont	77:869cf507173a	463	#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) \|\| \
emilmont	77:869cf507173a	464	((IT) == SDIO_IT_DCRCFAIL) \|\| \
emilmont	77:869cf507173a	465	((IT) == SDIO_IT_CTIMEOUT) \|\| \
emilmont	77:869cf507173a	466	((IT) == SDIO_IT_DTIMEOUT) \|\| \
emilmont	77:869cf507173a	467	((IT) == SDIO_IT_TXUNDERR) \|\| \
emilmont	77:869cf507173a	468	((IT) == SDIO_IT_RXOVERR) \|\| \
emilmont	77:869cf507173a	469	((IT) == SDIO_IT_CMDREND) \|\| \
emilmont	77:869cf507173a	470	((IT) == SDIO_IT_CMDSENT) \|\| \
emilmont	77:869cf507173a	471	((IT) == SDIO_IT_DATAEND) \|\| \
emilmont	77:869cf507173a	472	((IT) == SDIO_IT_STBITERR) \|\| \
emilmont	77:869cf507173a	473	((IT) == SDIO_IT_DBCKEND) \|\| \
emilmont	77:869cf507173a	474	((IT) == SDIO_IT_CMDACT) \|\| \
emilmont	77:869cf507173a	475	((IT) == SDIO_IT_TXACT) \|\| \
emilmont	77:869cf507173a	476	((IT) == SDIO_IT_RXACT) \|\| \
emilmont	77:869cf507173a	477	((IT) == SDIO_IT_TXFIFOHE) \|\| \
emilmont	77:869cf507173a	478	((IT) == SDIO_IT_RXFIFOHF) \|\| \
emilmont	77:869cf507173a	479	((IT) == SDIO_IT_TXFIFOF) \|\| \
emilmont	77:869cf507173a	480	((IT) == SDIO_IT_RXFIFOF) \|\| \
emilmont	77:869cf507173a	481	((IT) == SDIO_IT_TXFIFOE) \|\| \
emilmont	77:869cf507173a	482	((IT) == SDIO_IT_RXFIFOE) \|\| \
emilmont	77:869cf507173a	483	((IT) == SDIO_IT_TXDAVL) \|\| \
emilmont	77:869cf507173a	484	((IT) == SDIO_IT_RXDAVL) \|\| \
emilmont	77:869cf507173a	485	((IT) == SDIO_IT_SDIOIT) \|\| \
emilmont	77:869cf507173a	486	((IT) == SDIO_IT_CEATAEND))
emilmont	77:869cf507173a	487
emilmont	77:869cf507173a	488	#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
emilmont	77:869cf507173a	489
emilmont	77:869cf507173a	490	/**
emilmont	77:869cf507173a	491	* @}
emilmont	77:869cf507173a	492	*/
emilmont	77:869cf507173a	493
emilmont	77:869cf507173a	494
emilmont	77:869cf507173a	495	/** @defgroup SDIO_Instance_definition
emilmont	77:869cf507173a	496	* @{
emilmont	77:869cf507173a	497	*/
emilmont	77:869cf507173a	498	#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
emilmont	77:869cf507173a	499
emilmont	77:869cf507173a	500	/**
emilmont	77:869cf507173a	501	* @}
emilmont	77:869cf507173a	502	*/
emilmont	77:869cf507173a	503
emilmont	77:869cf507173a	504	/* Exported macro ------------------------------------------------------------*/
emilmont	77:869cf507173a	505	/* ------------ SDIO registers bit address in the alias region -------------- */
emilmont	77:869cf507173a	506	#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
emilmont	77:869cf507173a	507
emilmont	77:869cf507173a	508	/* --- CLKCR Register ---*/
emilmont	77:869cf507173a	509	/* Alias word address of CLKEN bit */
emilmont	77:869cf507173a	510	#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
emilmont	77:869cf507173a	511	#define CLKEN_BitNumber 0x08
emilmont	77:869cf507173a	512	#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
emilmont	77:869cf507173a	513
emilmont	77:869cf507173a	514	/* --- CMD Register ---*/
emilmont	77:869cf507173a	515	/* Alias word address of SDIOSUSPEND bit */
emilmont	77:869cf507173a	516	#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
emilmont	77:869cf507173a	517	#define SDIOSUSPEND_BitNumber 0x0B
emilmont	77:869cf507173a	518	#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
emilmont	77:869cf507173a	519
emilmont	77:869cf507173a	520	/* Alias word address of ENCMDCOMPL bit */
emilmont	77:869cf507173a	521	#define ENCMDCOMPL_BitNumber 0x0C
emilmont	77:869cf507173a	522	#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
emilmont	77:869cf507173a	523
emilmont	77:869cf507173a	524	/* Alias word address of NIEN bit */
emilmont	77:869cf507173a	525	#define NIEN_BitNumber 0x0D
emilmont	77:869cf507173a	526	#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
emilmont	77:869cf507173a	527
emilmont	77:869cf507173a	528	/* Alias word address of ATACMD bit */
emilmont	77:869cf507173a	529	#define ATACMD_BitNumber 0x0E
emilmont	77:869cf507173a	530	#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
emilmont	77:869cf507173a	531
emilmont	77:869cf507173a	532	/* --- DCTRL Register ---*/
emilmont	77:869cf507173a	533	/* Alias word address of DMAEN bit */
emilmont	77:869cf507173a	534	#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
emilmont	77:869cf507173a	535	#define DMAEN_BitNumber 0x03
emilmont	77:869cf507173a	536	#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
emilmont	77:869cf507173a	537
emilmont	77:869cf507173a	538	/* Alias word address of RWSTART bit */
emilmont	77:869cf507173a	539	#define RWSTART_BitNumber 0x08
emilmont	77:869cf507173a	540	#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
emilmont	77:869cf507173a	541
emilmont	77:869cf507173a	542	/* Alias word address of RWSTOP bit */
emilmont	77:869cf507173a	543	#define RWSTOP_BitNumber 0x09
emilmont	77:869cf507173a	544	#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
emilmont	77:869cf507173a	545
emilmont	77:869cf507173a	546	/* Alias word address of RWMOD bit */
emilmont	77:869cf507173a	547	#define RWMOD_BitNumber 0x0A
emilmont	77:869cf507173a	548	#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
emilmont	77:869cf507173a	549
emilmont	77:869cf507173a	550	/* Alias word address of SDIOEN bit */
emilmont	77:869cf507173a	551	#define SDIOEN_BitNumber 0x0B
emilmont	77:869cf507173a	552	#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
emilmont	77:869cf507173a	553
emilmont	77:869cf507173a	554	/* ---------------------- SDIO registers bit mask --------------------------- */
emilmont	77:869cf507173a	555	/* --- CLKCR Register ---*/
emilmont	77:869cf507173a	556	/* CLKCR register clear mask */
emilmont	77:869cf507173a	557	#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
emilmont	77:869cf507173a	558
emilmont	77:869cf507173a	559	/* --- PWRCTRL Register ---*/
emilmont	77:869cf507173a	560	/* SDIO PWRCTRL Mask */
emilmont	77:869cf507173a	561	#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
emilmont	77:869cf507173a	562
emilmont	77:869cf507173a	563	/* --- DCTRL Register ---*/
emilmont	77:869cf507173a	564	/* SDIO DCTRL Clear Mask */
emilmont	77:869cf507173a	565	#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
emilmont	77:869cf507173a	566
emilmont	77:869cf507173a	567	/* --- CMD Register ---*/
emilmont	77:869cf507173a	568	/* CMD Register clear mask */
emilmont	77:869cf507173a	569	#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
emilmont	77:869cf507173a	570
emilmont	77:869cf507173a	571	/* SDIO RESP Registers Address */
emilmont	77:869cf507173a	572	#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
emilmont	77:869cf507173a	573
emilmont	77:869cf507173a	574	/* SD FLASH SDIO Interface */
emilmont	77:869cf507173a	575	#define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80)
emilmont	77:869cf507173a	576
emilmont	77:869cf507173a	577	/* SDIO Intialization Frequency (400KHz max) */
emilmont	77:869cf507173a	578	#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
emilmont	77:869cf507173a	579
emilmont	77:869cf507173a	580	/* SDIO Data Transfer Frequency (25MHz max) */
emilmont	77:869cf507173a	581	#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
emilmont	77:869cf507173a	582
emilmont	77:869cf507173a	583	/** @defgroup SDIO_Interrupt_Clock
emilmont	77:869cf507173a	584	* @brief macros to handle interrupts and specific clock configurations
emilmont	77:869cf507173a	585	* @{
emilmont	77:869cf507173a	586	*/
emilmont	77:869cf507173a	587
emilmont	77:869cf507173a	588	/**
emilmont	77:869cf507173a	589	* @brief Enable the SDIO device.
emilmont	77:869cf507173a	590	* @param None
emilmont	77:869cf507173a	591	* @retval None
emilmont	77:869cf507173a	592	*/
emilmont	77:869cf507173a	593	#define __SDIO_ENABLE() ((__IO uint32_t )CLKCR_CLKEN_BB = ENABLE)
emilmont	77:869cf507173a	594
emilmont	77:869cf507173a	595	/**
emilmont	77:869cf507173a	596	* @brief Disable the SDIO device.
emilmont	77:869cf507173a	597	* @param None
emilmont	77:869cf507173a	598	* @retval None
emilmont	77:869cf507173a	599	*/
emilmont	77:869cf507173a	600	#define __SDIO_DISABLE() ((__IO uint32_t )CLKCR_CLKEN_BB = DISABLE)
emilmont	77:869cf507173a	601
emilmont	77:869cf507173a	602	/**
emilmont	77:869cf507173a	603	* @brief Enable the SDIO DMA transfer.
emilmont	77:869cf507173a	604	* @param None
emilmont	77:869cf507173a	605	* @retval None
emilmont	77:869cf507173a	606	*/
emilmont	77:869cf507173a	607	#define __SDIO_DMA_ENABLE() ((__IO uint32_t )DCTRL_DMAEN_BB = ENABLE)
emilmont	77:869cf507173a	608
emilmont	77:869cf507173a	609	/**
emilmont	77:869cf507173a	610	* @brief Disable the SDIO DMA transfer.
emilmont	77:869cf507173a	611	* @param None
emilmont	77:869cf507173a	612	* @retval None
emilmont	77:869cf507173a	613	*/
emilmont	77:869cf507173a	614	#define __SDIO_DMA_DISABLE() ((__IO uint32_t )DCTRL_DMAEN_BB = DISABLE)
emilmont	77:869cf507173a	615
emilmont	77:869cf507173a	616	/**
emilmont	77:869cf507173a	617	* @brief Enable the SDIO device interrupt.
emilmont	77:869cf507173a	618	* @param __INSTANCE__ : Pointer to SDIO register base
emilmont	77:869cf507173a	619	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
emilmont	77:869cf507173a	620	* This parameter can be one or a combination of the following values:
emilmont	77:869cf507173a	621	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
emilmont	77:869cf507173a	622	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
emilmont	77:869cf507173a	623	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
emilmont	77:869cf507173a	624	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
emilmont	77:869cf507173a	625	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
emilmont	77:869cf507173a	626	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
emilmont	77:869cf507173a	627	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
emilmont	77:869cf507173a	628	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
emilmont	77:869cf507173a	629	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
emilmont	77:869cf507173a	630	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
emilmont	77:869cf507173a	631	* bus mode interrupt
emilmont	77:869cf507173a	632	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
emilmont	77:869cf507173a	633	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
emilmont	77:869cf507173a	634	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
emilmont	77:869cf507173a	635	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
emilmont	77:869cf507173a	636	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
emilmont	77:869cf507173a	637	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
emilmont	77:869cf507173a	638	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
emilmont	77:869cf507173a	639	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
emilmont	77:869cf507173a	640	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
emilmont	77:869cf507173a	641	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
emilmont	77:869cf507173a	642	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
emilmont	77:869cf507173a	643	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
emilmont	77:869cf507173a	644	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
emilmont	77:869cf507173a	645	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
emilmont	77:869cf507173a	646	* @retval None
emilmont	77:869cf507173a	647	*/
emilmont	77:869cf507173a	648	#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
emilmont	77:869cf507173a	649
emilmont	77:869cf507173a	650	/**
emilmont	77:869cf507173a	651	* @brief Disable the SDIO device interrupt.
emilmont	77:869cf507173a	652	* @param __INSTANCE__ : Pointer to SDIO register base
emilmont	77:869cf507173a	653	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
emilmont	77:869cf507173a	654	* This parameter can be one or a combination of the following values:
emilmont	77:869cf507173a	655	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
emilmont	77:869cf507173a	656	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
emilmont	77:869cf507173a	657	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
emilmont	77:869cf507173a	658	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
emilmont	77:869cf507173a	659	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
emilmont	77:869cf507173a	660	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
emilmont	77:869cf507173a	661	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
emilmont	77:869cf507173a	662	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
emilmont	77:869cf507173a	663	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
emilmont	77:869cf507173a	664	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
emilmont	77:869cf507173a	665	* bus mode interrupt
emilmont	77:869cf507173a	666	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
emilmont	77:869cf507173a	667	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
emilmont	77:869cf507173a	668	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
emilmont	77:869cf507173a	669	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
emilmont	77:869cf507173a	670	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
emilmont	77:869cf507173a	671	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
emilmont	77:869cf507173a	672	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
emilmont	77:869cf507173a	673	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
emilmont	77:869cf507173a	674	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
emilmont	77:869cf507173a	675	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
emilmont	77:869cf507173a	676	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
emilmont	77:869cf507173a	677	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
emilmont	77:869cf507173a	678	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
emilmont	77:869cf507173a	679	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
emilmont	77:869cf507173a	680	* @retval None
emilmont	77:869cf507173a	681	*/
emilmont	77:869cf507173a	682	#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	683
emilmont	77:869cf507173a	684	/**
emilmont	77:869cf507173a	685	* @brief Checks whether the specified SDIO flag is set or not.
emilmont	77:869cf507173a	686	* @param __INSTANCE__ : Pointer to SDIO register base
emilmont	77:869cf507173a	687	* @param __FLAG__: specifies the flag to check.
emilmont	77:869cf507173a	688	* This parameter can be one of the following values:
emilmont	77:869cf507173a	689	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
emilmont	77:869cf507173a	690	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
emilmont	77:869cf507173a	691	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
emilmont	77:869cf507173a	692	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
emilmont	77:869cf507173a	693	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
emilmont	77:869cf507173a	694	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
emilmont	77:869cf507173a	695	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
emilmont	77:869cf507173a	696	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
emilmont	77:869cf507173a	697	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
emilmont	77:869cf507173a	698	* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
emilmont	77:869cf507173a	699	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
emilmont	77:869cf507173a	700	* @arg SDIO_FLAG_CMDACT: Command transfer in progress
emilmont	77:869cf507173a	701	* @arg SDIO_FLAG_TXACT: Data transmit in progress
emilmont	77:869cf507173a	702	* @arg SDIO_FLAG_RXACT: Data receive in progress
emilmont	77:869cf507173a	703	* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
emilmont	77:869cf507173a	704	* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
emilmont	77:869cf507173a	705	* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
emilmont	77:869cf507173a	706	* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
emilmont	77:869cf507173a	707	* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
emilmont	77:869cf507173a	708	* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
emilmont	77:869cf507173a	709	* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
emilmont	77:869cf507173a	710	* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
emilmont	77:869cf507173a	711	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
emilmont	77:869cf507173a	712	* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
emilmont	77:869cf507173a	713	* @retval The new state of SDIO_FLAG (SET or RESET).
emilmont	77:869cf507173a	714	*/
emilmont	77:869cf507173a	715	#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
emilmont	77:869cf507173a	716
emilmont	77:869cf507173a	717
emilmont	77:869cf507173a	718	/**
emilmont	77:869cf507173a	719	* @brief Clears the SDIO's pending flags.
emilmont	77:869cf507173a	720	* @param __INSTANCE__ : Pointer to SDIO register base
emilmont	77:869cf507173a	721	* @param __FLAG__: specifies the flag to clear.
emilmont	77:869cf507173a	722	* This parameter can be one or a combination of the following values:
emilmont	77:869cf507173a	723	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
emilmont	77:869cf507173a	724	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
emilmont	77:869cf507173a	725	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
emilmont	77:869cf507173a	726	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
emilmont	77:869cf507173a	727	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
emilmont	77:869cf507173a	728	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
emilmont	77:869cf507173a	729	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
emilmont	77:869cf507173a	730	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
emilmont	77:869cf507173a	731	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
emilmont	77:869cf507173a	732	* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
emilmont	77:869cf507173a	733	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
emilmont	77:869cf507173a	734	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
emilmont	77:869cf507173a	735	* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
emilmont	77:869cf507173a	736	* @retval None
emilmont	77:869cf507173a	737	*/
emilmont	77:869cf507173a	738	#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
emilmont	77:869cf507173a	739
emilmont	77:869cf507173a	740	/**
emilmont	77:869cf507173a	741	* @brief Checks whether the specified SDIO interrupt has occurred or not.
emilmont	77:869cf507173a	742	* @param __INSTANCE__ : Pointer to SDIO register base
emilmont	77:869cf507173a	743	* @param __INTERRUPT__: specifies the SDIO interrupt source to check.
emilmont	77:869cf507173a	744	* This parameter can be one of the following values:
emilmont	77:869cf507173a	745	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
emilmont	77:869cf507173a	746	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
emilmont	77:869cf507173a	747	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
emilmont	77:869cf507173a	748	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
emilmont	77:869cf507173a	749	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
emilmont	77:869cf507173a	750	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
emilmont	77:869cf507173a	751	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
emilmont	77:869cf507173a	752	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
emilmont	77:869cf507173a	753	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
emilmont	77:869cf507173a	754	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
emilmont	77:869cf507173a	755	* bus mode interrupt
emilmont	77:869cf507173a	756	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
emilmont	77:869cf507173a	757	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
emilmont	77:869cf507173a	758	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
emilmont	77:869cf507173a	759	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
emilmont	77:869cf507173a	760	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
emilmont	77:869cf507173a	761	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
emilmont	77:869cf507173a	762	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
emilmont	77:869cf507173a	763	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
emilmont	77:869cf507173a	764	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
emilmont	77:869cf507173a	765	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
emilmont	77:869cf507173a	766	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
emilmont	77:869cf507173a	767	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
emilmont	77:869cf507173a	768	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
emilmont	77:869cf507173a	769	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
emilmont	77:869cf507173a	770	* @retval The new state of SDIO_IT (SET or RESET).
emilmont	77:869cf507173a	771	*/
emilmont	77:869cf507173a	772	#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
emilmont	77:869cf507173a	773
emilmont	77:869cf507173a	774	/**
emilmont	77:869cf507173a	775	* @brief Clears the SDIO's interrupt pending bits.
emilmont	77:869cf507173a	776	* @param __INSTANCE__ : Pointer to SDIO register base
emilmont	77:869cf507173a	777	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
emilmont	77:869cf507173a	778	* This parameter can be one or a combination of the following values:
emilmont	77:869cf507173a	779	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
emilmont	77:869cf507173a	780	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
emilmont	77:869cf507173a	781	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
emilmont	77:869cf507173a	782	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
emilmont	77:869cf507173a	783	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
emilmont	77:869cf507173a	784	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
emilmont	77:869cf507173a	785	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
emilmont	77:869cf507173a	786	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
emilmont	77:869cf507173a	787	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
emilmont	77:869cf507173a	788	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
emilmont	77:869cf507173a	789	* bus mode interrupt
emilmont	77:869cf507173a	790	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
emilmont	77:869cf507173a	791	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
emilmont	77:869cf507173a	792	* @retval None
emilmont	77:869cf507173a	793	*/
emilmont	77:869cf507173a	794	#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
emilmont	77:869cf507173a	795
emilmont	77:869cf507173a	796	/**
emilmont	77:869cf507173a	797	* @brief Enable Start the SD I/O Read Wait operation.
emilmont	77:869cf507173a	798	* @param None
emilmont	77:869cf507173a	799	* @retval None
emilmont	77:869cf507173a	800	*/
emilmont	77:869cf507173a	801	#define __SDIO_START_READWAIT_ENABLE() ((__IO uint32_t ) DCTRL_RWSTART_BB = ENABLE)
emilmont	77:869cf507173a	802
emilmont	77:869cf507173a	803	/**
emilmont	77:869cf507173a	804	* @brief Disable Start the SD I/O Read Wait operations.
emilmont	77:869cf507173a	805	* @param None
emilmont	77:869cf507173a	806	* @retval None
emilmont	77:869cf507173a	807	*/
emilmont	77:869cf507173a	808	#define __SDIO_START_READWAIT_DISABLE() ((__IO uint32_t ) DCTRL_RWSTART_BB = DISABLE)
emilmont	77:869cf507173a	809
emilmont	77:869cf507173a	810	/**
emilmont	77:869cf507173a	811	* @brief Enable Start the SD I/O Read Wait operation.
emilmont	77:869cf507173a	812	* @param None
emilmont	77:869cf507173a	813	* @retval None
emilmont	77:869cf507173a	814	*/
emilmont	77:869cf507173a	815	#define __SDIO_STOP_READWAIT_ENABLE() ((__IO uint32_t ) DCTRL_RWSTOP_BB = ENABLE)
emilmont	77:869cf507173a	816
emilmont	77:869cf507173a	817	/**
emilmont	77:869cf507173a	818	* @brief Disable Stop the SD I/O Read Wait operations.
emilmont	77:869cf507173a	819	* @param None
emilmont	77:869cf507173a	820	* @retval None
emilmont	77:869cf507173a	821	*/
emilmont	77:869cf507173a	822	#define __SDIO_STOP_READWAIT_DISABLE() ((__IO uint32_t ) DCTRL_RWSTOP_BB = DISABLE)
emilmont	77:869cf507173a	823
emilmont	77:869cf507173a	824	/**
emilmont	77:869cf507173a	825	* @brief Enable the SD I/O Mode Operation.
emilmont	77:869cf507173a	826	* @param None
emilmont	77:869cf507173a	827	* @retval None
emilmont	77:869cf507173a	828	*/
emilmont	77:869cf507173a	829	#define __SDIO_OPERATION_ENABLE() ((__IO uint32_t ) DCTRL_SDIOEN_BB = ENABLE)
emilmont	77:869cf507173a	830
emilmont	77:869cf507173a	831	/**
emilmont	77:869cf507173a	832	* @brief Disable the SD I/O Mode Operation.
emilmont	77:869cf507173a	833	* @param None
emilmont	77:869cf507173a	834	* @retval None
emilmont	77:869cf507173a	835	*/
emilmont	77:869cf507173a	836	#define __SDIO_OPERATION_DISABLE() ((__IO uint32_t ) DCTRL_SDIOEN_BB = DISABLE)
emilmont	77:869cf507173a	837
emilmont	77:869cf507173a	838	/**
emilmont	77:869cf507173a	839	* @brief Enable the SD I/O Suspend command sending.
emilmont	77:869cf507173a	840	* @param None
emilmont	77:869cf507173a	841	* @retval None
emilmont	77:869cf507173a	842	*/
emilmont	77:869cf507173a	843	#define __SDIO_SUSPEND_CMD_ENABLE() ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = ENABLE)
emilmont	77:869cf507173a	844
emilmont	77:869cf507173a	845	/**
emilmont	77:869cf507173a	846	* @brief Disable the SD I/O Suspend command sending.
emilmont	77:869cf507173a	847	* @param None
emilmont	77:869cf507173a	848	* @retval None
emilmont	77:869cf507173a	849	*/
emilmont	77:869cf507173a	850	#define __SDIO_SUSPEND_CMD_DISABLE() ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = DISABLE)
emilmont	77:869cf507173a	851
emilmont	77:869cf507173a	852	/**
emilmont	77:869cf507173a	853	* @brief Enable the command completion signal.
emilmont	77:869cf507173a	854	* @param None
emilmont	77:869cf507173a	855	* @retval None
emilmont	77:869cf507173a	856	*/
emilmont	77:869cf507173a	857	#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = ENABLE)
emilmont	77:869cf507173a	858
emilmont	77:869cf507173a	859	/**
emilmont	77:869cf507173a	860	* @brief Disable the command completion signal.
emilmont	77:869cf507173a	861	* @param None
emilmont	77:869cf507173a	862	* @retval None
emilmont	77:869cf507173a	863	*/
emilmont	77:869cf507173a	864	#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = DISABLE)
emilmont	77:869cf507173a	865
emilmont	77:869cf507173a	866	/**
emilmont	77:869cf507173a	867	* @brief Enable the CE-ATA interrupt.
emilmont	77:869cf507173a	868	* @param None
emilmont	77:869cf507173a	869	* @retval None
emilmont	77:869cf507173a	870	*/
emilmont	77:869cf507173a	871	#define __SDIO_CEATA_ENABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)0)
emilmont	77:869cf507173a	872
emilmont	77:869cf507173a	873	/**
emilmont	77:869cf507173a	874	* @brief Disable the CE-ATA interrupt.
emilmont	77:869cf507173a	875	* @param None
emilmont	77:869cf507173a	876	* @retval None
emilmont	77:869cf507173a	877	*/
emilmont	77:869cf507173a	878	#define __SDIO_CEATA_DISABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)1)
emilmont	77:869cf507173a	879
emilmont	77:869cf507173a	880	/**
emilmont	77:869cf507173a	881	* @brief Enable send CE-ATA command (CMD61).
emilmont	77:869cf507173a	882	* @param None
emilmont	77:869cf507173a	883	* @retval None
emilmont	77:869cf507173a	884	*/
emilmont	77:869cf507173a	885	#define __SDIO_CEATA_SENDCMD_ENABLE() ((__IO uint32_t ) CMD_ATACMD_BB = ENABLE)
emilmont	77:869cf507173a	886
emilmont	77:869cf507173a	887	/**
emilmont	77:869cf507173a	888	* @brief Disable send CE-ATA command (CMD61).
emilmont	77:869cf507173a	889	* @param None
emilmont	77:869cf507173a	890	* @retval None
emilmont	77:869cf507173a	891	*/
emilmont	77:869cf507173a	892	#define __SDIO_CEATA_SENDCMD_DISABLE() ((__IO uint32_t ) CMD_ATACMD_BB = DISABLE)
emilmont	77:869cf507173a	893
emilmont	77:869cf507173a	894	/**
emilmont	77:869cf507173a	895	* @}
emilmont	77:869cf507173a	896	*/
emilmont	77:869cf507173a	897
emilmont	77:869cf507173a	898	/* Exported functions --------------------------------------------------------*/
emilmont	77:869cf507173a	899
emilmont	77:869cf507173a	900	/* Initialization/de-initialization functions **********************************/
emilmont	77:869cf507173a	901	HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
emilmont	77:869cf507173a	902
emilmont	77:869cf507173a	903	/* I/O operation functions *****************************************************/
emilmont	77:869cf507173a	904	/* Blocking mode: Polling */
emilmont	77:869cf507173a	905	uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
emilmont	77:869cf507173a	906	HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef SDIOx, uint32_t pWriteData);
emilmont	77:869cf507173a	907
emilmont	77:869cf507173a	908	/* Peripheral Control functions ************************************************/
emilmont	77:869cf507173a	909	HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
emilmont	77:869cf507173a	910	HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
emilmont	77:869cf507173a	911	uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
emilmont	77:869cf507173a	912
emilmont	77:869cf507173a	913	/* Command path state machine (CPSM) management functions */
emilmont	77:869cf507173a	914	HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef SDIOx, SDIO_CmdInitTypeDef SDIO_CmdInitStruct);
emilmont	77:869cf507173a	915	uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
emilmont	77:869cf507173a	916	uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
emilmont	77:869cf507173a	917
emilmont	77:869cf507173a	918	/* Data path state machine (DPSM) management functions */
emilmont	77:869cf507173a	919	HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef SDIOx, SDIO_DataInitTypeDef SDIO_DataInitStruct);
emilmont	77:869cf507173a	920	uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
emilmont	77:869cf507173a	921	uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
emilmont	77:869cf507173a	922
emilmont	77:869cf507173a	923	/* SDIO IO Cards mode management functions */
emilmont	77:869cf507173a	924	HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
emilmont	77:869cf507173a	925
emilmont	77:869cf507173a	926	#ifdef __cplusplus
emilmont	77:869cf507173a	927	}
emilmont	77:869cf507173a	928	#endif
emilmont	77:869cf507173a	929
emilmont	77:869cf507173a	930	#endif /* __STM32F4xx_LL_SDMMC_H */
emilmont	77:869cf507173a	931
emilmont	77:869cf507173a	932	/**
emilmont	77:869cf507173a	933	* @}
emilmont	77:869cf507173a	934	*/
emilmont	77:869cf507173a	935
emilmont	77:869cf507173a	936	/**
emilmont	77:869cf507173a	937	* @}
emilmont	77:869cf507173a	938	*/
emilmont	77:869cf507173a	939
emilmont	77:869cf507173a	940	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/