mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F401RE/stm32f4xx_ll_fsmc.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: 85:024bf7f99721
Child:: 90:cb3d968589d8

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_ll_fsmc.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
bogdanm	85:024bf7f99721	5	* @version V1.1.0RC2
bogdanm	85:024bf7f99721	6	* @date 14-May-2014
emilmont	77:869cf507173a	7	* @brief Header file of FSMC HAL module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
emilmont	77:869cf507173a	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_LL_FSMC_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_LL_FSMC_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
emilmont	77:869cf507173a	47
emilmont	77:869cf507173a	48	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	49	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	50
emilmont	77:869cf507173a	51	/** @addtogroup STM32F4xx_HAL_Driver
emilmont	77:869cf507173a	52	* @{
emilmont	77:869cf507173a	53	*/
emilmont	77:869cf507173a	54
emilmont	77:869cf507173a	55	/** @addtogroup FSMC
emilmont	77:869cf507173a	56	* @{
emilmont	77:869cf507173a	57	*/
emilmont	77:869cf507173a	58
emilmont	77:869cf507173a	59	/* Exported typedef ----------------------------------------------------------*/
emilmont	77:869cf507173a	60	#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
emilmont	77:869cf507173a	61	#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
emilmont	77:869cf507173a	62	#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
emilmont	77:869cf507173a	63	#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
emilmont	77:869cf507173a	64
bogdanm	85:024bf7f99721	65	#define FSMC_NORSRAM_DEVICE FSMC_Bank1
bogdanm	85:024bf7f99721	66	#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
bogdanm	85:024bf7f99721	67	#define FSMC_NAND_DEVICE FSMC_Bank2_3
bogdanm	85:024bf7f99721	68	#define FSMC_PCCARD_DEVICE FSMC_Bank4
emilmont	77:869cf507173a	69
emilmont	77:869cf507173a	70	/**
bogdanm	85:024bf7f99721	71	* @brief FSMC_NORSRAM Configuration Structure definition
emilmont	77:869cf507173a	72	*/
emilmont	77:869cf507173a	73	typedef struct
emilmont	77:869cf507173a	74	{
emilmont	77:869cf507173a	75	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm	85:024bf7f99721	76	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
bogdanm	85:024bf7f99721	77
emilmont	77:869cf507173a	78	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
emilmont	77:869cf507173a	79	multiplexed on the data bus or not.
emilmont	77:869cf507173a	80	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
bogdanm	85:024bf7f99721	81
emilmont	77:869cf507173a	82	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
emilmont	77:869cf507173a	83	the corresponding memory device.
emilmont	77:869cf507173a	84	This parameter can be a value of @ref FSMC_Memory_Type */
bogdanm	85:024bf7f99721	85
emilmont	77:869cf507173a	86	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
emilmont	77:869cf507173a	87	This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
bogdanm	85:024bf7f99721	88
emilmont	77:869cf507173a	89	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
emilmont	77:869cf507173a	90	valid only with synchronous burst Flash memories.
emilmont	77:869cf507173a	91	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
bogdanm	85:024bf7f99721	92
emilmont	77:869cf507173a	93	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
emilmont	77:869cf507173a	94	the Flash memory in burst mode.
emilmont	77:869cf507173a	95	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
bogdanm	85:024bf7f99721	96
emilmont	77:869cf507173a	97	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
emilmont	77:869cf507173a	98	memory, valid only when accessing Flash memories in burst mode.
emilmont	77:869cf507173a	99	This parameter can be a value of @ref FSMC_Wrap_Mode */
bogdanm	85:024bf7f99721	100
emilmont	77:869cf507173a	101	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
emilmont	77:869cf507173a	102	clock cycle before the wait state or during the wait state,
emilmont	77:869cf507173a	103	valid only when accessing memories in burst mode.
emilmont	77:869cf507173a	104	This parameter can be a value of @ref FSMC_Wait_Timing */
bogdanm	85:024bf7f99721	105
emilmont	77:869cf507173a	106	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
emilmont	77:869cf507173a	107	This parameter can be a value of @ref FSMC_Write_Operation */
bogdanm	85:024bf7f99721	108
emilmont	77:869cf507173a	109	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
emilmont	77:869cf507173a	110	signal, valid for Flash memory access in burst mode.
emilmont	77:869cf507173a	111	This parameter can be a value of @ref FSMC_Wait_Signal */
bogdanm	85:024bf7f99721	112
emilmont	77:869cf507173a	113	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
emilmont	77:869cf507173a	114	This parameter can be a value of @ref FSMC_Extended_Mode */
bogdanm	85:024bf7f99721	115
emilmont	77:869cf507173a	116	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
emilmont	77:869cf507173a	117	valid only with asynchronous Flash memories.
emilmont	77:869cf507173a	118	This parameter can be a value of @ref FSMC_AsynchronousWait */
bogdanm	85:024bf7f99721	119
emilmont	77:869cf507173a	120	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm	85:024bf7f99721	121	This parameter can be a value of @ref FSMC_Write_Burst */
emilmont	77:869cf507173a	122
emilmont	77:869cf507173a	123	}FSMC_NORSRAM_InitTypeDef;
emilmont	77:869cf507173a	124
emilmont	77:869cf507173a	125	/**
bogdanm	85:024bf7f99721	126	* @brief FSMC_NORSRAM Timing parameters structure definition
emilmont	77:869cf507173a	127	*/
emilmont	77:869cf507173a	128	typedef struct
emilmont	77:869cf507173a	129	{
emilmont	77:869cf507173a	130	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	131	the duration of the address setup time.
emilmont	77:869cf507173a	132	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
emilmont	77:869cf507173a	133	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	85:024bf7f99721	134
emilmont	77:869cf507173a	135	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	136	the duration of the address hold time.
emilmont	77:869cf507173a	137	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
emilmont	77:869cf507173a	138	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	85:024bf7f99721	139
emilmont	77:869cf507173a	140	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	141	the duration of the data setup time.
emilmont	77:869cf507173a	142	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
emilmont	77:869cf507173a	143	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
emilmont	77:869cf507173a	144	NOR Flash memories. */
bogdanm	85:024bf7f99721	145
emilmont	77:869cf507173a	146	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	147	the duration of the bus turnaround.
emilmont	77:869cf507173a	148	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
emilmont	77:869cf507173a	149	@note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm	85:024bf7f99721	150
emilmont	77:869cf507173a	151	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
emilmont	77:869cf507173a	152	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
emilmont	77:869cf507173a	153	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
emilmont	77:869cf507173a	154	accesses. */
bogdanm	85:024bf7f99721	155
emilmont	77:869cf507173a	156	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
emilmont	77:869cf507173a	157	to the memory before getting the first data.
emilmont	77:869cf507173a	158	The parameter value depends on the memory type as shown below:
emilmont	77:869cf507173a	159	- It must be set to 0 in case of a CRAM
emilmont	77:869cf507173a	160	- It is don't care in asynchronous NOR, SRAM or ROM accesses
emilmont	77:869cf507173a	161	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
emilmont	77:869cf507173a	162	with synchronous burst mode enable */
bogdanm	85:024bf7f99721	163
emilmont	77:869cf507173a	164	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
emilmont	77:869cf507173a	165	This parameter can be a value of @ref FSMC_Access_Mode */
bogdanm	85:024bf7f99721	166
emilmont	77:869cf507173a	167	}FSMC_NORSRAM_TimingTypeDef;
emilmont	77:869cf507173a	168
emilmont	77:869cf507173a	169	/**
bogdanm	85:024bf7f99721	170	* @brief FSMC_NAND Configuration Structure definition
emilmont	77:869cf507173a	171	*/
emilmont	77:869cf507173a	172	typedef struct
emilmont	77:869cf507173a	173	{
emilmont	77:869cf507173a	174	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm	85:024bf7f99721	175	This parameter can be a value of @ref FSMC_NAND_Bank */
bogdanm	85:024bf7f99721	176
emilmont	77:869cf507173a	177	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
emilmont	77:869cf507173a	178	This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm	85:024bf7f99721	179
emilmont	77:869cf507173a	180	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
emilmont	77:869cf507173a	181	This parameter can be any value of @ref FSMC_NAND_Data_Width */
bogdanm	85:024bf7f99721	182
emilmont	77:869cf507173a	183	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
emilmont	77:869cf507173a	184	This parameter can be any value of @ref FSMC_ECC */
bogdanm	85:024bf7f99721	185
emilmont	77:869cf507173a	186	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
emilmont	77:869cf507173a	187	This parameter can be any value of @ref FSMC_ECC_Page_Size */
bogdanm	85:024bf7f99721	188
emilmont	77:869cf507173a	189	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	190	delay between CLE low and RE low.
emilmont	77:869cf507173a	191	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	192
emilmont	77:869cf507173a	193	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	194	delay between ALE low and RE low.
emilmont	77:869cf507173a	195	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	196
emilmont	77:869cf507173a	197	}FSMC_NAND_InitTypeDef;
emilmont	77:869cf507173a	198
emilmont	77:869cf507173a	199	/**
emilmont	77:869cf507173a	200	* @brief FSMC_NAND_PCCARD Timing parameters structure definition
emilmont	77:869cf507173a	201	*/
emilmont	77:869cf507173a	202	typedef struct
emilmont	77:869cf507173a	203	{
emilmont	77:869cf507173a	204	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
emilmont	77:869cf507173a	205	the command assertion for NAND-Flash read or write access
emilmont	77:869cf507173a	206	to common/Attribute or I/O memory space (depending on
emilmont	77:869cf507173a	207	the memory space timing to be configured).
emilmont	77:869cf507173a	208	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	209
emilmont	77:869cf507173a	210	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
emilmont	77:869cf507173a	211	command for NAND-Flash read or write access to
emilmont	77:869cf507173a	212	common/Attribute or I/O memory space (depending on the
emilmont	77:869cf507173a	213	memory space timing to be configured).
emilmont	77:869cf507173a	214	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	215
emilmont	77:869cf507173a	216	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
emilmont	77:869cf507173a	217	(and data for write access) after the command de-assertion
emilmont	77:869cf507173a	218	for NAND-Flash read or write access to common/Attribute
emilmont	77:869cf507173a	219	or I/O memory space (depending on the memory space timing
emilmont	77:869cf507173a	220	to be configured).
emilmont	77:869cf507173a	221	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	222
emilmont	77:869cf507173a	223	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
emilmont	77:869cf507173a	224	data bus is kept in HiZ after the start of a NAND-Flash
emilmont	77:869cf507173a	225	write access to common/Attribute or I/O memory space (depending
emilmont	77:869cf507173a	226	on the memory space timing to be configured).
emilmont	77:869cf507173a	227	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	228
emilmont	77:869cf507173a	229	}FSMC_NAND_PCC_TimingTypeDef;
emilmont	77:869cf507173a	230
emilmont	77:869cf507173a	231	/**
bogdanm	85:024bf7f99721	232	* @brief FSMC_NAND Configuration Structure definition
bogdanm	85:024bf7f99721	233	*/
emilmont	77:869cf507173a	234	typedef struct
emilmont	77:869cf507173a	235	{
emilmont	77:869cf507173a	236	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
emilmont	77:869cf507173a	237	This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm	85:024bf7f99721	238
emilmont	77:869cf507173a	239	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	240	delay between CLE low and RE low.
emilmont	77:869cf507173a	241	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	242
emilmont	77:869cf507173a	243	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	244	delay between ALE low and RE low.
emilmont	77:869cf507173a	245	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	246
bogdanm	85:024bf7f99721	247	}FSMC_PCCARD_InitTypeDef;
emilmont	77:869cf507173a	248
emilmont	77:869cf507173a	249	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	250
emilmont	77:869cf507173a	251	/** @defgroup FSMC_NOR_SRAM_Controller
emilmont	77:869cf507173a	252	* @{
emilmont	77:869cf507173a	253	*/
emilmont	77:869cf507173a	254
emilmont	77:869cf507173a	255	/** @defgroup FSMC_NORSRAM_Bank
emilmont	77:869cf507173a	256	* @{
emilmont	77:869cf507173a	257	*/
emilmont	77:869cf507173a	258	#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	259	#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	260	#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	261	#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
emilmont	77:869cf507173a	262
emilmont	77:869cf507173a	263	#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_NORSRAM_BANK1) \|\| \
emilmont	77:869cf507173a	264	((BANK) == FSMC_NORSRAM_BANK2) \|\| \
emilmont	77:869cf507173a	265	((BANK) == FSMC_NORSRAM_BANK3) \|\| \
emilmont	77:869cf507173a	266	((BANK) == FSMC_NORSRAM_BANK4))
emilmont	77:869cf507173a	267	/**
emilmont	77:869cf507173a	268	* @}
emilmont	77:869cf507173a	269	*/
emilmont	77:869cf507173a	270
emilmont	77:869cf507173a	271	/** @defgroup FSMC_Data_Address_Bus_Multiplexing
emilmont	77:869cf507173a	272	* @{
emilmont	77:869cf507173a	273	*/
emilmont	77:869cf507173a	274
emilmont	77:869cf507173a	275	#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	276	#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
emilmont	77:869cf507173a	277
emilmont	77:869cf507173a	278	#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
emilmont	77:869cf507173a	279	((MUX) == FSMC_DATA_ADDRESS_MUX_ENABLE))
emilmont	77:869cf507173a	280	/**
emilmont	77:869cf507173a	281	* @}
emilmont	77:869cf507173a	282	*/
emilmont	77:869cf507173a	283
emilmont	77:869cf507173a	284	/** @defgroup FSMC_Memory_Type
emilmont	77:869cf507173a	285	* @{
emilmont	77:869cf507173a	286	*/
emilmont	77:869cf507173a	287
emilmont	77:869cf507173a	288	#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
emilmont	77:869cf507173a	289	#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
emilmont	77:869cf507173a	290	#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
emilmont	77:869cf507173a	291
emilmont	77:869cf507173a	292
emilmont	77:869cf507173a	293	#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MEMORY_TYPE_SRAM) \|\| \
emilmont	77:869cf507173a	294	((MEMORY) == FSMC_MEMORY_TYPE_PSRAM)\|\| \
emilmont	77:869cf507173a	295	((MEMORY) == FSMC_MEMORY_TYPE_NOR))
emilmont	77:869cf507173a	296	/**
emilmont	77:869cf507173a	297	* @}
emilmont	77:869cf507173a	298	*/
emilmont	77:869cf507173a	299
emilmont	77:869cf507173a	300	/** @defgroup FSMC_NORSRAM_Data_Width
emilmont	77:869cf507173a	301	* @{
emilmont	77:869cf507173a	302	*/
emilmont	77:869cf507173a	303
emilmont	77:869cf507173a	304	#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	305	#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	306	#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	307
emilmont	77:869cf507173a	308	#define IS_FSMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
emilmont	77:869cf507173a	309	((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
emilmont	77:869cf507173a	310	((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
emilmont	77:869cf507173a	311	/**
emilmont	77:869cf507173a	312	* @}
emilmont	77:869cf507173a	313	*/
emilmont	77:869cf507173a	314
emilmont	77:869cf507173a	315	/** @defgroup FSMC_NORSRAM_Flash_Access
emilmont	77:869cf507173a	316	* @{
emilmont	77:869cf507173a	317	*/
emilmont	77:869cf507173a	318	#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
emilmont	77:869cf507173a	319	#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	320	/**
emilmont	77:869cf507173a	321	* @}
emilmont	77:869cf507173a	322	*/
emilmont	77:869cf507173a	323
emilmont	77:869cf507173a	324	/** @defgroup FSMC_Burst_Access_Mode
emilmont	77:869cf507173a	325	* @{
emilmont	77:869cf507173a	326	*/
emilmont	77:869cf507173a	327
emilmont	77:869cf507173a	328	#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	329	#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
emilmont	77:869cf507173a	330
emilmont	77:869cf507173a	331	#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BURST_ACCESS_MODE_DISABLE) \|\| \
emilmont	77:869cf507173a	332	((STATE) == FSMC_BURST_ACCESS_MODE_ENABLE))
emilmont	77:869cf507173a	333	/**
emilmont	77:869cf507173a	334	* @}
emilmont	77:869cf507173a	335	*/
emilmont	77:869cf507173a	336
emilmont	77:869cf507173a	337
emilmont	77:869cf507173a	338	/** @defgroup FSMC_Wait_Signal_Polarity
emilmont	77:869cf507173a	339	* @{
emilmont	77:869cf507173a	340	*/
emilmont	77:869cf507173a	341	#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
emilmont	77:869cf507173a	342	#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
emilmont	77:869cf507173a	343
emilmont	77:869cf507173a	344	#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
emilmont	77:869cf507173a	345	((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
emilmont	77:869cf507173a	346	/**
emilmont	77:869cf507173a	347	* @}
emilmont	77:869cf507173a	348	*/
emilmont	77:869cf507173a	349
emilmont	77:869cf507173a	350	/** @defgroup FSMC_Wrap_Mode
emilmont	77:869cf507173a	351	* @{
emilmont	77:869cf507173a	352	*/
emilmont	77:869cf507173a	353	#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	354	#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
emilmont	77:869cf507173a	355
emilmont	77:869cf507173a	356	#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WRAP_MODE_DISABLE) \|\| \
emilmont	77:869cf507173a	357	((MODE) == FSMC_WRAP_MODE_ENABLE))
emilmont	77:869cf507173a	358	/**
emilmont	77:869cf507173a	359	* @}
emilmont	77:869cf507173a	360	*/
emilmont	77:869cf507173a	361
emilmont	77:869cf507173a	362	/** @defgroup FSMC_Wait_Timing
emilmont	77:869cf507173a	363	* @{
emilmont	77:869cf507173a	364	*/
emilmont	77:869cf507173a	365	#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
emilmont	77:869cf507173a	366	#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
emilmont	77:869cf507173a	367
emilmont	77:869cf507173a	368	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WAIT_TIMING_BEFORE_WS) \|\| \
emilmont	77:869cf507173a	369	((ACTIVE) == FSMC_WAIT_TIMING_DURING_WS))
emilmont	77:869cf507173a	370	/**
emilmont	77:869cf507173a	371	* @}
emilmont	77:869cf507173a	372	*/
emilmont	77:869cf507173a	373
emilmont	77:869cf507173a	374	/** @defgroup FSMC_Write_Operation
emilmont	77:869cf507173a	375	* @{
emilmont	77:869cf507173a	376	*/
emilmont	77:869cf507173a	377	#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	378	#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
emilmont	77:869cf507173a	379
emilmont	77:869cf507173a	380	#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) \|\| \
bogdanm	85:024bf7f99721	381	((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
emilmont	77:869cf507173a	382	/**
emilmont	77:869cf507173a	383	* @}
emilmont	77:869cf507173a	384	*/
emilmont	77:869cf507173a	385
emilmont	77:869cf507173a	386	/** @defgroup FSMC_Wait_Signal
emilmont	77:869cf507173a	387	* @{
emilmont	77:869cf507173a	388	*/
emilmont	77:869cf507173a	389	#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	390	#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
emilmont	77:869cf507173a	391
emilmont	77:869cf507173a	392	#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WAIT_SIGNAL_DISABLE) \|\| \
emilmont	77:869cf507173a	393	((SIGNAL) == FSMC_WAIT_SIGNAL_ENABLE))
emilmont	77:869cf507173a	394
emilmont	77:869cf507173a	395	/**
emilmont	77:869cf507173a	396	* @}
emilmont	77:869cf507173a	397	*/
emilmont	77:869cf507173a	398
emilmont	77:869cf507173a	399	/** @defgroup FSMC_Extended_Mode
emilmont	77:869cf507173a	400	* @{
emilmont	77:869cf507173a	401	*/
emilmont	77:869cf507173a	402	#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	403	#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
emilmont	77:869cf507173a	404
emilmont	77:869cf507173a	405	#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_EXTENDED_MODE_DISABLE) \|\| \
emilmont	77:869cf507173a	406	((MODE) == FSMC_EXTENDED_MODE_ENABLE))
emilmont	77:869cf507173a	407	/**
emilmont	77:869cf507173a	408	* @}
emilmont	77:869cf507173a	409	*/
emilmont	77:869cf507173a	410
emilmont	77:869cf507173a	411	/** @defgroup FSMC_AsynchronousWait
emilmont	77:869cf507173a	412	* @{
emilmont	77:869cf507173a	413	*/
emilmont	77:869cf507173a	414	#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	415	#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
emilmont	77:869cf507173a	416
emilmont	77:869cf507173a	417	#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
emilmont	77:869cf507173a	418	((STATE) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
emilmont	77:869cf507173a	419
emilmont	77:869cf507173a	420	/**
emilmont	77:869cf507173a	421	* @}
emilmont	77:869cf507173a	422	*/
emilmont	77:869cf507173a	423
emilmont	77:869cf507173a	424	/** @defgroup FSMC_Write_Burst
emilmont	77:869cf507173a	425	* @{
emilmont	77:869cf507173a	426	*/
emilmont	77:869cf507173a	427
emilmont	77:869cf507173a	428	#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	429	#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
emilmont	77:869cf507173a	430
emilmont	77:869cf507173a	431	#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WRITE_BURST_DISABLE) \|\| \
emilmont	77:869cf507173a	432	((BURST) == FSMC_WRITE_BURST_ENABLE))
emilmont	77:869cf507173a	433
emilmont	77:869cf507173a	434	/**
emilmont	77:869cf507173a	435	* @}
emilmont	77:869cf507173a	436	*/
emilmont	77:869cf507173a	437
emilmont	77:869cf507173a	438	/** @defgroup FSMC_Continous_Clock
emilmont	77:869cf507173a	439	* @{
emilmont	77:869cf507173a	440	*/
emilmont	77:869cf507173a	441
emilmont	77:869cf507173a	442	#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
emilmont	77:869cf507173a	443	#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
emilmont	77:869cf507173a	444
emilmont	77:869cf507173a	445	#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
emilmont	77:869cf507173a	446	((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
emilmont	77:869cf507173a	447
emilmont	77:869cf507173a	448	/**
emilmont	77:869cf507173a	449	* @}
emilmont	77:869cf507173a	450	*/
emilmont	77:869cf507173a	451
emilmont	77:869cf507173a	452	/** @defgroup FSMC_Address_Setup_Time
emilmont	77:869cf507173a	453	* @{
emilmont	77:869cf507173a	454	*/
emilmont	77:869cf507173a	455	#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
emilmont	77:869cf507173a	456	/**
emilmont	77:869cf507173a	457	* @}
emilmont	77:869cf507173a	458	*/
emilmont	77:869cf507173a	459
emilmont	77:869cf507173a	460	/** @defgroup FSMC_Address_Hold_Time
emilmont	77:869cf507173a	461	* @{
emilmont	77:869cf507173a	462	*/
emilmont	77:869cf507173a	463	#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
emilmont	77:869cf507173a	464	/**
emilmont	77:869cf507173a	465	* @}
emilmont	77:869cf507173a	466	*/
emilmont	77:869cf507173a	467
emilmont	77:869cf507173a	468	/** @defgroup FSMC_Data_Setup_Time
emilmont	77:869cf507173a	469	* @{
emilmont	77:869cf507173a	470	*/
emilmont	77:869cf507173a	471	#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
emilmont	77:869cf507173a	472	/**
emilmont	77:869cf507173a	473	* @}
emilmont	77:869cf507173a	474	*/
emilmont	77:869cf507173a	475
emilmont	77:869cf507173a	476	/** @defgroup FSMC_Bus_Turn_around_Duration
emilmont	77:869cf507173a	477	* @{
emilmont	77:869cf507173a	478	*/
emilmont	77:869cf507173a	479	#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
emilmont	77:869cf507173a	480	/**
emilmont	77:869cf507173a	481	* @}
emilmont	77:869cf507173a	482	*/
emilmont	77:869cf507173a	483
emilmont	77:869cf507173a	484	/** @defgroup FSMC_CLK_Division
emilmont	77:869cf507173a	485	* @{
emilmont	77:869cf507173a	486	*/
emilmont	77:869cf507173a	487	#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
emilmont	77:869cf507173a	488	/**
emilmont	77:869cf507173a	489	* @}
emilmont	77:869cf507173a	490	*/
emilmont	77:869cf507173a	491
emilmont	77:869cf507173a	492	/** @defgroup FSMC_Data_Latency
emilmont	77:869cf507173a	493	* @{
emilmont	77:869cf507173a	494	*/
emilmont	77:869cf507173a	495	#define IS_FSMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
emilmont	77:869cf507173a	496	/**
emilmont	77:869cf507173a	497	* @}
emilmont	77:869cf507173a	498	*/
emilmont	77:869cf507173a	499
emilmont	77:869cf507173a	500	/** @defgroup FSMC_Access_Mode
emilmont	77:869cf507173a	501	* @{
emilmont	77:869cf507173a	502	*/
emilmont	77:869cf507173a	503	#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
emilmont	77:869cf507173a	504	#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
emilmont	77:869cf507173a	505	#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
emilmont	77:869cf507173a	506	#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
emilmont	77:869cf507173a	507
emilmont	77:869cf507173a	508	#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_ACCESS_MODE_A) \|\| \
emilmont	77:869cf507173a	509	((MODE) == FSMC_ACCESS_MODE_B) \|\| \
emilmont	77:869cf507173a	510	((MODE) == FSMC_ACCESS_MODE_C) \|\| \
emilmont	77:869cf507173a	511	((MODE) == FSMC_ACCESS_MODE_D))
emilmont	77:869cf507173a	512	/**
emilmont	77:869cf507173a	513	* @}
emilmont	77:869cf507173a	514	*/
emilmont	77:869cf507173a	515
emilmont	77:869cf507173a	516	/**
emilmont	77:869cf507173a	517	* @}
emilmont	77:869cf507173a	518	*/
emilmont	77:869cf507173a	519
emilmont	77:869cf507173a	520	/** @defgroup FSMC_NAND_Controller
emilmont	77:869cf507173a	521	* @{
emilmont	77:869cf507173a	522	*/
emilmont	77:869cf507173a	523
emilmont	77:869cf507173a	524	/** @defgroup FSMC_NAND_Bank
emilmont	77:869cf507173a	525	* @{
emilmont	77:869cf507173a	526	*/
emilmont	77:869cf507173a	527	#define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	528	#define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	529
emilmont	77:869cf507173a	530	#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) \|\| \
emilmont	77:869cf507173a	531	((BANK) == FSMC_NAND_BANK3))
emilmont	77:869cf507173a	532
emilmont	77:869cf507173a	533	/**
emilmont	77:869cf507173a	534	* @}
emilmont	77:869cf507173a	535	*/
emilmont	77:869cf507173a	536
emilmont	77:869cf507173a	537	/** @defgroup FSMC_Wait_feature
emilmont	77:869cf507173a	538	* @{
emilmont	77:869cf507173a	539	*/
emilmont	77:869cf507173a	540	#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	541	#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
emilmont	77:869cf507173a	542
emilmont	77:869cf507173a	543	#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
bogdanm	85:024bf7f99721	544	((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
emilmont	77:869cf507173a	545	/**
emilmont	77:869cf507173a	546	* @}
emilmont	77:869cf507173a	547	*/
emilmont	77:869cf507173a	548
emilmont	77:869cf507173a	549	/** @defgroup FSMC_PCR_Memory_Type
emilmont	77:869cf507173a	550	* @{
emilmont	77:869cf507173a	551	*/
emilmont	77:869cf507173a	552	#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
emilmont	77:869cf507173a	553	#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
emilmont	77:869cf507173a	554	/**
emilmont	77:869cf507173a	555	* @}
emilmont	77:869cf507173a	556	*/
emilmont	77:869cf507173a	557
emilmont	77:869cf507173a	558	/** @defgroup FSMC_NAND_Data_Width
emilmont	77:869cf507173a	559	* @{
emilmont	77:869cf507173a	560	*/
emilmont	77:869cf507173a	561	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	562	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	563
emilmont	77:869cf507173a	564	#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
emilmont	77:869cf507173a	565	((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
emilmont	77:869cf507173a	566	/**
emilmont	77:869cf507173a	567	* @}
emilmont	77:869cf507173a	568	*/
emilmont	77:869cf507173a	569
emilmont	77:869cf507173a	570	/** @defgroup FSMC_ECC
emilmont	77:869cf507173a	571	* @{
emilmont	77:869cf507173a	572	*/
emilmont	77:869cf507173a	573	#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	574	#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
emilmont	77:869cf507173a	575
emilmont	77:869cf507173a	576	#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) \|\| \
emilmont	77:869cf507173a	577	((STATE) == FSMC_NAND_ECC_ENABLE))
emilmont	77:869cf507173a	578	/**
emilmont	77:869cf507173a	579	* @}
emilmont	77:869cf507173a	580	*/
emilmont	77:869cf507173a	581
emilmont	77:869cf507173a	582	/** @defgroup FSMC_ECC_Page_Size
emilmont	77:869cf507173a	583	* @{
emilmont	77:869cf507173a	584	*/
emilmont	77:869cf507173a	585	#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	586	#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
emilmont	77:869cf507173a	587	#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
emilmont	77:869cf507173a	588	#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
emilmont	77:869cf507173a	589	#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
emilmont	77:869cf507173a	590	#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
emilmont	77:869cf507173a	591
emilmont	77:869cf507173a	592	#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
emilmont	77:869cf507173a	593	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
emilmont	77:869cf507173a	594	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
emilmont	77:869cf507173a	595	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
emilmont	77:869cf507173a	596	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
emilmont	77:869cf507173a	597	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
emilmont	77:869cf507173a	598	/**
emilmont	77:869cf507173a	599	* @}
emilmont	77:869cf507173a	600	*/
emilmont	77:869cf507173a	601
emilmont	77:869cf507173a	602	/** @defgroup FSMC_TCLR_Setup_Time
emilmont	77:869cf507173a	603	* @{
emilmont	77:869cf507173a	604	*/
emilmont	77:869cf507173a	605	#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
emilmont	77:869cf507173a	606	/**
emilmont	77:869cf507173a	607	* @}
emilmont	77:869cf507173a	608	*/
emilmont	77:869cf507173a	609
emilmont	77:869cf507173a	610	/** @defgroup FSMC_TAR_Setup_Time
emilmont	77:869cf507173a	611	* @{
emilmont	77:869cf507173a	612	*/
emilmont	77:869cf507173a	613	#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
emilmont	77:869cf507173a	614	/**
emilmont	77:869cf507173a	615	* @}
emilmont	77:869cf507173a	616	*/
emilmont	77:869cf507173a	617
emilmont	77:869cf507173a	618	/** @defgroup FSMC_Setup_Time
emilmont	77:869cf507173a	619	* @{
emilmont	77:869cf507173a	620	*/
emilmont	77:869cf507173a	621	#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
emilmont	77:869cf507173a	622	/**
emilmont	77:869cf507173a	623	* @}
emilmont	77:869cf507173a	624	*/
emilmont	77:869cf507173a	625
emilmont	77:869cf507173a	626	/** @defgroup FSMC_Wait_Setup_Time
emilmont	77:869cf507173a	627	* @{
emilmont	77:869cf507173a	628	*/
emilmont	77:869cf507173a	629	#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
emilmont	77:869cf507173a	630	/**
emilmont	77:869cf507173a	631	* @}
emilmont	77:869cf507173a	632	*/
emilmont	77:869cf507173a	633
emilmont	77:869cf507173a	634	/** @defgroup FSMC_Hold_Setup_Time
emilmont	77:869cf507173a	635	* @{
emilmont	77:869cf507173a	636	*/
emilmont	77:869cf507173a	637	#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
emilmont	77:869cf507173a	638	/**
emilmont	77:869cf507173a	639	* @}
emilmont	77:869cf507173a	640	*/
emilmont	77:869cf507173a	641
emilmont	77:869cf507173a	642	/** @defgroup FSMC_HiZ_Setup_Time
emilmont	77:869cf507173a	643	* @{
emilmont	77:869cf507173a	644	*/
emilmont	77:869cf507173a	645	#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
emilmont	77:869cf507173a	646	/**
emilmont	77:869cf507173a	647	* @}
emilmont	77:869cf507173a	648	*/
emilmont	77:869cf507173a	649
emilmont	77:869cf507173a	650	/**
emilmont	77:869cf507173a	651	* @}
emilmont	77:869cf507173a	652	*/
emilmont	77:869cf507173a	653
emilmont	77:869cf507173a	654
emilmont	77:869cf507173a	655	/** @defgroup FSMC_NORSRAM_Device_Instance
emilmont	77:869cf507173a	656	* @{
emilmont	77:869cf507173a	657	*/
emilmont	77:869cf507173a	658	#define IS_FSMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_DEVICE)
emilmont	77:869cf507173a	659
emilmont	77:869cf507173a	660	/**
emilmont	77:869cf507173a	661	* @}
emilmont	77:869cf507173a	662	*/
emilmont	77:869cf507173a	663
emilmont	77:869cf507173a	664	/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance
emilmont	77:869cf507173a	665	* @{
emilmont	77:869cf507173a	666	*/
emilmont	77:869cf507173a	667	#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_EXTENDED_DEVICE)
emilmont	77:869cf507173a	668
emilmont	77:869cf507173a	669	/**
emilmont	77:869cf507173a	670	* @}
emilmont	77:869cf507173a	671	*/
emilmont	77:869cf507173a	672
emilmont	77:869cf507173a	673	/** @defgroup FSMC_NAND_Device_Instance
emilmont	77:869cf507173a	674	* @{
emilmont	77:869cf507173a	675	*/
emilmont	77:869cf507173a	676	#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
emilmont	77:869cf507173a	677
emilmont	77:869cf507173a	678	/**
emilmont	77:869cf507173a	679	* @}
emilmont	77:869cf507173a	680	*/
emilmont	77:869cf507173a	681
emilmont	77:869cf507173a	682	/** @defgroup FSMC_PCCARD_Device_Instance
emilmont	77:869cf507173a	683	* @{
emilmont	77:869cf507173a	684	*/
emilmont	77:869cf507173a	685	#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
emilmont	77:869cf507173a	686
emilmont	77:869cf507173a	687	/**
emilmont	77:869cf507173a	688	* @}
emilmont	77:869cf507173a	689	*/
emilmont	77:869cf507173a	690
emilmont	77:869cf507173a	691	/** @defgroup FSMC_Interrupt_definition
emilmont	77:869cf507173a	692	* @brief FSMC Interrupt definition
emilmont	77:869cf507173a	693	* @{
emilmont	77:869cf507173a	694	*/
emilmont	77:869cf507173a	695	#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
emilmont	77:869cf507173a	696	#define FSMC_IT_LEVEL ((uint32_t)0x00000010)
emilmont	77:869cf507173a	697	#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
emilmont	77:869cf507173a	698	#define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
emilmont	77:869cf507173a	699
emilmont	77:869cf507173a	700	#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
emilmont	77:869cf507173a	701	#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RISING_EDGE) \|\| \
emilmont	77:869cf507173a	702	((IT) == FSMC_IT_LEVEL) \|\| \
emilmont	77:869cf507173a	703	((IT) == FSMC_IT_FALLING_EDGE) \|\| \
emilmont	77:869cf507173a	704	((IT) == FSMC_IT_REFRESH_ERROR))
emilmont	77:869cf507173a	705	/**
emilmont	77:869cf507173a	706	* @}
emilmont	77:869cf507173a	707	*/
emilmont	77:869cf507173a	708
emilmont	77:869cf507173a	709	/** @defgroup FSMC_Flag_definition
emilmont	77:869cf507173a	710	* @brief FSMC Flag definition
emilmont	77:869cf507173a	711	* @{
emilmont	77:869cf507173a	712	*/
emilmont	77:869cf507173a	713	#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
emilmont	77:869cf507173a	714	#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
emilmont	77:869cf507173a	715	#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
emilmont	77:869cf507173a	716	#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
emilmont	77:869cf507173a	717
emilmont	77:869cf507173a	718	#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RISING_EDGE) \|\| \
emilmont	77:869cf507173a	719	((FLAG) == FSMC_FLAG_LEVEL) \|\| \
emilmont	77:869cf507173a	720	((FLAG) == FSMC_FLAG_FALLING_EDGE) \|\| \
emilmont	77:869cf507173a	721	((FLAG) == FSMC_FLAG_FEMPT))
emilmont	77:869cf507173a	722
emilmont	77:869cf507173a	723	#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
emilmont	77:869cf507173a	724
emilmont	77:869cf507173a	725
emilmont	77:869cf507173a	726	/**
emilmont	77:869cf507173a	727	* @}
emilmont	77:869cf507173a	728	*/
emilmont	77:869cf507173a	729
emilmont	77:869cf507173a	730
emilmont	77:869cf507173a	731	/* Exported macro ------------------------------------------------------------*/
emilmont	77:869cf507173a	732
emilmont	77:869cf507173a	733
emilmont	77:869cf507173a	734	/** @defgroup FSMC_NOR_Macros
emilmont	77:869cf507173a	735	* @brief macros to handle NOR device enable/disable and read/write operations
emilmont	77:869cf507173a	736	* @{
emilmont	77:869cf507173a	737	*/
emilmont	77:869cf507173a	738
emilmont	77:869cf507173a	739	/**
emilmont	77:869cf507173a	740	* @brief Enable the NORSRAM device access.
emilmont	77:869cf507173a	741	* @param __INSTANCE__: FSMC_NORSRAM Instance
emilmont	77:869cf507173a	742	* @param __BANK__: FSMC_NORSRAM Bank
emilmont	77:869cf507173a	743	* @retval none
emilmont	77:869cf507173a	744	*/
emilmont	77:869cf507173a	745	#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FSMC_BCR1_MBKEN)
emilmont	77:869cf507173a	746
emilmont	77:869cf507173a	747	/**
emilmont	77:869cf507173a	748	* @brief Disable the NORSRAM device access.
emilmont	77:869cf507173a	749	* @param __INSTANCE__: FSMC_NORSRAM Instance
emilmont	77:869cf507173a	750	* @param __BANK__: FSMC_NORSRAM Bank
emilmont	77:869cf507173a	751	* @retval none
emilmont	77:869cf507173a	752	*/
emilmont	77:869cf507173a	753	#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
emilmont	77:869cf507173a	754
emilmont	77:869cf507173a	755	/**
emilmont	77:869cf507173a	756	* @}
emilmont	77:869cf507173a	757	*/
emilmont	77:869cf507173a	758
emilmont	77:869cf507173a	759
emilmont	77:869cf507173a	760	/** @defgroup FSMC_NAND_Macros
emilmont	77:869cf507173a	761	* @brief macros to handle NAND device enable/disable
emilmont	77:869cf507173a	762	* @{
emilmont	77:869cf507173a	763	*/
emilmont	77:869cf507173a	764
emilmont	77:869cf507173a	765	/**
emilmont	77:869cf507173a	766	* @brief Enable the NAND device access.
emilmont	77:869cf507173a	767	* @param __INSTANCE__: FSMC_NAND Instance
emilmont	77:869cf507173a	768	* @param __BANK__: FSMC_NAND Bank
emilmont	77:869cf507173a	769	* @retval none
emilmont	77:869cf507173a	770	*/
emilmont	77:869cf507173a	771	#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FSMC_PCR2_PBKEN): \
emilmont	77:869cf507173a	772	((__INSTANCE__)->PCR3 \|= FSMC_PCR3_PBKEN))
emilmont	77:869cf507173a	773
emilmont	77:869cf507173a	774
emilmont	77:869cf507173a	775	/**
emilmont	77:869cf507173a	776	* @brief Disable the NAND device access.
emilmont	77:869cf507173a	777	* @param __INSTANCE__: FSMC_NAND Instance
emilmont	77:869cf507173a	778	* @param __BANK__: FSMC_NAND Bank
emilmont	77:869cf507173a	779	* @retval none
emilmont	77:869cf507173a	780	*/
emilmont	77:869cf507173a	781	#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
emilmont	77:869cf507173a	782	((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
emilmont	77:869cf507173a	783
emilmont	77:869cf507173a	784
emilmont	77:869cf507173a	785	/**
emilmont	77:869cf507173a	786	* @}
emilmont	77:869cf507173a	787	*/
emilmont	77:869cf507173a	788
emilmont	77:869cf507173a	789	/** @defgroup FSMC_PCCARD_Macros
emilmont	77:869cf507173a	790	* @brief macros to handle SRAM read/write operations
emilmont	77:869cf507173a	791	* @{
emilmont	77:869cf507173a	792	*/
emilmont	77:869cf507173a	793
emilmont	77:869cf507173a	794	/**
emilmont	77:869cf507173a	795	* @brief Enable the PCCARD device access.
emilmont	77:869cf507173a	796	* @param __INSTANCE__: FSMC_PCCARD Instance
emilmont	77:869cf507173a	797	* @retval none
emilmont	77:869cf507173a	798	*/
emilmont	77:869cf507173a	799	#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FSMC_PCR4_PBKEN)
emilmont	77:869cf507173a	800
emilmont	77:869cf507173a	801	/**
emilmont	77:869cf507173a	802	* @brief Disable the PCCARD device access.
emilmont	77:869cf507173a	803	* @param __INSTANCE__: FSMC_PCCARD Instance
emilmont	77:869cf507173a	804	* @retval none
emilmont	77:869cf507173a	805	*/
emilmont	77:869cf507173a	806	#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
emilmont	77:869cf507173a	807
emilmont	77:869cf507173a	808	/**
emilmont	77:869cf507173a	809	* @}
emilmont	77:869cf507173a	810	*/
emilmont	77:869cf507173a	811
emilmont	77:869cf507173a	812	/** @defgroup FSMC_Interrupt
emilmont	77:869cf507173a	813	* @brief macros to handle FSMC interrupts
emilmont	77:869cf507173a	814	* @{
emilmont	77:869cf507173a	815	*/
emilmont	77:869cf507173a	816
emilmont	77:869cf507173a	817	/**
emilmont	77:869cf507173a	818	* @brief Enable the NAND device interrupt.
emilmont	77:869cf507173a	819	* @param __INSTANCE__: FSMC_NAND Instance
emilmont	77:869cf507173a	820	* @param __BANK__: FSMC_NAND Bank
emilmont	77:869cf507173a	821	* @param __INTERRUPT__: FSMC_NAND interrupt
emilmont	77:869cf507173a	822	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	823	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	824	* @arg FSMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	825	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	826	* @retval None
emilmont	77:869cf507173a	827	*/
emilmont	77:869cf507173a	828	#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
emilmont	77:869cf507173a	829	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
emilmont	77:869cf507173a	830
emilmont	77:869cf507173a	831	/**
emilmont	77:869cf507173a	832	* @brief Disable the NAND device interrupt.
emilmont	77:869cf507173a	833	* @param __INSTANCE__: FSMC_NAND Instance
emilmont	77:869cf507173a	834	* @param __BANK__: FSMC_NAND Bank
emilmont	77:869cf507173a	835	* @param __INTERRUPT__: FSMC_NAND interrupt
emilmont	77:869cf507173a	836	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	837	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	838	* @arg FSMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	839	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	840	* @retval None
emilmont	77:869cf507173a	841	*/
emilmont	77:869cf507173a	842	#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
emilmont	77:869cf507173a	843	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
emilmont	77:869cf507173a	844
emilmont	77:869cf507173a	845	/**
emilmont	77:869cf507173a	846	* @brief Get flag status of the NAND device.
emilmont	77:869cf507173a	847	* @param __INSTANCE__: FSMC_NAND Instance
emilmont	77:869cf507173a	848	* @param __BANK__: FSMC_NAND Bank
emilmont	77:869cf507173a	849	* @param __FLAG__: FSMC_NAND flag
emilmont	77:869cf507173a	850	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	851	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	852	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	853	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	854	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	855	* @retval The state of FLAG (SET or RESET).
emilmont	77:869cf507173a	856	*/
emilmont	77:869cf507173a	857	#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
emilmont	77:869cf507173a	858	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
emilmont	77:869cf507173a	859	/**
emilmont	77:869cf507173a	860	* @brief Clear flag status of the NAND device.
emilmont	77:869cf507173a	861	* @param __INSTANCE__: FSMC_NAND Instance
emilmont	77:869cf507173a	862	* @param __BANK__: FSMC_NAND Bank
emilmont	77:869cf507173a	863	* @param __FLAG__: FSMC_NAND flag
emilmont	77:869cf507173a	864	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	865	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	866	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	867	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	868	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	869	* @retval None
emilmont	77:869cf507173a	870	*/
emilmont	77:869cf507173a	871	#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
emilmont	77:869cf507173a	872	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
emilmont	77:869cf507173a	873	/**
emilmont	77:869cf507173a	874	* @brief Enable the PCCARD device interrupt.
emilmont	77:869cf507173a	875	* @param __INSTANCE__: FSMC_PCCARD Instance
emilmont	77:869cf507173a	876	* @param __INTERRUPT__: FSMC_PCCARD interrupt
emilmont	77:869cf507173a	877	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	878	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	879	* @arg FSMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	880	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	881	* @retval None
emilmont	77:869cf507173a	882	*/
emilmont	77:869cf507173a	883	#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
emilmont	77:869cf507173a	884
emilmont	77:869cf507173a	885	/**
emilmont	77:869cf507173a	886	* @brief Disable the PCCARD device interrupt.
emilmont	77:869cf507173a	887	* @param __INSTANCE__: FSMC_PCCARD Instance
emilmont	77:869cf507173a	888	* @param __INTERRUPT__: FSMC_PCCARD interrupt
emilmont	77:869cf507173a	889	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	890	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	891	* @arg FSMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	892	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	893	* @retval None
emilmont	77:869cf507173a	894	*/
emilmont	77:869cf507173a	895	#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	896
emilmont	77:869cf507173a	897	/**
emilmont	77:869cf507173a	898	* @brief Get flag status of the PCCARD device.
emilmont	77:869cf507173a	899	* @param __INSTANCE__: FSMC_PCCARD Instance
emilmont	77:869cf507173a	900	* @param __FLAG__: FSMC_PCCARD flag
emilmont	77:869cf507173a	901	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	902	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	903	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	904	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	905	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	906	* @retval The state of FLAG (SET or RESET).
emilmont	77:869cf507173a	907	*/
emilmont	77:869cf507173a	908	#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
emilmont	77:869cf507173a	909
emilmont	77:869cf507173a	910	/**
emilmont	77:869cf507173a	911	* @brief Clear flag status of the PCCARD device.
emilmont	77:869cf507173a	912	* @param __INSTANCE__: FSMC_PCCARD Instance
emilmont	77:869cf507173a	913	* @param __FLAG__: FSMC_PCCARD flag
emilmont	77:869cf507173a	914	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	915	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	916	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	917	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	918	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	919	* @retval None
emilmont	77:869cf507173a	920	*/
emilmont	77:869cf507173a	921	#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
emilmont	77:869cf507173a	922
emilmont	77:869cf507173a	923	/**
emilmont	77:869cf507173a	924	* @}
emilmont	77:869cf507173a	925	*/
emilmont	77:869cf507173a	926
emilmont	77:869cf507173a	927	/* Exported functions --------------------------------------------------------*/
emilmont	77:869cf507173a	928
emilmont	77:869cf507173a	929	/* FSMC_NORSRAM Controller functions ******************************************/
emilmont	77:869cf507173a	930	/* Initialization/de-initialization functions */
emilmont	77:869cf507173a	931	HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_InitTypeDef Init);
emilmont	77:869cf507173a	932	HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	933	HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
emilmont	77:869cf507173a	934	HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
emilmont	77:869cf507173a	935
emilmont	77:869cf507173a	936	/* FSMC_NORSRAM Control functions */
emilmont	77:869cf507173a	937	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	938	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	939
emilmont	77:869cf507173a	940	/* FSMC_NAND Controller functions *********************************************/
emilmont	77:869cf507173a	941	/* Initialization/de-initialization functions */
emilmont	77:869cf507173a	942	HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_InitTypeDef Init);
emilmont	77:869cf507173a	943	HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	944	HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	945	HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	946
emilmont	77:869cf507173a	947	/* FSMC_NAND Control functions */
emilmont	77:869cf507173a	948	HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	949	HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	950	HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
emilmont	77:869cf507173a	951
emilmont	77:869cf507173a	952	/* FSMC_PCCARD Controller functions *******************************************/
emilmont	77:869cf507173a	953	/* Initialization/de-initialization functions */
emilmont	77:869cf507173a	954	HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef Device, FSMC_PCCARD_InitTypeDef Init);
emilmont	77:869cf507173a	955	HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
emilmont	77:869cf507173a	956	HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
emilmont	77:869cf507173a	957	HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
emilmont	77:869cf507173a	958	HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
emilmont	77:869cf507173a	959
emilmont	77:869cf507173a	960	/* FSMC APIs, macros and typedefs redefinition */
emilmont	77:869cf507173a	961	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
emilmont	77:869cf507173a	962	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
emilmont	77:869cf507173a	963	#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
emilmont	77:869cf507173a	964	#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
emilmont	77:869cf507173a	965
emilmont	77:869cf507173a	966	#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
emilmont	77:869cf507173a	967	#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
emilmont	77:869cf507173a	968	#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
emilmont	77:869cf507173a	969	#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
emilmont	77:869cf507173a	970	#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
emilmont	77:869cf507173a	971	#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
emilmont	77:869cf507173a	972
emilmont	77:869cf507173a	973	#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
emilmont	77:869cf507173a	974	#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
emilmont	77:869cf507173a	975
emilmont	77:869cf507173a	976	#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
emilmont	77:869cf507173a	977	#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
emilmont	77:869cf507173a	978	#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
emilmont	77:869cf507173a	979
emilmont	77:869cf507173a	980	#define FMC_NAND_Init FSMC_NAND_Init
emilmont	77:869cf507173a	981	#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
emilmont	77:869cf507173a	982	#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
emilmont	77:869cf507173a	983	#define FMC_NAND_DeInit FSMC_NAND_DeInit
emilmont	77:869cf507173a	984	#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
emilmont	77:869cf507173a	985	#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
emilmont	77:869cf507173a	986	#define FMC_NAND_GetECC FSMC_NAND_GetECC
emilmont	77:869cf507173a	987	#define FMC_PCCARD_Init FSMC_PCCARD_Init
emilmont	77:869cf507173a	988	#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
emilmont	77:869cf507173a	989	#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
emilmont	77:869cf507173a	990	#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
emilmont	77:869cf507173a	991	#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
emilmont	77:869cf507173a	992
emilmont	77:869cf507173a	993	#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
emilmont	77:869cf507173a	994	#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
emilmont	77:869cf507173a	995	#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
emilmont	77:869cf507173a	996	#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
emilmont	77:869cf507173a	997	#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
emilmont	77:869cf507173a	998	#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
emilmont	77:869cf507173a	999	#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
emilmont	77:869cf507173a	1000	#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
emilmont	77:869cf507173a	1001	#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
emilmont	77:869cf507173a	1002	#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
emilmont	77:869cf507173a	1003	#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
emilmont	77:869cf507173a	1004	#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
emilmont	77:869cf507173a	1005
emilmont	77:869cf507173a	1006	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
emilmont	77:869cf507173a	1007	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
emilmont	77:869cf507173a	1008	#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
emilmont	77:869cf507173a	1009	#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
emilmont	77:869cf507173a	1010
emilmont	77:869cf507173a	1011	#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
emilmont	77:869cf507173a	1012	#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
emilmont	77:869cf507173a	1013	#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
emilmont	77:869cf507173a	1014	#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
emilmont	77:869cf507173a	1015
emilmont	77:869cf507173a	1016	#define FMC_NAND_BANK2 FSMC_NAND_BANK2
emilmont	77:869cf507173a	1017
emilmont	77:869cf507173a	1018	#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
emilmont	77:869cf507173a	1019	#define FMC_IT_LEVEL FSMC_IT_LEVEL
emilmont	77:869cf507173a	1020	#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
emilmont	77:869cf507173a	1021	#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
emilmont	77:869cf507173a	1022
emilmont	77:869cf507173a	1023	#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
emilmont	77:869cf507173a	1024	#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
emilmont	77:869cf507173a	1025	#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
emilmont	77:869cf507173a	1026	#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
emilmont	77:869cf507173a	1027
emilmont	77:869cf507173a	1028	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
emilmont	77:869cf507173a	1029
emilmont	77:869cf507173a	1030	/**
emilmont	77:869cf507173a	1031	* @}
emilmont	77:869cf507173a	1032	*/
emilmont	77:869cf507173a	1033
emilmont	77:869cf507173a	1034	/**
emilmont	77:869cf507173a	1035	* @}
emilmont	77:869cf507173a	1036	*/
emilmont	77:869cf507173a	1037
emilmont	77:869cf507173a	1038	#ifdef __cplusplus
emilmont	77:869cf507173a	1039	}
emilmont	77:869cf507173a	1040	#endif
emilmont	77:869cf507173a	1041
emilmont	77:869cf507173a	1042	#endif /* __STM32F4xx_LL_FSMC_H */
emilmont	77:869cf507173a	1043
emilmont	77:869cf507173a	1044	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/