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TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: 85:024bf7f99721
Child:: 90:cb3d968589d8

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_hal_spi.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
bogdanm	85:024bf7f99721	5	* @version V1.1.0RC2
bogdanm	85:024bf7f99721	6	* @date 14-May-2014
emilmont	77:869cf507173a	7	* @brief Header file of SPI HAL module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
emilmont	77:869cf507173a	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_HAL_SPI_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_HAL_SPI_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	47	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	48
emilmont	77:869cf507173a	49	/** @addtogroup STM32F4xx_HAL_Driver
emilmont	77:869cf507173a	50	* @{
emilmont	77:869cf507173a	51	*/
emilmont	77:869cf507173a	52
emilmont	77:869cf507173a	53	/** @addtogroup SPI
emilmont	77:869cf507173a	54	* @{
emilmont	77:869cf507173a	55	*/
emilmont	77:869cf507173a	56
emilmont	77:869cf507173a	57	/* Exported types ------------------------------------------------------------*/
emilmont	77:869cf507173a	58
emilmont	77:869cf507173a	59	/**
emilmont	77:869cf507173a	60	* @brief SPI Configuration Structure definition
emilmont	77:869cf507173a	61	*/
emilmont	77:869cf507173a	62	typedef struct
emilmont	77:869cf507173a	63	{
emilmont	77:869cf507173a	64	uint32_t Mode; /*!< Specifies the SPI operating mode.
emilmont	77:869cf507173a	65	This parameter can be a value of @ref SPI_mode */
emilmont	77:869cf507173a	66
emilmont	77:869cf507173a	67	uint32_t Direction; /*!< Specifies the SPI Directional mode state.
emilmont	77:869cf507173a	68	This parameter can be a value of @ref SPI_Direction_mode */
emilmont	77:869cf507173a	69
emilmont	77:869cf507173a	70	uint32_t DataSize; /*!< Specifies the SPI data size.
emilmont	77:869cf507173a	71	This parameter can be a value of @ref SPI_data_size */
emilmont	77:869cf507173a	72
emilmont	77:869cf507173a	73	uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
emilmont	77:869cf507173a	74	This parameter can be a value of @ref SPI_Clock_Polarity */
emilmont	77:869cf507173a	75
emilmont	77:869cf507173a	76	uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
emilmont	77:869cf507173a	77	This parameter can be a value of @ref SPI_Clock_Phase */
emilmont	77:869cf507173a	78
emilmont	77:869cf507173a	79	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
emilmont	77:869cf507173a	80	hardware (NSS pin) or by software using the SSI bit.
emilmont	77:869cf507173a	81	This parameter can be a value of @ref SPI_Slave_Select_management */
emilmont	77:869cf507173a	82
emilmont	77:869cf507173a	83	uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
emilmont	77:869cf507173a	84	used to configure the transmit and receive SCK clock.
emilmont	77:869cf507173a	85	This parameter can be a value of @ref SPI_BaudRate_Prescaler
emilmont	77:869cf507173a	86	@note The communication clock is derived from the master
emilmont	77:869cf507173a	87	clock. The slave clock does not need to be set */
emilmont	77:869cf507173a	88
emilmont	77:869cf507173a	89	uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
emilmont	77:869cf507173a	90	This parameter can be a value of @ref SPI_MSB_LSB_transmission */
emilmont	77:869cf507173a	91
emilmont	77:869cf507173a	92	uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
emilmont	77:869cf507173a	93	This parameter can be a value of @ref SPI_TI_mode */
emilmont	77:869cf507173a	94
emilmont	77:869cf507173a	95	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
emilmont	77:869cf507173a	96	This parameter can be a value of @ref SPI_CRC_Calculation */
emilmont	77:869cf507173a	97
emilmont	77:869cf507173a	98	uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
emilmont	77:869cf507173a	99	This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
emilmont	77:869cf507173a	100
emilmont	77:869cf507173a	101	}SPI_InitTypeDef;
emilmont	77:869cf507173a	102
emilmont	77:869cf507173a	103	/**
emilmont	77:869cf507173a	104	* @brief HAL SPI State structure definition
emilmont	77:869cf507173a	105	*/
emilmont	77:869cf507173a	106	typedef enum
emilmont	77:869cf507173a	107	{
emilmont	77:869cf507173a	108	HAL_SPI_STATE_RESET = 0x00, /!< SPI not yet initialized or disabled /
emilmont	77:869cf507173a	109	HAL_SPI_STATE_READY = 0x01, /!< SPI initialized and ready for use /
emilmont	77:869cf507173a	110	HAL_SPI_STATE_BUSY = 0x02, /!< SPI process is ongoing /
emilmont	77:869cf507173a	111	HAL_SPI_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
emilmont	77:869cf507173a	112	HAL_SPI_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
emilmont	77:869cf507173a	113	HAL_SPI_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
emilmont	77:869cf507173a	114	HAL_SPI_STATE_ERROR = 0x03 /!< SPI error state /
emilmont	77:869cf507173a	115
emilmont	77:869cf507173a	116	}HAL_SPI_StateTypeDef;
emilmont	77:869cf507173a	117
emilmont	77:869cf507173a	118	/**
emilmont	77:869cf507173a	119	* @brief HAL SPI Error Code structure definition
emilmont	77:869cf507173a	120	*/
emilmont	77:869cf507173a	121	typedef enum
emilmont	77:869cf507173a	122	{
emilmont	77:869cf507173a	123	HAL_SPI_ERROR_NONE = 0x00, /!< No error /
emilmont	77:869cf507173a	124	HAL_SPI_ERROR_MODF = 0x01, /!< MODF error /
emilmont	77:869cf507173a	125	HAL_SPI_ERROR_CRC = 0x02, /!< CRC error /
emilmont	77:869cf507173a	126	HAL_SPI_ERROR_OVR = 0x04, /!< OVR error /
emilmont	77:869cf507173a	127	HAL_SPI_ERROR_FRE = 0x08, /!< FRE error /
emilmont	77:869cf507173a	128	HAL_SPI_ERROR_DMA = 0x10, /!< DMA transfer error /
emilmont	77:869cf507173a	129	HAL_SPI_ERROR_FLAG = 0x20 /!< Flag: RXNE,TXE, BSY /
emilmont	77:869cf507173a	130
emilmont	77:869cf507173a	131	}HAL_SPI_ErrorTypeDef;
emilmont	77:869cf507173a	132
emilmont	77:869cf507173a	133	/**
emilmont	77:869cf507173a	134	* @brief SPI handle Structure definition
emilmont	77:869cf507173a	135	*/
emilmont	77:869cf507173a	136	typedef struct __SPI_HandleTypeDef
emilmont	77:869cf507173a	137	{
emilmont	77:869cf507173a	138	SPI_TypeDef Instance; / SPI registers base address */
emilmont	77:869cf507173a	139
emilmont	77:869cf507173a	140	SPI_InitTypeDef Init; /* SPI communication parameters */
emilmont	77:869cf507173a	141
emilmont	77:869cf507173a	142	uint8_t pTxBuffPtr; / Pointer to SPI Tx transfer Buffer */
emilmont	77:869cf507173a	143
emilmont	77:869cf507173a	144	uint16_t TxXferSize; /* SPI Tx transfer size */
emilmont	77:869cf507173a	145
emilmont	77:869cf507173a	146	uint16_t TxXferCount; /* SPI Tx Transfer Counter */
emilmont	77:869cf507173a	147
emilmont	77:869cf507173a	148	uint8_t pRxBuffPtr; / Pointer to SPI Rx transfer Buffer */
emilmont	77:869cf507173a	149
emilmont	77:869cf507173a	150	uint16_t RxXferSize; /* SPI Rx transfer size */
emilmont	77:869cf507173a	151
emilmont	77:869cf507173a	152	uint16_t RxXferCount; /* SPI Rx Transfer Counter */
emilmont	77:869cf507173a	153
emilmont	77:869cf507173a	154	DMA_HandleTypeDef hdmatx; / SPI Tx DMA handle parameters */
emilmont	77:869cf507173a	155
emilmont	77:869cf507173a	156	DMA_HandleTypeDef hdmarx; / SPI Rx DMA handle parameters */
emilmont	77:869cf507173a	157
emilmont	77:869cf507173a	158	void (RxISR)(struct __SPI_HandleTypeDef hspi); /* function pointer on Rx ISR */
emilmont	77:869cf507173a	159
emilmont	77:869cf507173a	160	void (TxISR)(struct __SPI_HandleTypeDef hspi); /* function pointer on Tx ISR */
emilmont	77:869cf507173a	161
emilmont	77:869cf507173a	162	HAL_LockTypeDef Lock; /* SPI locking object */
emilmont	77:869cf507173a	163
emilmont	77:869cf507173a	164	__IO HAL_SPI_StateTypeDef State; /* SPI communication state */
emilmont	77:869cf507173a	165
emilmont	77:869cf507173a	166	__IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
emilmont	77:869cf507173a	167
emilmont	77:869cf507173a	168	}SPI_HandleTypeDef;
emilmont	77:869cf507173a	169
emilmont	77:869cf507173a	170	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	171
emilmont	77:869cf507173a	172	/** @defgroup SPI_Exported_Constants
emilmont	77:869cf507173a	173	* @{
emilmont	77:869cf507173a	174	*/
emilmont	77:869cf507173a	175
emilmont	77:869cf507173a	176	/** @defgroup SPI_mode
emilmont	77:869cf507173a	177	* @{
emilmont	77:869cf507173a	178	*/
emilmont	77:869cf507173a	179	#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	180	#define SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI)
emilmont	77:869cf507173a	181
emilmont	77:869cf507173a	182	#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) \|\| \
emilmont	77:869cf507173a	183	((MODE) == SPI_MODE_MASTER))
emilmont	77:869cf507173a	184	/**
emilmont	77:869cf507173a	185	* @}
emilmont	77:869cf507173a	186	*/
emilmont	77:869cf507173a	187
emilmont	77:869cf507173a	188	/** @defgroup SPI_Direction_mode
emilmont	77:869cf507173a	189	* @{
emilmont	77:869cf507173a	190	*/
emilmont	77:869cf507173a	191	#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
emilmont	77:869cf507173a	192	#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
emilmont	77:869cf507173a	193	#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
emilmont	77:869cf507173a	194
emilmont	77:869cf507173a	195	#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) \|\| \
emilmont	77:869cf507173a	196	((MODE) == SPI_DIRECTION_2LINES_RXONLY) \|\| \
emilmont	77:869cf507173a	197	((MODE) == SPI_DIRECTION_1LINE))
emilmont	77:869cf507173a	198
emilmont	77:869cf507173a	199	#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) \|\| \
emilmont	77:869cf507173a	200	((MODE) == SPI_DIRECTION_1LINE))
emilmont	77:869cf507173a	201
emilmont	77:869cf507173a	202	#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
emilmont	77:869cf507173a	203
emilmont	77:869cf507173a	204	/**
emilmont	77:869cf507173a	205	* @}
emilmont	77:869cf507173a	206	*/
emilmont	77:869cf507173a	207
emilmont	77:869cf507173a	208	/** @defgroup SPI_data_size
emilmont	77:869cf507173a	209	* @{
emilmont	77:869cf507173a	210	*/
emilmont	77:869cf507173a	211	#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
emilmont	77:869cf507173a	212	#define SPI_DATASIZE_16BIT SPI_CR1_DFF
emilmont	77:869cf507173a	213
emilmont	77:869cf507173a	214	#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) \|\| \
emilmont	77:869cf507173a	215	((DATASIZE) == SPI_DATASIZE_8BIT))
emilmont	77:869cf507173a	216	/**
emilmont	77:869cf507173a	217	* @}
emilmont	77:869cf507173a	218	*/
emilmont	77:869cf507173a	219
emilmont	77:869cf507173a	220	/** @defgroup SPI_Clock_Polarity
emilmont	77:869cf507173a	221	* @{
emilmont	77:869cf507173a	222	*/
emilmont	77:869cf507173a	223	#define SPI_POLARITY_LOW ((uint32_t)0x00000000)
emilmont	77:869cf507173a	224	#define SPI_POLARITY_HIGH SPI_CR1_CPOL
emilmont	77:869cf507173a	225
emilmont	77:869cf507173a	226	#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) \|\| \
emilmont	77:869cf507173a	227	((CPOL) == SPI_POLARITY_HIGH))
emilmont	77:869cf507173a	228	/**
emilmont	77:869cf507173a	229	* @}
emilmont	77:869cf507173a	230	*/
emilmont	77:869cf507173a	231
emilmont	77:869cf507173a	232	/** @defgroup SPI_Clock_Phase
emilmont	77:869cf507173a	233	* @{
emilmont	77:869cf507173a	234	*/
emilmont	77:869cf507173a	235	#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	236	#define SPI_PHASE_2EDGE SPI_CR1_CPHA
emilmont	77:869cf507173a	237
emilmont	77:869cf507173a	238	#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) \|\| \
emilmont	77:869cf507173a	239	((CPHA) == SPI_PHASE_2EDGE))
emilmont	77:869cf507173a	240	/**
emilmont	77:869cf507173a	241	* @}
emilmont	77:869cf507173a	242	*/
emilmont	77:869cf507173a	243
emilmont	77:869cf507173a	244	/** @defgroup SPI_Slave_Select_management
emilmont	77:869cf507173a	245	* @{
emilmont	77:869cf507173a	246	*/
emilmont	77:869cf507173a	247	#define SPI_NSS_SOFT SPI_CR1_SSM
emilmont	77:869cf507173a	248	#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
emilmont	77:869cf507173a	249	#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
emilmont	77:869cf507173a	250
emilmont	77:869cf507173a	251	#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) \|\| \
emilmont	77:869cf507173a	252	((NSS) == SPI_NSS_HARD_INPUT) \|\| \
emilmont	77:869cf507173a	253	((NSS) == SPI_NSS_HARD_OUTPUT))
emilmont	77:869cf507173a	254	/**
emilmont	77:869cf507173a	255	* @}
emilmont	77:869cf507173a	256	*/
emilmont	77:869cf507173a	257
emilmont	77:869cf507173a	258	/** @defgroup SPI_BaudRate_Prescaler
emilmont	77:869cf507173a	259	* @{
emilmont	77:869cf507173a	260	*/
emilmont	77:869cf507173a	261	#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	262	#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	263	#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	264	#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
emilmont	77:869cf507173a	265	#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	266	#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
emilmont	77:869cf507173a	267	#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
emilmont	77:869cf507173a	268	#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
emilmont	77:869cf507173a	269
emilmont	77:869cf507173a	270	#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) \|\| \
emilmont	77:869cf507173a	271	((PRESCALER) == SPI_BAUDRATEPRESCALER_4) \|\| \
emilmont	77:869cf507173a	272	((PRESCALER) == SPI_BAUDRATEPRESCALER_8) \|\| \
emilmont	77:869cf507173a	273	((PRESCALER) == SPI_BAUDRATEPRESCALER_16) \|\| \
emilmont	77:869cf507173a	274	((PRESCALER) == SPI_BAUDRATEPRESCALER_32) \|\| \
emilmont	77:869cf507173a	275	((PRESCALER) == SPI_BAUDRATEPRESCALER_64) \|\| \
emilmont	77:869cf507173a	276	((PRESCALER) == SPI_BAUDRATEPRESCALER_128) \|\| \
emilmont	77:869cf507173a	277	((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
emilmont	77:869cf507173a	278	/**
emilmont	77:869cf507173a	279	* @}
emilmont	77:869cf507173a	280	*/
emilmont	77:869cf507173a	281
emilmont	77:869cf507173a	282	/** @defgroup SPI_MSB_LSB_transmission
emilmont	77:869cf507173a	283	* @{
emilmont	77:869cf507173a	284	*/
emilmont	77:869cf507173a	285	#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
emilmont	77:869cf507173a	286	#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
emilmont	77:869cf507173a	287
emilmont	77:869cf507173a	288	#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) \|\| \
emilmont	77:869cf507173a	289	((BIT) == SPI_FIRSTBIT_LSB))
emilmont	77:869cf507173a	290	/**
emilmont	77:869cf507173a	291	* @}
emilmont	77:869cf507173a	292	*/
emilmont	77:869cf507173a	293
emilmont	77:869cf507173a	294	/** @defgroup SPI_TI_mode
emilmont	77:869cf507173a	295	* @{
emilmont	77:869cf507173a	296	*/
emilmont	77:869cf507173a	297	#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
emilmont	77:869cf507173a	298	#define SPI_TIMODE_ENABLED SPI_CR2_FRF
emilmont	77:869cf507173a	299
emilmont	77:869cf507173a	300	#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) \|\| \
emilmont	77:869cf507173a	301	((MODE) == SPI_TIMODE_ENABLED))
emilmont	77:869cf507173a	302	/**
emilmont	77:869cf507173a	303	* @}
emilmont	77:869cf507173a	304	*/
emilmont	77:869cf507173a	305
emilmont	77:869cf507173a	306	/** @defgroup SPI_CRC_Calculation
emilmont	77:869cf507173a	307	* @{
emilmont	77:869cf507173a	308	*/
emilmont	77:869cf507173a	309	#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
emilmont	77:869cf507173a	310	#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
emilmont	77:869cf507173a	311
emilmont	77:869cf507173a	312	#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) \|\| \
emilmont	77:869cf507173a	313	((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
emilmont	77:869cf507173a	314	/**
emilmont	77:869cf507173a	315	* @}
emilmont	77:869cf507173a	316	*/
emilmont	77:869cf507173a	317
emilmont	77:869cf507173a	318	/** @defgroup SPI_Interrupt_configuration_definition
emilmont	77:869cf507173a	319	* @{
emilmont	77:869cf507173a	320	*/
emilmont	77:869cf507173a	321	#define SPI_IT_TXE SPI_CR2_TXEIE
emilmont	77:869cf507173a	322	#define SPI_IT_RXNE SPI_CR2_RXNEIE
emilmont	77:869cf507173a	323	#define SPI_IT_ERR SPI_CR2_ERRIE
emilmont	77:869cf507173a	324	/**
emilmont	77:869cf507173a	325	* @}
emilmont	77:869cf507173a	326	*/
emilmont	77:869cf507173a	327
emilmont	77:869cf507173a	328	/** @defgroup SPI_Flag_definition
emilmont	77:869cf507173a	329	* @{
emilmont	77:869cf507173a	330	*/
emilmont	77:869cf507173a	331	#define SPI_FLAG_RXNE SPI_SR_RXNE
emilmont	77:869cf507173a	332	#define SPI_FLAG_TXE SPI_SR_TXE
emilmont	77:869cf507173a	333	#define SPI_FLAG_CRCERR SPI_SR_CRCERR
emilmont	77:869cf507173a	334	#define SPI_FLAG_MODF SPI_SR_MODF
emilmont	77:869cf507173a	335	#define SPI_FLAG_OVR SPI_SR_OVR
emilmont	77:869cf507173a	336	#define SPI_FLAG_BSY SPI_SR_BSY
emilmont	77:869cf507173a	337	#define SPI_FLAG_FRE SPI_SR_FRE
emilmont	77:869cf507173a	338
emilmont	77:869cf507173a	339	/**
emilmont	77:869cf507173a	340	* @}
emilmont	77:869cf507173a	341	*/
emilmont	77:869cf507173a	342
emilmont	77:869cf507173a	343	/**
emilmont	77:869cf507173a	344	* @}
emilmont	77:869cf507173a	345	*/
emilmont	77:869cf507173a	346
emilmont	77:869cf507173a	347	/* Exported macro ------------------------------------------------------------*/
emilmont	77:869cf507173a	348
bogdanm	85:024bf7f99721	349	/** @brief Reset SPI handle state
bogdanm	85:024bf7f99721	350	* @param __HANDLE__: specifies the SPI handle.
bogdanm	85:024bf7f99721	351	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	352	* @retval None
bogdanm	85:024bf7f99721	353	*/
bogdanm	85:024bf7f99721	354	#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
bogdanm	85:024bf7f99721	355
emilmont	77:869cf507173a	356	/** @brief Enable or disable the specified SPI interrupts.
emilmont	77:869cf507173a	357	* @param __HANDLE__: specifies the SPI handle.
emilmont	77:869cf507173a	358	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
emilmont	77:869cf507173a	359	* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
emilmont	77:869cf507173a	360	* This parameter can be one of the following values:
emilmont	77:869cf507173a	361	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
emilmont	77:869cf507173a	362	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
emilmont	77:869cf507173a	363	* @arg SPI_IT_ERR: Error interrupt enable
emilmont	77:869cf507173a	364	* @retval None
emilmont	77:869cf507173a	365	*/
emilmont	77:869cf507173a	366	#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 \|= (__INTERRUPT__))
emilmont	77:869cf507173a	367	#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
emilmont	77:869cf507173a	368
emilmont	77:869cf507173a	369	/** @brief Check if the specified SPI interrupt source is enabled or disabled.
emilmont	77:869cf507173a	370	* @param __HANDLE__: specifies the SPI handle.
emilmont	77:869cf507173a	371	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
emilmont	77:869cf507173a	372	* @param __INTERRUPT__: specifies the SPI interrupt source to check.
emilmont	77:869cf507173a	373	* This parameter can be one of the following values:
emilmont	77:869cf507173a	374	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
emilmont	77:869cf507173a	375	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
emilmont	77:869cf507173a	376	* @arg SPI_IT_ERR: Error interrupt enable
emilmont	77:869cf507173a	377	* @retval The new state of __IT__ (TRUE or FALSE).
emilmont	77:869cf507173a	378	*/
emilmont	77:869cf507173a	379	#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
emilmont	77:869cf507173a	380
emilmont	77:869cf507173a	381	/** @brief Check whether the specified SPI flag is set or not.
emilmont	77:869cf507173a	382	* @param __HANDLE__: specifies the SPI handle.
emilmont	77:869cf507173a	383	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
emilmont	77:869cf507173a	384	* @param __FLAG__: specifies the flag to check.
emilmont	77:869cf507173a	385	* This parameter can be one of the following values:
emilmont	77:869cf507173a	386	* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
emilmont	77:869cf507173a	387	* @arg SPI_FLAG_TXE: Transmit buffer empty flag
emilmont	77:869cf507173a	388	* @arg SPI_FLAG_CRCERR: CRC error flag
emilmont	77:869cf507173a	389	* @arg SPI_FLAG_MODF: Mode fault flag
emilmont	77:869cf507173a	390	* @arg SPI_FLAG_OVR: Overrun flag
emilmont	77:869cf507173a	391	* @arg SPI_FLAG_BSY: Busy flag
emilmont	77:869cf507173a	392	* @arg SPI_FLAG_FRE: Frame format error flag
emilmont	77:869cf507173a	393	* @retval The new state of __FLAG__ (TRUE or FALSE).
emilmont	77:869cf507173a	394	*/
emilmont	77:869cf507173a	395	#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
emilmont	77:869cf507173a	396
emilmont	77:869cf507173a	397	/** @brief Clear the SPI CRCERR pending flag.
emilmont	77:869cf507173a	398	* @param __HANDLE__: specifies the SPI handle.
emilmont	77:869cf507173a	399	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
emilmont	77:869cf507173a	400	* @retval None
emilmont	77:869cf507173a	401	*/
emilmont	77:869cf507173a	402	#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR &= ~(SPI_FLAG_CRCERR))
emilmont	77:869cf507173a	403
emilmont	77:869cf507173a	404	/** @brief Clear the SPI MODF pending flag.
emilmont	77:869cf507173a	405	* @param __HANDLE__: specifies the SPI handle.
emilmont	77:869cf507173a	406	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
emilmont	77:869cf507173a	407	* @retval None
emilmont	77:869cf507173a	408	*/
emilmont	77:869cf507173a	409	#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
emilmont	77:869cf507173a	410	(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0)
emilmont	77:869cf507173a	411
emilmont	77:869cf507173a	412	/** @brief Clear the SPI OVR pending flag.
emilmont	77:869cf507173a	413	* @param __HANDLE__: specifies the SPI handle.
emilmont	77:869cf507173a	414	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
emilmont	77:869cf507173a	415	* @retval None
emilmont	77:869cf507173a	416	*/
emilmont	77:869cf507173a	417	#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
emilmont	77:869cf507173a	418	(__HANDLE__)->Instance->SR;}while(0)
emilmont	77:869cf507173a	419
emilmont	77:869cf507173a	420	/** @brief Clear the SPI FRE pending flag.
emilmont	77:869cf507173a	421	* @param __HANDLE__: specifies the SPI handle.
emilmont	77:869cf507173a	422	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
emilmont	77:869cf507173a	423	* @retval None
emilmont	77:869cf507173a	424	*/
emilmont	77:869cf507173a	425	#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
emilmont	77:869cf507173a	426
emilmont	77:869cf507173a	427	#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 \|= SPI_CR1_SPE)
emilmont	77:869cf507173a	428	#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
emilmont	77:869cf507173a	429
emilmont	77:869cf507173a	430	#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
emilmont	77:869cf507173a	431
emilmont	77:869cf507173a	432	#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 \|= SPI_CR1_BIDIOE)
emilmont	77:869cf507173a	433
emilmont	77:869cf507173a	434	#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
emilmont	77:869cf507173a	435
emilmont	77:869cf507173a	436	#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
emilmont	77:869cf507173a	437	(__HANDLE__)->Instance->CR1 \|= SPI_CR1_CRCEN;}while(0)
emilmont	77:869cf507173a	438
emilmont	77:869cf507173a	439	/* Exported functions --------------------------------------------------------*/
emilmont	77:869cf507173a	440
emilmont	77:869cf507173a	441	/* Initialization/de-initialization functions **********************************/
emilmont	77:869cf507173a	442	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
emilmont	77:869cf507173a	443	HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
emilmont	77:869cf507173a	444	void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
emilmont	77:869cf507173a	445	void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
emilmont	77:869cf507173a	446
emilmont	77:869cf507173a	447	/* I/O operation functions *****************************************************/
emilmont	77:869cf507173a	448	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout);
emilmont	77:869cf507173a	449	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout);
emilmont	77:869cf507173a	450	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
emilmont	77:869cf507173a	451	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
emilmont	77:869cf507173a	452	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
emilmont	77:869cf507173a	453	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size);
emilmont	77:869cf507173a	454	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
emilmont	77:869cf507173a	455	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
emilmont	77:869cf507173a	456	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size);
emilmont	77:869cf507173a	457	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
bogdanm	81:7d30d6019079	458	void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm	81:7d30d6019079	459	void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm	81:7d30d6019079	460	void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm	81:7d30d6019079	461	void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
emilmont	77:869cf507173a	462
emilmont	77:869cf507173a	463	/* Peripheral State and Control functions **************************************/
emilmont	77:869cf507173a	464	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
emilmont	77:869cf507173a	465	HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
emilmont	77:869cf507173a	466
emilmont	77:869cf507173a	467	/**
emilmont	77:869cf507173a	468	* @}
emilmont	77:869cf507173a	469	*/
emilmont	77:869cf507173a	470
emilmont	77:869cf507173a	471	/**
emilmont	77:869cf507173a	472	* @}
emilmont	77:869cf507173a	473	*/
emilmont	77:869cf507173a	474
emilmont	77:869cf507173a	475	#ifdef __cplusplus
emilmont	77:869cf507173a	476	}
emilmont	77:869cf507173a	477	#endif
emilmont	77:869cf507173a	478
emilmont	77:869cf507173a	479	#endif /* __STM32F4xx_HAL_SPI_H */
emilmont	77:869cf507173a	480
emilmont	77:869cf507173a	481	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/