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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F401RE/core_cmInstr.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Parent:
77:869cf507173a
Child:
110:165afa46840b
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**************************************************************************//**
emilmont 77:869cf507173a 2 * @file core_cmInstr.h
emilmont 77:869cf507173a 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
emilmont 77:869cf507173a 4 * @version V3.20
emilmont 77:869cf507173a 5 * @date 05. March 2013
emilmont 77:869cf507173a 6 *
emilmont 77:869cf507173a 7 * @note
emilmont 77:869cf507173a 8 *
emilmont 77:869cf507173a 9 ******************************************************************************/
emilmont 77:869cf507173a 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
emilmont 77:869cf507173a 11
emilmont 77:869cf507173a 12 All rights reserved.
emilmont 77:869cf507173a 13 Redistribution and use in source and binary forms, with or without
emilmont 77:869cf507173a 14 modification, are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 - Redistributions of source code must retain the above copyright
emilmont 77:869cf507173a 16 notice, this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 - Redistributions in binary form must reproduce the above copyright
emilmont 77:869cf507173a 18 notice, this list of conditions and the following disclaimer in the
emilmont 77:869cf507173a 19 documentation and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 77:869cf507173a 21 to endorse or promote products derived from this software without
emilmont 77:869cf507173a 22 specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 77:869cf507173a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 77:869cf507173a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 77:869cf507173a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 77:869cf507173a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 77:869cf507173a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 77:869cf507173a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 77:869cf507173a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 77:869cf507173a 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 35 ---------------------------------------------------------------------------*/
emilmont 77:869cf507173a 36
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 #ifndef __CORE_CMINSTR_H
emilmont 77:869cf507173a 39 #define __CORE_CMINSTR_H
emilmont 77:869cf507173a 40
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 /* ########################## Core Instruction Access ######################### */
emilmont 77:869cf507173a 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
emilmont 77:869cf507173a 44 Access to dedicated instructions
emilmont 77:869cf507173a 45 @{
emilmont 77:869cf507173a 46 */
emilmont 77:869cf507173a 47
emilmont 77:869cf507173a 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 77:869cf507173a 49 /* ARM armcc specific functions */
emilmont 77:869cf507173a 50
emilmont 77:869cf507173a 51 #if (__ARMCC_VERSION < 400677)
emilmont 77:869cf507173a 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 77:869cf507173a 53 #endif
emilmont 77:869cf507173a 54
emilmont 77:869cf507173a 55
emilmont 77:869cf507173a 56 /** \brief No Operation
emilmont 77:869cf507173a 57
emilmont 77:869cf507173a 58 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 77:869cf507173a 59 */
emilmont 77:869cf507173a 60 #define __NOP __nop
emilmont 77:869cf507173a 61
emilmont 77:869cf507173a 62
emilmont 77:869cf507173a 63 /** \brief Wait For Interrupt
emilmont 77:869cf507173a 64
emilmont 77:869cf507173a 65 Wait For Interrupt is a hint instruction that suspends execution
emilmont 77:869cf507173a 66 until one of a number of events occurs.
emilmont 77:869cf507173a 67 */
emilmont 77:869cf507173a 68 #define __WFI __wfi
emilmont 77:869cf507173a 69
emilmont 77:869cf507173a 70
emilmont 77:869cf507173a 71 /** \brief Wait For Event
emilmont 77:869cf507173a 72
emilmont 77:869cf507173a 73 Wait For Event is a hint instruction that permits the processor to enter
emilmont 77:869cf507173a 74 a low-power state until one of a number of events occurs.
emilmont 77:869cf507173a 75 */
emilmont 77:869cf507173a 76 #define __WFE __wfe
emilmont 77:869cf507173a 77
emilmont 77:869cf507173a 78
emilmont 77:869cf507173a 79 /** \brief Send Event
emilmont 77:869cf507173a 80
emilmont 77:869cf507173a 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 77:869cf507173a 82 */
emilmont 77:869cf507173a 83 #define __SEV __sev
emilmont 77:869cf507173a 84
emilmont 77:869cf507173a 85
emilmont 77:869cf507173a 86 /** \brief Instruction Synchronization Barrier
emilmont 77:869cf507173a 87
emilmont 77:869cf507173a 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 77:869cf507173a 89 so that all instructions following the ISB are fetched from cache or
emilmont 77:869cf507173a 90 memory, after the instruction has been completed.
emilmont 77:869cf507173a 91 */
emilmont 77:869cf507173a 92 #define __ISB() __isb(0xF)
emilmont 77:869cf507173a 93
emilmont 77:869cf507173a 94
emilmont 77:869cf507173a 95 /** \brief Data Synchronization Barrier
emilmont 77:869cf507173a 96
emilmont 77:869cf507173a 97 This function acts as a special kind of Data Memory Barrier.
emilmont 77:869cf507173a 98 It completes when all explicit memory accesses before this instruction complete.
emilmont 77:869cf507173a 99 */
emilmont 77:869cf507173a 100 #define __DSB() __dsb(0xF)
emilmont 77:869cf507173a 101
emilmont 77:869cf507173a 102
emilmont 77:869cf507173a 103 /** \brief Data Memory Barrier
emilmont 77:869cf507173a 104
emilmont 77:869cf507173a 105 This function ensures the apparent order of the explicit memory operations before
emilmont 77:869cf507173a 106 and after the instruction, without ensuring their completion.
emilmont 77:869cf507173a 107 */
emilmont 77:869cf507173a 108 #define __DMB() __dmb(0xF)
emilmont 77:869cf507173a 109
emilmont 77:869cf507173a 110
emilmont 77:869cf507173a 111 /** \brief Reverse byte order (32 bit)
emilmont 77:869cf507173a 112
emilmont 77:869cf507173a 113 This function reverses the byte order in integer value.
emilmont 77:869cf507173a 114
emilmont 77:869cf507173a 115 \param [in] value Value to reverse
emilmont 77:869cf507173a 116 \return Reversed value
emilmont 77:869cf507173a 117 */
emilmont 77:869cf507173a 118 #define __REV __rev
emilmont 77:869cf507173a 119
emilmont 77:869cf507173a 120
emilmont 77:869cf507173a 121 /** \brief Reverse byte order (16 bit)
emilmont 77:869cf507173a 122
emilmont 77:869cf507173a 123 This function reverses the byte order in two unsigned short values.
emilmont 77:869cf507173a 124
emilmont 77:869cf507173a 125 \param [in] value Value to reverse
emilmont 77:869cf507173a 126 \return Reversed value
emilmont 77:869cf507173a 127 */
emilmont 77:869cf507173a 128 #ifndef __NO_EMBEDDED_ASM
emilmont 77:869cf507173a 129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
emilmont 77:869cf507173a 130 {
emilmont 77:869cf507173a 131 rev16 r0, r0
emilmont 77:869cf507173a 132 bx lr
emilmont 77:869cf507173a 133 }
emilmont 77:869cf507173a 134 #endif
emilmont 77:869cf507173a 135
emilmont 77:869cf507173a 136 /** \brief Reverse byte order in signed short value
emilmont 77:869cf507173a 137
emilmont 77:869cf507173a 138 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 77:869cf507173a 139
emilmont 77:869cf507173a 140 \param [in] value Value to reverse
emilmont 77:869cf507173a 141 \return Reversed value
emilmont 77:869cf507173a 142 */
emilmont 77:869cf507173a 143 #ifndef __NO_EMBEDDED_ASM
emilmont 77:869cf507173a 144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
emilmont 77:869cf507173a 145 {
emilmont 77:869cf507173a 146 revsh r0, r0
emilmont 77:869cf507173a 147 bx lr
emilmont 77:869cf507173a 148 }
emilmont 77:869cf507173a 149 #endif
emilmont 77:869cf507173a 150
emilmont 77:869cf507173a 151
emilmont 77:869cf507173a 152 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 77:869cf507173a 153
emilmont 77:869cf507173a 154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 77:869cf507173a 155
emilmont 77:869cf507173a 156 \param [in] value Value to rotate
emilmont 77:869cf507173a 157 \param [in] value Number of Bits to rotate
emilmont 77:869cf507173a 158 \return Rotated value
emilmont 77:869cf507173a 159 */
emilmont 77:869cf507173a 160 #define __ROR __ror
emilmont 77:869cf507173a 161
emilmont 77:869cf507173a 162
emilmont 77:869cf507173a 163 /** \brief Breakpoint
emilmont 77:869cf507173a 164
emilmont 77:869cf507173a 165 This function causes the processor to enter Debug state.
emilmont 77:869cf507173a 166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emilmont 77:869cf507173a 167
emilmont 77:869cf507173a 168 \param [in] value is ignored by the processor.
emilmont 77:869cf507173a 169 If required, a debugger can use it to store additional information about the breakpoint.
emilmont 77:869cf507173a 170 */
emilmont 77:869cf507173a 171 #define __BKPT(value) __breakpoint(value)
emilmont 77:869cf507173a 172
emilmont 77:869cf507173a 173
emilmont 77:869cf507173a 174 #if (__CORTEX_M >= 0x03)
emilmont 77:869cf507173a 175
emilmont 77:869cf507173a 176 /** \brief Reverse bit order of value
emilmont 77:869cf507173a 177
emilmont 77:869cf507173a 178 This function reverses the bit order of the given value.
emilmont 77:869cf507173a 179
emilmont 77:869cf507173a 180 \param [in] value Value to reverse
emilmont 77:869cf507173a 181 \return Reversed value
emilmont 77:869cf507173a 182 */
emilmont 77:869cf507173a 183 #define __RBIT __rbit
emilmont 77:869cf507173a 184
emilmont 77:869cf507173a 185
emilmont 77:869cf507173a 186 /** \brief LDR Exclusive (8 bit)
emilmont 77:869cf507173a 187
emilmont 77:869cf507173a 188 This function performs a exclusive LDR command for 8 bit value.
emilmont 77:869cf507173a 189
emilmont 77:869cf507173a 190 \param [in] ptr Pointer to data
emilmont 77:869cf507173a 191 \return value of type uint8_t at (*ptr)
emilmont 77:869cf507173a 192 */
emilmont 77:869cf507173a 193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
emilmont 77:869cf507173a 194
emilmont 77:869cf507173a 195
emilmont 77:869cf507173a 196 /** \brief LDR Exclusive (16 bit)
emilmont 77:869cf507173a 197
emilmont 77:869cf507173a 198 This function performs a exclusive LDR command for 16 bit values.
emilmont 77:869cf507173a 199
emilmont 77:869cf507173a 200 \param [in] ptr Pointer to data
emilmont 77:869cf507173a 201 \return value of type uint16_t at (*ptr)
emilmont 77:869cf507173a 202 */
emilmont 77:869cf507173a 203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
emilmont 77:869cf507173a 204
emilmont 77:869cf507173a 205
emilmont 77:869cf507173a 206 /** \brief LDR Exclusive (32 bit)
emilmont 77:869cf507173a 207
emilmont 77:869cf507173a 208 This function performs a exclusive LDR command for 32 bit values.
emilmont 77:869cf507173a 209
emilmont 77:869cf507173a 210 \param [in] ptr Pointer to data
emilmont 77:869cf507173a 211 \return value of type uint32_t at (*ptr)
emilmont 77:869cf507173a 212 */
emilmont 77:869cf507173a 213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
emilmont 77:869cf507173a 214
emilmont 77:869cf507173a 215
emilmont 77:869cf507173a 216 /** \brief STR Exclusive (8 bit)
emilmont 77:869cf507173a 217
emilmont 77:869cf507173a 218 This function performs a exclusive STR command for 8 bit values.
emilmont 77:869cf507173a 219
emilmont 77:869cf507173a 220 \param [in] value Value to store
emilmont 77:869cf507173a 221 \param [in] ptr Pointer to location
emilmont 77:869cf507173a 222 \return 0 Function succeeded
emilmont 77:869cf507173a 223 \return 1 Function failed
emilmont 77:869cf507173a 224 */
emilmont 77:869cf507173a 225 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 77:869cf507173a 226
emilmont 77:869cf507173a 227
emilmont 77:869cf507173a 228 /** \brief STR Exclusive (16 bit)
emilmont 77:869cf507173a 229
emilmont 77:869cf507173a 230 This function performs a exclusive STR command for 16 bit values.
emilmont 77:869cf507173a 231
emilmont 77:869cf507173a 232 \param [in] value Value to store
emilmont 77:869cf507173a 233 \param [in] ptr Pointer to location
emilmont 77:869cf507173a 234 \return 0 Function succeeded
emilmont 77:869cf507173a 235 \return 1 Function failed
emilmont 77:869cf507173a 236 */
emilmont 77:869cf507173a 237 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 77:869cf507173a 238
emilmont 77:869cf507173a 239
emilmont 77:869cf507173a 240 /** \brief STR Exclusive (32 bit)
emilmont 77:869cf507173a 241
emilmont 77:869cf507173a 242 This function performs a exclusive STR command for 32 bit values.
emilmont 77:869cf507173a 243
emilmont 77:869cf507173a 244 \param [in] value Value to store
emilmont 77:869cf507173a 245 \param [in] ptr Pointer to location
emilmont 77:869cf507173a 246 \return 0 Function succeeded
emilmont 77:869cf507173a 247 \return 1 Function failed
emilmont 77:869cf507173a 248 */
emilmont 77:869cf507173a 249 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 77:869cf507173a 250
emilmont 77:869cf507173a 251
emilmont 77:869cf507173a 252 /** \brief Remove the exclusive lock
emilmont 77:869cf507173a 253
emilmont 77:869cf507173a 254 This function removes the exclusive lock which is created by LDREX.
emilmont 77:869cf507173a 255
emilmont 77:869cf507173a 256 */
emilmont 77:869cf507173a 257 #define __CLREX __clrex
emilmont 77:869cf507173a 258
emilmont 77:869cf507173a 259
emilmont 77:869cf507173a 260 /** \brief Signed Saturate
emilmont 77:869cf507173a 261
emilmont 77:869cf507173a 262 This function saturates a signed value.
emilmont 77:869cf507173a 263
emilmont 77:869cf507173a 264 \param [in] value Value to be saturated
emilmont 77:869cf507173a 265 \param [in] sat Bit position to saturate to (1..32)
emilmont 77:869cf507173a 266 \return Saturated value
emilmont 77:869cf507173a 267 */
emilmont 77:869cf507173a 268 #define __SSAT __ssat
emilmont 77:869cf507173a 269
emilmont 77:869cf507173a 270
emilmont 77:869cf507173a 271 /** \brief Unsigned Saturate
emilmont 77:869cf507173a 272
emilmont 77:869cf507173a 273 This function saturates an unsigned value.
emilmont 77:869cf507173a 274
emilmont 77:869cf507173a 275 \param [in] value Value to be saturated
emilmont 77:869cf507173a 276 \param [in] sat Bit position to saturate to (0..31)
emilmont 77:869cf507173a 277 \return Saturated value
emilmont 77:869cf507173a 278 */
emilmont 77:869cf507173a 279 #define __USAT __usat
emilmont 77:869cf507173a 280
emilmont 77:869cf507173a 281
emilmont 77:869cf507173a 282 /** \brief Count leading zeros
emilmont 77:869cf507173a 283
emilmont 77:869cf507173a 284 This function counts the number of leading zeros of a data value.
emilmont 77:869cf507173a 285
emilmont 77:869cf507173a 286 \param [in] value Value to count the leading zeros
emilmont 77:869cf507173a 287 \return number of leading zeros in value
emilmont 77:869cf507173a 288 */
emilmont 77:869cf507173a 289 #define __CLZ __clz
emilmont 77:869cf507173a 290
emilmont 77:869cf507173a 291 #endif /* (__CORTEX_M >= 0x03) */
emilmont 77:869cf507173a 292
emilmont 77:869cf507173a 293
emilmont 77:869cf507173a 294
emilmont 77:869cf507173a 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 77:869cf507173a 296 /* IAR iccarm specific functions */
emilmont 77:869cf507173a 297
emilmont 77:869cf507173a 298 #include <cmsis_iar.h>
emilmont 77:869cf507173a 299
emilmont 77:869cf507173a 300
emilmont 77:869cf507173a 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 77:869cf507173a 302 /* TI CCS specific functions */
emilmont 77:869cf507173a 303
emilmont 77:869cf507173a 304 #include <cmsis_ccs.h>
emilmont 77:869cf507173a 305
emilmont 77:869cf507173a 306
emilmont 77:869cf507173a 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 77:869cf507173a 308 /* GNU gcc specific functions */
emilmont 77:869cf507173a 309
emilmont 77:869cf507173a 310 /* Define macros for porting to both thumb1 and thumb2.
emilmont 77:869cf507173a 311 * For thumb1, use low register (r0-r7), specified by constrant "l"
emilmont 77:869cf507173a 312 * Otherwise, use general registers, specified by constrant "r" */
emilmont 77:869cf507173a 313 #if defined (__thumb__) && !defined (__thumb2__)
emilmont 77:869cf507173a 314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
emilmont 77:869cf507173a 315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
emilmont 77:869cf507173a 316 #else
emilmont 77:869cf507173a 317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
emilmont 77:869cf507173a 318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
emilmont 77:869cf507173a 319 #endif
emilmont 77:869cf507173a 320
emilmont 77:869cf507173a 321 /** \brief No Operation
emilmont 77:869cf507173a 322
emilmont 77:869cf507173a 323 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 77:869cf507173a 324 */
emilmont 77:869cf507173a 325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
emilmont 77:869cf507173a 326 {
emilmont 77:869cf507173a 327 __ASM volatile ("nop");
emilmont 77:869cf507173a 328 }
emilmont 77:869cf507173a 329
emilmont 77:869cf507173a 330
emilmont 77:869cf507173a 331 /** \brief Wait For Interrupt
emilmont 77:869cf507173a 332
emilmont 77:869cf507173a 333 Wait For Interrupt is a hint instruction that suspends execution
emilmont 77:869cf507173a 334 until one of a number of events occurs.
emilmont 77:869cf507173a 335 */
emilmont 77:869cf507173a 336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
emilmont 77:869cf507173a 337 {
emilmont 77:869cf507173a 338 __ASM volatile ("wfi");
emilmont 77:869cf507173a 339 }
emilmont 77:869cf507173a 340
emilmont 77:869cf507173a 341
emilmont 77:869cf507173a 342 /** \brief Wait For Event
emilmont 77:869cf507173a 343
emilmont 77:869cf507173a 344 Wait For Event is a hint instruction that permits the processor to enter
emilmont 77:869cf507173a 345 a low-power state until one of a number of events occurs.
emilmont 77:869cf507173a 346 */
emilmont 77:869cf507173a 347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
emilmont 77:869cf507173a 348 {
emilmont 77:869cf507173a 349 __ASM volatile ("wfe");
emilmont 77:869cf507173a 350 }
emilmont 77:869cf507173a 351
emilmont 77:869cf507173a 352
emilmont 77:869cf507173a 353 /** \brief Send Event
emilmont 77:869cf507173a 354
emilmont 77:869cf507173a 355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 77:869cf507173a 356 */
emilmont 77:869cf507173a 357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
emilmont 77:869cf507173a 358 {
emilmont 77:869cf507173a 359 __ASM volatile ("sev");
emilmont 77:869cf507173a 360 }
emilmont 77:869cf507173a 361
emilmont 77:869cf507173a 362
emilmont 77:869cf507173a 363 /** \brief Instruction Synchronization Barrier
emilmont 77:869cf507173a 364
emilmont 77:869cf507173a 365 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 77:869cf507173a 366 so that all instructions following the ISB are fetched from cache or
emilmont 77:869cf507173a 367 memory, after the instruction has been completed.
emilmont 77:869cf507173a 368 */
emilmont 77:869cf507173a 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
emilmont 77:869cf507173a 370 {
emilmont 77:869cf507173a 371 __ASM volatile ("isb");
emilmont 77:869cf507173a 372 }
emilmont 77:869cf507173a 373
emilmont 77:869cf507173a 374
emilmont 77:869cf507173a 375 /** \brief Data Synchronization Barrier
emilmont 77:869cf507173a 376
emilmont 77:869cf507173a 377 This function acts as a special kind of Data Memory Barrier.
emilmont 77:869cf507173a 378 It completes when all explicit memory accesses before this instruction complete.
emilmont 77:869cf507173a 379 */
emilmont 77:869cf507173a 380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
emilmont 77:869cf507173a 381 {
emilmont 77:869cf507173a 382 __ASM volatile ("dsb");
emilmont 77:869cf507173a 383 }
emilmont 77:869cf507173a 384
emilmont 77:869cf507173a 385
emilmont 77:869cf507173a 386 /** \brief Data Memory Barrier
emilmont 77:869cf507173a 387
emilmont 77:869cf507173a 388 This function ensures the apparent order of the explicit memory operations before
emilmont 77:869cf507173a 389 and after the instruction, without ensuring their completion.
emilmont 77:869cf507173a 390 */
emilmont 77:869cf507173a 391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
emilmont 77:869cf507173a 392 {
emilmont 77:869cf507173a 393 __ASM volatile ("dmb");
emilmont 77:869cf507173a 394 }
emilmont 77:869cf507173a 395
emilmont 77:869cf507173a 396
emilmont 77:869cf507173a 397 /** \brief Reverse byte order (32 bit)
emilmont 77:869cf507173a 398
emilmont 77:869cf507173a 399 This function reverses the byte order in integer value.
emilmont 77:869cf507173a 400
emilmont 77:869cf507173a 401 \param [in] value Value to reverse
emilmont 77:869cf507173a 402 \return Reversed value
emilmont 77:869cf507173a 403 */
emilmont 77:869cf507173a 404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
emilmont 77:869cf507173a 405 {
emilmont 77:869cf507173a 406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
emilmont 77:869cf507173a 407 return __builtin_bswap32(value);
emilmont 77:869cf507173a 408 #else
emilmont 77:869cf507173a 409 uint32_t result;
emilmont 77:869cf507173a 410
emilmont 77:869cf507173a 411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 77:869cf507173a 412 return(result);
emilmont 77:869cf507173a 413 #endif
emilmont 77:869cf507173a 414 }
emilmont 77:869cf507173a 415
emilmont 77:869cf507173a 416
emilmont 77:869cf507173a 417 /** \brief Reverse byte order (16 bit)
emilmont 77:869cf507173a 418
emilmont 77:869cf507173a 419 This function reverses the byte order in two unsigned short values.
emilmont 77:869cf507173a 420
emilmont 77:869cf507173a 421 \param [in] value Value to reverse
emilmont 77:869cf507173a 422 \return Reversed value
emilmont 77:869cf507173a 423 */
emilmont 77:869cf507173a 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
emilmont 77:869cf507173a 425 {
emilmont 77:869cf507173a 426 uint32_t result;
emilmont 77:869cf507173a 427
emilmont 77:869cf507173a 428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 77:869cf507173a 429 return(result);
emilmont 77:869cf507173a 430 }
emilmont 77:869cf507173a 431
emilmont 77:869cf507173a 432
emilmont 77:869cf507173a 433 /** \brief Reverse byte order in signed short value
emilmont 77:869cf507173a 434
emilmont 77:869cf507173a 435 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 77:869cf507173a 436
emilmont 77:869cf507173a 437 \param [in] value Value to reverse
emilmont 77:869cf507173a 438 \return Reversed value
emilmont 77:869cf507173a 439 */
emilmont 77:869cf507173a 440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
emilmont 77:869cf507173a 441 {
emilmont 77:869cf507173a 442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
emilmont 77:869cf507173a 443 return (short)__builtin_bswap16(value);
emilmont 77:869cf507173a 444 #else
emilmont 77:869cf507173a 445 uint32_t result;
emilmont 77:869cf507173a 446
emilmont 77:869cf507173a 447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
emilmont 77:869cf507173a 448 return(result);
emilmont 77:869cf507173a 449 #endif
emilmont 77:869cf507173a 450 }
emilmont 77:869cf507173a 451
emilmont 77:869cf507173a 452
emilmont 77:869cf507173a 453 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 77:869cf507173a 454
emilmont 77:869cf507173a 455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 77:869cf507173a 456
emilmont 77:869cf507173a 457 \param [in] value Value to rotate
emilmont 77:869cf507173a 458 \param [in] value Number of Bits to rotate
emilmont 77:869cf507173a 459 \return Rotated value
emilmont 77:869cf507173a 460 */
emilmont 77:869cf507173a 461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
emilmont 77:869cf507173a 462 {
emilmont 77:869cf507173a 463 return (op1 >> op2) | (op1 << (32 - op2));
emilmont 77:869cf507173a 464 }
emilmont 77:869cf507173a 465
emilmont 77:869cf507173a 466
emilmont 77:869cf507173a 467 /** \brief Breakpoint
emilmont 77:869cf507173a 468
emilmont 77:869cf507173a 469 This function causes the processor to enter Debug state.
emilmont 77:869cf507173a 470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emilmont 77:869cf507173a 471
emilmont 77:869cf507173a 472 \param [in] value is ignored by the processor.
emilmont 77:869cf507173a 473 If required, a debugger can use it to store additional information about the breakpoint.
emilmont 77:869cf507173a 474 */
emilmont 77:869cf507173a 475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
emilmont 77:869cf507173a 476
emilmont 77:869cf507173a 477
emilmont 77:869cf507173a 478 #if (__CORTEX_M >= 0x03)
emilmont 77:869cf507173a 479
emilmont 77:869cf507173a 480 /** \brief Reverse bit order of value
emilmont 77:869cf507173a 481
emilmont 77:869cf507173a 482 This function reverses the bit order of the given value.
emilmont 77:869cf507173a 483
emilmont 77:869cf507173a 484 \param [in] value Value to reverse
emilmont 77:869cf507173a 485 \return Reversed value
emilmont 77:869cf507173a 486 */
emilmont 77:869cf507173a 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
emilmont 77:869cf507173a 488 {
emilmont 77:869cf507173a 489 uint32_t result;
emilmont 77:869cf507173a 490
emilmont 77:869cf507173a 491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
emilmont 77:869cf507173a 492 return(result);
emilmont 77:869cf507173a 493 }
emilmont 77:869cf507173a 494
emilmont 77:869cf507173a 495
emilmont 77:869cf507173a 496 /** \brief LDR Exclusive (8 bit)
emilmont 77:869cf507173a 497
emilmont 77:869cf507173a 498 This function performs a exclusive LDR command for 8 bit value.
emilmont 77:869cf507173a 499
emilmont 77:869cf507173a 500 \param [in] ptr Pointer to data
emilmont 77:869cf507173a 501 \return value of type uint8_t at (*ptr)
emilmont 77:869cf507173a 502 */
emilmont 77:869cf507173a 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
emilmont 77:869cf507173a 504 {
emilmont 77:869cf507173a 505 uint32_t result;
emilmont 77:869cf507173a 506
emilmont 77:869cf507173a 507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
emilmont 77:869cf507173a 508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
emilmont 77:869cf507173a 509 #else
emilmont 77:869cf507173a 510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
emilmont 77:869cf507173a 511 accepted by assembler. So has to use following less efficient pattern.
emilmont 77:869cf507173a 512 */
emilmont 77:869cf507173a 513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
emilmont 77:869cf507173a 514 #endif
emilmont 77:869cf507173a 515 return(result);
emilmont 77:869cf507173a 516 }
emilmont 77:869cf507173a 517
emilmont 77:869cf507173a 518
emilmont 77:869cf507173a 519 /** \brief LDR Exclusive (16 bit)
emilmont 77:869cf507173a 520
emilmont 77:869cf507173a 521 This function performs a exclusive LDR command for 16 bit values.
emilmont 77:869cf507173a 522
emilmont 77:869cf507173a 523 \param [in] ptr Pointer to data
emilmont 77:869cf507173a 524 \return value of type uint16_t at (*ptr)
emilmont 77:869cf507173a 525 */
emilmont 77:869cf507173a 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
emilmont 77:869cf507173a 527 {
emilmont 77:869cf507173a 528 uint32_t result;
emilmont 77:869cf507173a 529
emilmont 77:869cf507173a 530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
emilmont 77:869cf507173a 531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
emilmont 77:869cf507173a 532 #else
emilmont 77:869cf507173a 533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
emilmont 77:869cf507173a 534 accepted by assembler. So has to use following less efficient pattern.
emilmont 77:869cf507173a 535 */
emilmont 77:869cf507173a 536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
emilmont 77:869cf507173a 537 #endif
emilmont 77:869cf507173a 538 return(result);
emilmont 77:869cf507173a 539 }
emilmont 77:869cf507173a 540
emilmont 77:869cf507173a 541
emilmont 77:869cf507173a 542 /** \brief LDR Exclusive (32 bit)
emilmont 77:869cf507173a 543
emilmont 77:869cf507173a 544 This function performs a exclusive LDR command for 32 bit values.
emilmont 77:869cf507173a 545
emilmont 77:869cf507173a 546 \param [in] ptr Pointer to data
emilmont 77:869cf507173a 547 \return value of type uint32_t at (*ptr)
emilmont 77:869cf507173a 548 */
emilmont 77:869cf507173a 549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
emilmont 77:869cf507173a 550 {
emilmont 77:869cf507173a 551 uint32_t result;
emilmont 77:869cf507173a 552
emilmont 77:869cf507173a 553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
emilmont 77:869cf507173a 554 return(result);
emilmont 77:869cf507173a 555 }
emilmont 77:869cf507173a 556
emilmont 77:869cf507173a 557
emilmont 77:869cf507173a 558 /** \brief STR Exclusive (8 bit)
emilmont 77:869cf507173a 559
emilmont 77:869cf507173a 560 This function performs a exclusive STR command for 8 bit values.
emilmont 77:869cf507173a 561
emilmont 77:869cf507173a 562 \param [in] value Value to store
emilmont 77:869cf507173a 563 \param [in] ptr Pointer to location
emilmont 77:869cf507173a 564 \return 0 Function succeeded
emilmont 77:869cf507173a 565 \return 1 Function failed
emilmont 77:869cf507173a 566 */
emilmont 77:869cf507173a 567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
emilmont 77:869cf507173a 568 {
emilmont 77:869cf507173a 569 uint32_t result;
emilmont 77:869cf507173a 570
emilmont 77:869cf507173a 571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
emilmont 77:869cf507173a 572 return(result);
emilmont 77:869cf507173a 573 }
emilmont 77:869cf507173a 574
emilmont 77:869cf507173a 575
emilmont 77:869cf507173a 576 /** \brief STR Exclusive (16 bit)
emilmont 77:869cf507173a 577
emilmont 77:869cf507173a 578 This function performs a exclusive STR command for 16 bit values.
emilmont 77:869cf507173a 579
emilmont 77:869cf507173a 580 \param [in] value Value to store
emilmont 77:869cf507173a 581 \param [in] ptr Pointer to location
emilmont 77:869cf507173a 582 \return 0 Function succeeded
emilmont 77:869cf507173a 583 \return 1 Function failed
emilmont 77:869cf507173a 584 */
emilmont 77:869cf507173a 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
emilmont 77:869cf507173a 586 {
emilmont 77:869cf507173a 587 uint32_t result;
emilmont 77:869cf507173a 588
emilmont 77:869cf507173a 589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
emilmont 77:869cf507173a 590 return(result);
emilmont 77:869cf507173a 591 }
emilmont 77:869cf507173a 592
emilmont 77:869cf507173a 593
emilmont 77:869cf507173a 594 /** \brief STR Exclusive (32 bit)
emilmont 77:869cf507173a 595
emilmont 77:869cf507173a 596 This function performs a exclusive STR command for 32 bit values.
emilmont 77:869cf507173a 597
emilmont 77:869cf507173a 598 \param [in] value Value to store
emilmont 77:869cf507173a 599 \param [in] ptr Pointer to location
emilmont 77:869cf507173a 600 \return 0 Function succeeded
emilmont 77:869cf507173a 601 \return 1 Function failed
emilmont 77:869cf507173a 602 */
emilmont 77:869cf507173a 603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
emilmont 77:869cf507173a 604 {
emilmont 77:869cf507173a 605 uint32_t result;
emilmont 77:869cf507173a 606
emilmont 77:869cf507173a 607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
emilmont 77:869cf507173a 608 return(result);
emilmont 77:869cf507173a 609 }
emilmont 77:869cf507173a 610
emilmont 77:869cf507173a 611
emilmont 77:869cf507173a 612 /** \brief Remove the exclusive lock
emilmont 77:869cf507173a 613
emilmont 77:869cf507173a 614 This function removes the exclusive lock which is created by LDREX.
emilmont 77:869cf507173a 615
emilmont 77:869cf507173a 616 */
emilmont 77:869cf507173a 617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
emilmont 77:869cf507173a 618 {
emilmont 77:869cf507173a 619 __ASM volatile ("clrex" ::: "memory");
emilmont 77:869cf507173a 620 }
emilmont 77:869cf507173a 621
emilmont 77:869cf507173a 622
emilmont 77:869cf507173a 623 /** \brief Signed Saturate
emilmont 77:869cf507173a 624
emilmont 77:869cf507173a 625 This function saturates a signed value.
emilmont 77:869cf507173a 626
emilmont 77:869cf507173a 627 \param [in] value Value to be saturated
emilmont 77:869cf507173a 628 \param [in] sat Bit position to saturate to (1..32)
emilmont 77:869cf507173a 629 \return Saturated value
emilmont 77:869cf507173a 630 */
emilmont 77:869cf507173a 631 #define __SSAT(ARG1,ARG2) \
emilmont 77:869cf507173a 632 ({ \
emilmont 77:869cf507173a 633 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 77:869cf507173a 634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 77:869cf507173a 635 __RES; \
emilmont 77:869cf507173a 636 })
emilmont 77:869cf507173a 637
emilmont 77:869cf507173a 638
emilmont 77:869cf507173a 639 /** \brief Unsigned Saturate
emilmont 77:869cf507173a 640
emilmont 77:869cf507173a 641 This function saturates an unsigned value.
emilmont 77:869cf507173a 642
emilmont 77:869cf507173a 643 \param [in] value Value to be saturated
emilmont 77:869cf507173a 644 \param [in] sat Bit position to saturate to (0..31)
emilmont 77:869cf507173a 645 \return Saturated value
emilmont 77:869cf507173a 646 */
emilmont 77:869cf507173a 647 #define __USAT(ARG1,ARG2) \
emilmont 77:869cf507173a 648 ({ \
emilmont 77:869cf507173a 649 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 77:869cf507173a 650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 77:869cf507173a 651 __RES; \
emilmont 77:869cf507173a 652 })
emilmont 77:869cf507173a 653
emilmont 77:869cf507173a 654
emilmont 77:869cf507173a 655 /** \brief Count leading zeros
emilmont 77:869cf507173a 656
emilmont 77:869cf507173a 657 This function counts the number of leading zeros of a data value.
emilmont 77:869cf507173a 658
emilmont 77:869cf507173a 659 \param [in] value Value to count the leading zeros
emilmont 77:869cf507173a 660 \return number of leading zeros in value
emilmont 77:869cf507173a 661 */
emilmont 77:869cf507173a 662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
emilmont 77:869cf507173a 663 {
emilmont 77:869cf507173a 664 uint32_t result;
emilmont 77:869cf507173a 665
emilmont 77:869cf507173a 666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
emilmont 77:869cf507173a 667 return(result);
emilmont 77:869cf507173a 668 }
emilmont 77:869cf507173a 669
emilmont 77:869cf507173a 670 #endif /* (__CORTEX_M >= 0x03) */
emilmont 77:869cf507173a 671
emilmont 77:869cf507173a 672
emilmont 77:869cf507173a 673
emilmont 77:869cf507173a 674
emilmont 77:869cf507173a 675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 77:869cf507173a 676 /* TASKING carm specific functions */
emilmont 77:869cf507173a 677
emilmont 77:869cf507173a 678 /*
emilmont 77:869cf507173a 679 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 77:869cf507173a 680 * Please use "carm -?i" to get an up to date list of all intrinsics,
emilmont 77:869cf507173a 681 * Including the CMSIS ones.
emilmont 77:869cf507173a 682 */
emilmont 77:869cf507173a 683
emilmont 77:869cf507173a 684 #endif
emilmont 77:869cf507173a 685
emilmont 77:869cf507173a 686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
emilmont 77:869cf507173a 687
emilmont 77:869cf507173a 688 #endif /* __CORE_CMINSTR_H */