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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F401RE/core_cmFunc.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Parent:
77:869cf507173a
Child:
110:165afa46840b
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**************************************************************************//**
emilmont 77:869cf507173a 2 * @file core_cmFunc.h
emilmont 77:869cf507173a 3 * @brief CMSIS Cortex-M Core Function Access Header File
emilmont 77:869cf507173a 4 * @version V3.20
emilmont 77:869cf507173a 5 * @date 25. February 2013
emilmont 77:869cf507173a 6 *
emilmont 77:869cf507173a 7 * @note
emilmont 77:869cf507173a 8 *
emilmont 77:869cf507173a 9 ******************************************************************************/
emilmont 77:869cf507173a 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
emilmont 77:869cf507173a 11
emilmont 77:869cf507173a 12 All rights reserved.
emilmont 77:869cf507173a 13 Redistribution and use in source and binary forms, with or without
emilmont 77:869cf507173a 14 modification, are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 - Redistributions of source code must retain the above copyright
emilmont 77:869cf507173a 16 notice, this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 - Redistributions in binary form must reproduce the above copyright
emilmont 77:869cf507173a 18 notice, this list of conditions and the following disclaimer in the
emilmont 77:869cf507173a 19 documentation and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 77:869cf507173a 21 to endorse or promote products derived from this software without
emilmont 77:869cf507173a 22 specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 77:869cf507173a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 77:869cf507173a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 77:869cf507173a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 77:869cf507173a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 77:869cf507173a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 77:869cf507173a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 77:869cf507173a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 77:869cf507173a 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 35 ---------------------------------------------------------------------------*/
emilmont 77:869cf507173a 36
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 #ifndef __CORE_CMFUNC_H
emilmont 77:869cf507173a 39 #define __CORE_CMFUNC_H
emilmont 77:869cf507173a 40
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 /* ########################### Core Function Access ########################### */
emilmont 77:869cf507173a 43 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 77:869cf507173a 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
emilmont 77:869cf507173a 45 @{
emilmont 77:869cf507173a 46 */
emilmont 77:869cf507173a 47
emilmont 77:869cf507173a 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 77:869cf507173a 49 /* ARM armcc specific functions */
emilmont 77:869cf507173a 50
emilmont 77:869cf507173a 51 #if (__ARMCC_VERSION < 400677)
emilmont 77:869cf507173a 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 77:869cf507173a 53 #endif
emilmont 77:869cf507173a 54
emilmont 77:869cf507173a 55 /* intrinsic void __enable_irq(); */
emilmont 77:869cf507173a 56 /* intrinsic void __disable_irq(); */
emilmont 77:869cf507173a 57
emilmont 77:869cf507173a 58 /** \brief Get Control Register
emilmont 77:869cf507173a 59
emilmont 77:869cf507173a 60 This function returns the content of the Control Register.
emilmont 77:869cf507173a 61
emilmont 77:869cf507173a 62 \return Control Register value
emilmont 77:869cf507173a 63 */
emilmont 77:869cf507173a 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 77:869cf507173a 65 {
emilmont 77:869cf507173a 66 register uint32_t __regControl __ASM("control");
emilmont 77:869cf507173a 67 return(__regControl);
emilmont 77:869cf507173a 68 }
emilmont 77:869cf507173a 69
emilmont 77:869cf507173a 70
emilmont 77:869cf507173a 71 /** \brief Set Control Register
emilmont 77:869cf507173a 72
emilmont 77:869cf507173a 73 This function writes the given value to the Control Register.
emilmont 77:869cf507173a 74
emilmont 77:869cf507173a 75 \param [in] control Control Register value to set
emilmont 77:869cf507173a 76 */
emilmont 77:869cf507173a 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 77:869cf507173a 78 {
emilmont 77:869cf507173a 79 register uint32_t __regControl __ASM("control");
emilmont 77:869cf507173a 80 __regControl = control;
emilmont 77:869cf507173a 81 }
emilmont 77:869cf507173a 82
emilmont 77:869cf507173a 83
emilmont 77:869cf507173a 84 /** \brief Get IPSR Register
emilmont 77:869cf507173a 85
emilmont 77:869cf507173a 86 This function returns the content of the IPSR Register.
emilmont 77:869cf507173a 87
emilmont 77:869cf507173a 88 \return IPSR Register value
emilmont 77:869cf507173a 89 */
emilmont 77:869cf507173a 90 __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 77:869cf507173a 91 {
emilmont 77:869cf507173a 92 register uint32_t __regIPSR __ASM("ipsr");
emilmont 77:869cf507173a 93 return(__regIPSR);
emilmont 77:869cf507173a 94 }
emilmont 77:869cf507173a 95
emilmont 77:869cf507173a 96
emilmont 77:869cf507173a 97 /** \brief Get APSR Register
emilmont 77:869cf507173a 98
emilmont 77:869cf507173a 99 This function returns the content of the APSR Register.
emilmont 77:869cf507173a 100
emilmont 77:869cf507173a 101 \return APSR Register value
emilmont 77:869cf507173a 102 */
emilmont 77:869cf507173a 103 __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 77:869cf507173a 104 {
emilmont 77:869cf507173a 105 register uint32_t __regAPSR __ASM("apsr");
emilmont 77:869cf507173a 106 return(__regAPSR);
emilmont 77:869cf507173a 107 }
emilmont 77:869cf507173a 108
emilmont 77:869cf507173a 109
emilmont 77:869cf507173a 110 /** \brief Get xPSR Register
emilmont 77:869cf507173a 111
emilmont 77:869cf507173a 112 This function returns the content of the xPSR Register.
emilmont 77:869cf507173a 113
emilmont 77:869cf507173a 114 \return xPSR Register value
emilmont 77:869cf507173a 115 */
emilmont 77:869cf507173a 116 __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 77:869cf507173a 117 {
emilmont 77:869cf507173a 118 register uint32_t __regXPSR __ASM("xpsr");
emilmont 77:869cf507173a 119 return(__regXPSR);
emilmont 77:869cf507173a 120 }
emilmont 77:869cf507173a 121
emilmont 77:869cf507173a 122
emilmont 77:869cf507173a 123 /** \brief Get Process Stack Pointer
emilmont 77:869cf507173a 124
emilmont 77:869cf507173a 125 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 77:869cf507173a 126
emilmont 77:869cf507173a 127 \return PSP Register value
emilmont 77:869cf507173a 128 */
emilmont 77:869cf507173a 129 __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 77:869cf507173a 130 {
emilmont 77:869cf507173a 131 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 77:869cf507173a 132 return(__regProcessStackPointer);
emilmont 77:869cf507173a 133 }
emilmont 77:869cf507173a 134
emilmont 77:869cf507173a 135
emilmont 77:869cf507173a 136 /** \brief Set Process Stack Pointer
emilmont 77:869cf507173a 137
emilmont 77:869cf507173a 138 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 77:869cf507173a 139
emilmont 77:869cf507173a 140 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 77:869cf507173a 141 */
emilmont 77:869cf507173a 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 77:869cf507173a 143 {
emilmont 77:869cf507173a 144 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 77:869cf507173a 145 __regProcessStackPointer = topOfProcStack;
emilmont 77:869cf507173a 146 }
emilmont 77:869cf507173a 147
emilmont 77:869cf507173a 148
emilmont 77:869cf507173a 149 /** \brief Get Main Stack Pointer
emilmont 77:869cf507173a 150
emilmont 77:869cf507173a 151 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 77:869cf507173a 152
emilmont 77:869cf507173a 153 \return MSP Register value
emilmont 77:869cf507173a 154 */
emilmont 77:869cf507173a 155 __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 77:869cf507173a 156 {
emilmont 77:869cf507173a 157 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 77:869cf507173a 158 return(__regMainStackPointer);
emilmont 77:869cf507173a 159 }
emilmont 77:869cf507173a 160
emilmont 77:869cf507173a 161
emilmont 77:869cf507173a 162 /** \brief Set Main Stack Pointer
emilmont 77:869cf507173a 163
emilmont 77:869cf507173a 164 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 77:869cf507173a 165
emilmont 77:869cf507173a 166 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 77:869cf507173a 167 */
emilmont 77:869cf507173a 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 77:869cf507173a 169 {
emilmont 77:869cf507173a 170 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 77:869cf507173a 171 __regMainStackPointer = topOfMainStack;
emilmont 77:869cf507173a 172 }
emilmont 77:869cf507173a 173
emilmont 77:869cf507173a 174
emilmont 77:869cf507173a 175 /** \brief Get Priority Mask
emilmont 77:869cf507173a 176
emilmont 77:869cf507173a 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 77:869cf507173a 178
emilmont 77:869cf507173a 179 \return Priority Mask value
emilmont 77:869cf507173a 180 */
emilmont 77:869cf507173a 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 77:869cf507173a 182 {
emilmont 77:869cf507173a 183 register uint32_t __regPriMask __ASM("primask");
emilmont 77:869cf507173a 184 return(__regPriMask);
emilmont 77:869cf507173a 185 }
emilmont 77:869cf507173a 186
emilmont 77:869cf507173a 187
emilmont 77:869cf507173a 188 /** \brief Set Priority Mask
emilmont 77:869cf507173a 189
emilmont 77:869cf507173a 190 This function assigns the given value to the Priority Mask Register.
emilmont 77:869cf507173a 191
emilmont 77:869cf507173a 192 \param [in] priMask Priority Mask
emilmont 77:869cf507173a 193 */
emilmont 77:869cf507173a 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 77:869cf507173a 195 {
emilmont 77:869cf507173a 196 register uint32_t __regPriMask __ASM("primask");
emilmont 77:869cf507173a 197 __regPriMask = (priMask);
emilmont 77:869cf507173a 198 }
emilmont 77:869cf507173a 199
emilmont 77:869cf507173a 200
emilmont 77:869cf507173a 201 #if (__CORTEX_M >= 0x03)
emilmont 77:869cf507173a 202
emilmont 77:869cf507173a 203 /** \brief Enable FIQ
emilmont 77:869cf507173a 204
emilmont 77:869cf507173a 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 77:869cf507173a 206 Can only be executed in Privileged modes.
emilmont 77:869cf507173a 207 */
emilmont 77:869cf507173a 208 #define __enable_fault_irq __enable_fiq
emilmont 77:869cf507173a 209
emilmont 77:869cf507173a 210
emilmont 77:869cf507173a 211 /** \brief Disable FIQ
emilmont 77:869cf507173a 212
emilmont 77:869cf507173a 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 77:869cf507173a 214 Can only be executed in Privileged modes.
emilmont 77:869cf507173a 215 */
emilmont 77:869cf507173a 216 #define __disable_fault_irq __disable_fiq
emilmont 77:869cf507173a 217
emilmont 77:869cf507173a 218
emilmont 77:869cf507173a 219 /** \brief Get Base Priority
emilmont 77:869cf507173a 220
emilmont 77:869cf507173a 221 This function returns the current value of the Base Priority register.
emilmont 77:869cf507173a 222
emilmont 77:869cf507173a 223 \return Base Priority register value
emilmont 77:869cf507173a 224 */
emilmont 77:869cf507173a 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 77:869cf507173a 226 {
emilmont 77:869cf507173a 227 register uint32_t __regBasePri __ASM("basepri");
emilmont 77:869cf507173a 228 return(__regBasePri);
emilmont 77:869cf507173a 229 }
emilmont 77:869cf507173a 230
emilmont 77:869cf507173a 231
emilmont 77:869cf507173a 232 /** \brief Set Base Priority
emilmont 77:869cf507173a 233
emilmont 77:869cf507173a 234 This function assigns the given value to the Base Priority register.
emilmont 77:869cf507173a 235
emilmont 77:869cf507173a 236 \param [in] basePri Base Priority value to set
emilmont 77:869cf507173a 237 */
emilmont 77:869cf507173a 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
emilmont 77:869cf507173a 239 {
emilmont 77:869cf507173a 240 register uint32_t __regBasePri __ASM("basepri");
emilmont 77:869cf507173a 241 __regBasePri = (basePri & 0xff);
emilmont 77:869cf507173a 242 }
emilmont 77:869cf507173a 243
emilmont 77:869cf507173a 244
emilmont 77:869cf507173a 245 /** \brief Get Fault Mask
emilmont 77:869cf507173a 246
emilmont 77:869cf507173a 247 This function returns the current value of the Fault Mask register.
emilmont 77:869cf507173a 248
emilmont 77:869cf507173a 249 \return Fault Mask register value
emilmont 77:869cf507173a 250 */
emilmont 77:869cf507173a 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 77:869cf507173a 252 {
emilmont 77:869cf507173a 253 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 77:869cf507173a 254 return(__regFaultMask);
emilmont 77:869cf507173a 255 }
emilmont 77:869cf507173a 256
emilmont 77:869cf507173a 257
emilmont 77:869cf507173a 258 /** \brief Set Fault Mask
emilmont 77:869cf507173a 259
emilmont 77:869cf507173a 260 This function assigns the given value to the Fault Mask register.
emilmont 77:869cf507173a 261
emilmont 77:869cf507173a 262 \param [in] faultMask Fault Mask value to set
emilmont 77:869cf507173a 263 */
emilmont 77:869cf507173a 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 77:869cf507173a 265 {
emilmont 77:869cf507173a 266 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 77:869cf507173a 267 __regFaultMask = (faultMask & (uint32_t)1);
emilmont 77:869cf507173a 268 }
emilmont 77:869cf507173a 269
emilmont 77:869cf507173a 270 #endif /* (__CORTEX_M >= 0x03) */
emilmont 77:869cf507173a 271
emilmont 77:869cf507173a 272
emilmont 77:869cf507173a 273 #if (__CORTEX_M == 0x04)
emilmont 77:869cf507173a 274
emilmont 77:869cf507173a 275 /** \brief Get FPSCR
emilmont 77:869cf507173a 276
emilmont 77:869cf507173a 277 This function returns the current value of the Floating Point Status/Control register.
emilmont 77:869cf507173a 278
emilmont 77:869cf507173a 279 \return Floating Point Status/Control register value
emilmont 77:869cf507173a 280 */
emilmont 77:869cf507173a 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 77:869cf507173a 282 {
emilmont 77:869cf507173a 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 77:869cf507173a 284 register uint32_t __regfpscr __ASM("fpscr");
emilmont 77:869cf507173a 285 return(__regfpscr);
emilmont 77:869cf507173a 286 #else
emilmont 77:869cf507173a 287 return(0);
emilmont 77:869cf507173a 288 #endif
emilmont 77:869cf507173a 289 }
emilmont 77:869cf507173a 290
emilmont 77:869cf507173a 291
emilmont 77:869cf507173a 292 /** \brief Set FPSCR
emilmont 77:869cf507173a 293
emilmont 77:869cf507173a 294 This function assigns the given value to the Floating Point Status/Control register.
emilmont 77:869cf507173a 295
emilmont 77:869cf507173a 296 \param [in] fpscr Floating Point Status/Control value to set
emilmont 77:869cf507173a 297 */
emilmont 77:869cf507173a 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 77:869cf507173a 299 {
emilmont 77:869cf507173a 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 77:869cf507173a 301 register uint32_t __regfpscr __ASM("fpscr");
emilmont 77:869cf507173a 302 __regfpscr = (fpscr);
emilmont 77:869cf507173a 303 #endif
emilmont 77:869cf507173a 304 }
emilmont 77:869cf507173a 305
emilmont 77:869cf507173a 306 #endif /* (__CORTEX_M == 0x04) */
emilmont 77:869cf507173a 307
emilmont 77:869cf507173a 308
emilmont 77:869cf507173a 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 77:869cf507173a 310 /* IAR iccarm specific functions */
emilmont 77:869cf507173a 311
emilmont 77:869cf507173a 312 #include <cmsis_iar.h>
emilmont 77:869cf507173a 313
emilmont 77:869cf507173a 314
emilmont 77:869cf507173a 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 77:869cf507173a 316 /* TI CCS specific functions */
emilmont 77:869cf507173a 317
emilmont 77:869cf507173a 318 #include <cmsis_ccs.h>
emilmont 77:869cf507173a 319
emilmont 77:869cf507173a 320
emilmont 77:869cf507173a 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 77:869cf507173a 322 /* GNU gcc specific functions */
emilmont 77:869cf507173a 323
emilmont 77:869cf507173a 324 /** \brief Enable IRQ Interrupts
emilmont 77:869cf507173a 325
emilmont 77:869cf507173a 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
emilmont 77:869cf507173a 327 Can only be executed in Privileged modes.
emilmont 77:869cf507173a 328 */
emilmont 77:869cf507173a 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
emilmont 77:869cf507173a 330 {
emilmont 77:869cf507173a 331 __ASM volatile ("cpsie i" : : : "memory");
emilmont 77:869cf507173a 332 }
emilmont 77:869cf507173a 333
emilmont 77:869cf507173a 334
emilmont 77:869cf507173a 335 /** \brief Disable IRQ Interrupts
emilmont 77:869cf507173a 336
emilmont 77:869cf507173a 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
emilmont 77:869cf507173a 338 Can only be executed in Privileged modes.
emilmont 77:869cf507173a 339 */
emilmont 77:869cf507173a 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
emilmont 77:869cf507173a 341 {
emilmont 77:869cf507173a 342 __ASM volatile ("cpsid i" : : : "memory");
emilmont 77:869cf507173a 343 }
emilmont 77:869cf507173a 344
emilmont 77:869cf507173a 345
emilmont 77:869cf507173a 346 /** \brief Get Control Register
emilmont 77:869cf507173a 347
emilmont 77:869cf507173a 348 This function returns the content of the Control Register.
emilmont 77:869cf507173a 349
emilmont 77:869cf507173a 350 \return Control Register value
emilmont 77:869cf507173a 351 */
emilmont 77:869cf507173a 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 77:869cf507173a 353 {
emilmont 77:869cf507173a 354 uint32_t result;
emilmont 77:869cf507173a 355
emilmont 77:869cf507173a 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
emilmont 77:869cf507173a 357 return(result);
emilmont 77:869cf507173a 358 }
emilmont 77:869cf507173a 359
emilmont 77:869cf507173a 360
emilmont 77:869cf507173a 361 /** \brief Set Control Register
emilmont 77:869cf507173a 362
emilmont 77:869cf507173a 363 This function writes the given value to the Control Register.
emilmont 77:869cf507173a 364
emilmont 77:869cf507173a 365 \param [in] control Control Register value to set
emilmont 77:869cf507173a 366 */
emilmont 77:869cf507173a 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 77:869cf507173a 368 {
emilmont 77:869cf507173a 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
emilmont 77:869cf507173a 370 }
emilmont 77:869cf507173a 371
emilmont 77:869cf507173a 372
emilmont 77:869cf507173a 373 /** \brief Get IPSR Register
emilmont 77:869cf507173a 374
emilmont 77:869cf507173a 375 This function returns the content of the IPSR Register.
emilmont 77:869cf507173a 376
emilmont 77:869cf507173a 377 \return IPSR Register value
emilmont 77:869cf507173a 378 */
emilmont 77:869cf507173a 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 77:869cf507173a 380 {
emilmont 77:869cf507173a 381 uint32_t result;
emilmont 77:869cf507173a 382
emilmont 77:869cf507173a 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
emilmont 77:869cf507173a 384 return(result);
emilmont 77:869cf507173a 385 }
emilmont 77:869cf507173a 386
emilmont 77:869cf507173a 387
emilmont 77:869cf507173a 388 /** \brief Get APSR Register
emilmont 77:869cf507173a 389
emilmont 77:869cf507173a 390 This function returns the content of the APSR Register.
emilmont 77:869cf507173a 391
emilmont 77:869cf507173a 392 \return APSR Register value
emilmont 77:869cf507173a 393 */
emilmont 77:869cf507173a 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 77:869cf507173a 395 {
emilmont 77:869cf507173a 396 uint32_t result;
emilmont 77:869cf507173a 397
emilmont 77:869cf507173a 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
emilmont 77:869cf507173a 399 return(result);
emilmont 77:869cf507173a 400 }
emilmont 77:869cf507173a 401
emilmont 77:869cf507173a 402
emilmont 77:869cf507173a 403 /** \brief Get xPSR Register
emilmont 77:869cf507173a 404
emilmont 77:869cf507173a 405 This function returns the content of the xPSR Register.
emilmont 77:869cf507173a 406
emilmont 77:869cf507173a 407 \return xPSR Register value
emilmont 77:869cf507173a 408 */
emilmont 77:869cf507173a 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 77:869cf507173a 410 {
emilmont 77:869cf507173a 411 uint32_t result;
emilmont 77:869cf507173a 412
emilmont 77:869cf507173a 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
emilmont 77:869cf507173a 414 return(result);
emilmont 77:869cf507173a 415 }
emilmont 77:869cf507173a 416
emilmont 77:869cf507173a 417
emilmont 77:869cf507173a 418 /** \brief Get Process Stack Pointer
emilmont 77:869cf507173a 419
emilmont 77:869cf507173a 420 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 77:869cf507173a 421
emilmont 77:869cf507173a 422 \return PSP Register value
emilmont 77:869cf507173a 423 */
emilmont 77:869cf507173a 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 77:869cf507173a 425 {
emilmont 77:869cf507173a 426 register uint32_t result;
emilmont 77:869cf507173a 427
emilmont 77:869cf507173a 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
emilmont 77:869cf507173a 429 return(result);
emilmont 77:869cf507173a 430 }
emilmont 77:869cf507173a 431
emilmont 77:869cf507173a 432
emilmont 77:869cf507173a 433 /** \brief Set Process Stack Pointer
emilmont 77:869cf507173a 434
emilmont 77:869cf507173a 435 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 77:869cf507173a 436
emilmont 77:869cf507173a 437 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 77:869cf507173a 438 */
emilmont 77:869cf507173a 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 77:869cf507173a 440 {
emilmont 77:869cf507173a 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
emilmont 77:869cf507173a 442 }
emilmont 77:869cf507173a 443
emilmont 77:869cf507173a 444
emilmont 77:869cf507173a 445 /** \brief Get Main Stack Pointer
emilmont 77:869cf507173a 446
emilmont 77:869cf507173a 447 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 77:869cf507173a 448
emilmont 77:869cf507173a 449 \return MSP Register value
emilmont 77:869cf507173a 450 */
emilmont 77:869cf507173a 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 77:869cf507173a 452 {
emilmont 77:869cf507173a 453 register uint32_t result;
emilmont 77:869cf507173a 454
emilmont 77:869cf507173a 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
emilmont 77:869cf507173a 456 return(result);
emilmont 77:869cf507173a 457 }
emilmont 77:869cf507173a 458
emilmont 77:869cf507173a 459
emilmont 77:869cf507173a 460 /** \brief Set Main Stack Pointer
emilmont 77:869cf507173a 461
emilmont 77:869cf507173a 462 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 77:869cf507173a 463
emilmont 77:869cf507173a 464 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 77:869cf507173a 465 */
emilmont 77:869cf507173a 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 77:869cf507173a 467 {
emilmont 77:869cf507173a 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
emilmont 77:869cf507173a 469 }
emilmont 77:869cf507173a 470
emilmont 77:869cf507173a 471
emilmont 77:869cf507173a 472 /** \brief Get Priority Mask
emilmont 77:869cf507173a 473
emilmont 77:869cf507173a 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 77:869cf507173a 475
emilmont 77:869cf507173a 476 \return Priority Mask value
emilmont 77:869cf507173a 477 */
emilmont 77:869cf507173a 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 77:869cf507173a 479 {
emilmont 77:869cf507173a 480 uint32_t result;
emilmont 77:869cf507173a 481
emilmont 77:869cf507173a 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
emilmont 77:869cf507173a 483 return(result);
emilmont 77:869cf507173a 484 }
emilmont 77:869cf507173a 485
emilmont 77:869cf507173a 486
emilmont 77:869cf507173a 487 /** \brief Set Priority Mask
emilmont 77:869cf507173a 488
emilmont 77:869cf507173a 489 This function assigns the given value to the Priority Mask Register.
emilmont 77:869cf507173a 490
emilmont 77:869cf507173a 491 \param [in] priMask Priority Mask
emilmont 77:869cf507173a 492 */
emilmont 77:869cf507173a 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 77:869cf507173a 494 {
emilmont 77:869cf507173a 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
emilmont 77:869cf507173a 496 }
emilmont 77:869cf507173a 497
emilmont 77:869cf507173a 498
emilmont 77:869cf507173a 499 #if (__CORTEX_M >= 0x03)
emilmont 77:869cf507173a 500
emilmont 77:869cf507173a 501 /** \brief Enable FIQ
emilmont 77:869cf507173a 502
emilmont 77:869cf507173a 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 77:869cf507173a 504 Can only be executed in Privileged modes.
emilmont 77:869cf507173a 505 */
emilmont 77:869cf507173a 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
emilmont 77:869cf507173a 507 {
emilmont 77:869cf507173a 508 __ASM volatile ("cpsie f" : : : "memory");
emilmont 77:869cf507173a 509 }
emilmont 77:869cf507173a 510
emilmont 77:869cf507173a 511
emilmont 77:869cf507173a 512 /** \brief Disable FIQ
emilmont 77:869cf507173a 513
emilmont 77:869cf507173a 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 77:869cf507173a 515 Can only be executed in Privileged modes.
emilmont 77:869cf507173a 516 */
emilmont 77:869cf507173a 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
emilmont 77:869cf507173a 518 {
emilmont 77:869cf507173a 519 __ASM volatile ("cpsid f" : : : "memory");
emilmont 77:869cf507173a 520 }
emilmont 77:869cf507173a 521
emilmont 77:869cf507173a 522
emilmont 77:869cf507173a 523 /** \brief Get Base Priority
emilmont 77:869cf507173a 524
emilmont 77:869cf507173a 525 This function returns the current value of the Base Priority register.
emilmont 77:869cf507173a 526
emilmont 77:869cf507173a 527 \return Base Priority register value
emilmont 77:869cf507173a 528 */
emilmont 77:869cf507173a 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 77:869cf507173a 530 {
emilmont 77:869cf507173a 531 uint32_t result;
emilmont 77:869cf507173a 532
emilmont 77:869cf507173a 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
emilmont 77:869cf507173a 534 return(result);
emilmont 77:869cf507173a 535 }
emilmont 77:869cf507173a 536
emilmont 77:869cf507173a 537
emilmont 77:869cf507173a 538 /** \brief Set Base Priority
emilmont 77:869cf507173a 539
emilmont 77:869cf507173a 540 This function assigns the given value to the Base Priority register.
emilmont 77:869cf507173a 541
emilmont 77:869cf507173a 542 \param [in] basePri Base Priority value to set
emilmont 77:869cf507173a 543 */
emilmont 77:869cf507173a 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
emilmont 77:869cf507173a 545 {
emilmont 77:869cf507173a 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
emilmont 77:869cf507173a 547 }
emilmont 77:869cf507173a 548
emilmont 77:869cf507173a 549
emilmont 77:869cf507173a 550 /** \brief Get Fault Mask
emilmont 77:869cf507173a 551
emilmont 77:869cf507173a 552 This function returns the current value of the Fault Mask register.
emilmont 77:869cf507173a 553
emilmont 77:869cf507173a 554 \return Fault Mask register value
emilmont 77:869cf507173a 555 */
emilmont 77:869cf507173a 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 77:869cf507173a 557 {
emilmont 77:869cf507173a 558 uint32_t result;
emilmont 77:869cf507173a 559
emilmont 77:869cf507173a 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
emilmont 77:869cf507173a 561 return(result);
emilmont 77:869cf507173a 562 }
emilmont 77:869cf507173a 563
emilmont 77:869cf507173a 564
emilmont 77:869cf507173a 565 /** \brief Set Fault Mask
emilmont 77:869cf507173a 566
emilmont 77:869cf507173a 567 This function assigns the given value to the Fault Mask register.
emilmont 77:869cf507173a 568
emilmont 77:869cf507173a 569 \param [in] faultMask Fault Mask value to set
emilmont 77:869cf507173a 570 */
emilmont 77:869cf507173a 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 77:869cf507173a 572 {
emilmont 77:869cf507173a 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
emilmont 77:869cf507173a 574 }
emilmont 77:869cf507173a 575
emilmont 77:869cf507173a 576 #endif /* (__CORTEX_M >= 0x03) */
emilmont 77:869cf507173a 577
emilmont 77:869cf507173a 578
emilmont 77:869cf507173a 579 #if (__CORTEX_M == 0x04)
emilmont 77:869cf507173a 580
emilmont 77:869cf507173a 581 /** \brief Get FPSCR
emilmont 77:869cf507173a 582
emilmont 77:869cf507173a 583 This function returns the current value of the Floating Point Status/Control register.
emilmont 77:869cf507173a 584
emilmont 77:869cf507173a 585 \return Floating Point Status/Control register value
emilmont 77:869cf507173a 586 */
emilmont 77:869cf507173a 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 77:869cf507173a 588 {
emilmont 77:869cf507173a 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 77:869cf507173a 590 uint32_t result;
emilmont 77:869cf507173a 591
emilmont 77:869cf507173a 592 /* Empty asm statement works as a scheduling barrier */
emilmont 77:869cf507173a 593 __ASM volatile ("");
emilmont 77:869cf507173a 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
emilmont 77:869cf507173a 595 __ASM volatile ("");
emilmont 77:869cf507173a 596 return(result);
emilmont 77:869cf507173a 597 #else
emilmont 77:869cf507173a 598 return(0);
emilmont 77:869cf507173a 599 #endif
emilmont 77:869cf507173a 600 }
emilmont 77:869cf507173a 601
emilmont 77:869cf507173a 602
emilmont 77:869cf507173a 603 /** \brief Set FPSCR
emilmont 77:869cf507173a 604
emilmont 77:869cf507173a 605 This function assigns the given value to the Floating Point Status/Control register.
emilmont 77:869cf507173a 606
emilmont 77:869cf507173a 607 \param [in] fpscr Floating Point Status/Control value to set
emilmont 77:869cf507173a 608 */
emilmont 77:869cf507173a 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 77:869cf507173a 610 {
emilmont 77:869cf507173a 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 77:869cf507173a 612 /* Empty asm statement works as a scheduling barrier */
emilmont 77:869cf507173a 613 __ASM volatile ("");
emilmont 77:869cf507173a 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
emilmont 77:869cf507173a 615 __ASM volatile ("");
emilmont 77:869cf507173a 616 #endif
emilmont 77:869cf507173a 617 }
emilmont 77:869cf507173a 618
emilmont 77:869cf507173a 619 #endif /* (__CORTEX_M == 0x04) */
emilmont 77:869cf507173a 620
emilmont 77:869cf507173a 621
emilmont 77:869cf507173a 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 77:869cf507173a 623 /* TASKING carm specific functions */
emilmont 77:869cf507173a 624
emilmont 77:869cf507173a 625 /*
emilmont 77:869cf507173a 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 77:869cf507173a 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 77:869cf507173a 628 * Including the CMSIS ones.
emilmont 77:869cf507173a 629 */
emilmont 77:869cf507173a 630
emilmont 77:869cf507173a 631 #endif
emilmont 77:869cf507173a 632
emilmont 77:869cf507173a 633 /*@} end of CMSIS_Core_RegAccFunctions */
emilmont 77:869cf507173a 634
emilmont 77:869cf507173a 635
emilmont 77:869cf507173a 636 #endif /* __CORE_CMFUNC_H */