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TARGET_NUCLEO_F030R8/stm32f0xx_spi.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: 81:7d30d6019079

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f0xx_spi.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
emilmont	77:869cf507173a	5	* @version V1.3.0
emilmont	77:869cf507173a	6	* @date 16-January-2014
emilmont	77:869cf507173a	7	* @brief This file contains all the functions prototypes for the SPI
emilmont	77:869cf507173a	8	* firmware library.
emilmont	77:869cf507173a	9	******************************************************************************
emilmont	77:869cf507173a	10	* @attention
emilmont	77:869cf507173a	11	*
bogdanm	81:7d30d6019079	12	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	13	*
bogdanm	81:7d30d6019079	14	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	81:7d30d6019079	15	* are permitted provided that the following conditions are met:
bogdanm	81:7d30d6019079	16	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	81:7d30d6019079	17	* this list of conditions and the following disclaimer.
bogdanm	81:7d30d6019079	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	81:7d30d6019079	19	* this list of conditions and the following disclaimer in the documentation
bogdanm	81:7d30d6019079	20	* and/or other materials provided with the distribution.
bogdanm	81:7d30d6019079	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	81:7d30d6019079	22	* may be used to endorse or promote products derived from this software
bogdanm	81:7d30d6019079	23	* without specific prior written permission.
emilmont	77:869cf507173a	24	*
bogdanm	81:7d30d6019079	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	81:7d30d6019079	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	81:7d30d6019079	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	81:7d30d6019079	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	81:7d30d6019079	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	81:7d30d6019079	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	81:7d30d6019079	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	81:7d30d6019079	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	81:7d30d6019079	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	81:7d30d6019079	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	35	*
emilmont	77:869cf507173a	36	******************************************************************************
emilmont	77:869cf507173a	37	*/
emilmont	77:869cf507173a	38
emilmont	77:869cf507173a	39	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	40	#ifndef __STM32F0XX_SPI_H
emilmont	77:869cf507173a	41	#define __STM32F0XX_SPI_H
emilmont	77:869cf507173a	42
emilmont	77:869cf507173a	43	#ifdef __cplusplus
emilmont	77:869cf507173a	44	extern "C" {
emilmont	77:869cf507173a	45	#endif
emilmont	77:869cf507173a	46
emilmont	77:869cf507173a	47	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	48	#include "stm32f0xx.h"
emilmont	77:869cf507173a	49
emilmont	77:869cf507173a	50	/** @addtogroup STM32F0xx_StdPeriph_Driver
emilmont	77:869cf507173a	51	* @{
emilmont	77:869cf507173a	52	*/
emilmont	77:869cf507173a	53
emilmont	77:869cf507173a	54	/** @addtogroup SPI
emilmont	77:869cf507173a	55	* @{
emilmont	77:869cf507173a	56	*/
emilmont	77:869cf507173a	57
emilmont	77:869cf507173a	58	/* Exported types ------------------------------------------------------------*/
emilmont	77:869cf507173a	59
emilmont	77:869cf507173a	60	/**
emilmont	77:869cf507173a	61	* @brief SPI Init structure definition
emilmont	77:869cf507173a	62	*/
emilmont	77:869cf507173a	63
emilmont	77:869cf507173a	64	typedef struct
emilmont	77:869cf507173a	65	{
emilmont	77:869cf507173a	66	uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
emilmont	77:869cf507173a	67	This parameter can be a value of @ref SPI_data_direction */
emilmont	77:869cf507173a	68
emilmont	77:869cf507173a	69	uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
emilmont	77:869cf507173a	70	This parameter can be a value of @ref SPI_mode */
emilmont	77:869cf507173a	71
emilmont	77:869cf507173a	72	uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
emilmont	77:869cf507173a	73	This parameter can be a value of @ref SPI_data_size */
emilmont	77:869cf507173a	74
emilmont	77:869cf507173a	75	uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
emilmont	77:869cf507173a	76	This parameter can be a value of @ref SPI_Clock_Polarity */
emilmont	77:869cf507173a	77
emilmont	77:869cf507173a	78	uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
emilmont	77:869cf507173a	79	This parameter can be a value of @ref SPI_Clock_Phase */
emilmont	77:869cf507173a	80
emilmont	77:869cf507173a	81	uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
emilmont	77:869cf507173a	82	hardware (NSS pin) or by software using the SSI bit.
emilmont	77:869cf507173a	83	This parameter can be a value of @ref SPI_Slave_Select_management */
emilmont	77:869cf507173a	84
emilmont	77:869cf507173a	85	uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
emilmont	77:869cf507173a	86	used to configure the transmit and receive SCK clock.
emilmont	77:869cf507173a	87	This parameter can be a value of @ref SPI_BaudRate_Prescaler
emilmont	77:869cf507173a	88	@note The communication clock is derived from the master
emilmont	77:869cf507173a	89	clock. The slave clock does not need to be set. */
emilmont	77:869cf507173a	90
emilmont	77:869cf507173a	91	uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
emilmont	77:869cf507173a	92	This parameter can be a value of @ref SPI_MSB_LSB_transmission */
emilmont	77:869cf507173a	93
emilmont	77:869cf507173a	94	uint16_t SPI_CRCPolynomial; /!< Specifies the polynomial used for the CRC calculation. /
emilmont	77:869cf507173a	95	}SPI_InitTypeDef;
emilmont	77:869cf507173a	96
emilmont	77:869cf507173a	97
emilmont	77:869cf507173a	98	/**
emilmont	77:869cf507173a	99	* @brief I2S Init structure definition
emilmont	77:869cf507173a	100	* @note These parameters are not available for STM32F030 devices.
emilmont	77:869cf507173a	101	*/
emilmont	77:869cf507173a	102
emilmont	77:869cf507173a	103	typedef struct
emilmont	77:869cf507173a	104	{
emilmont	77:869cf507173a	105	uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
emilmont	77:869cf507173a	106	This parameter can be a value of @ref SPI_I2S_Mode */
emilmont	77:869cf507173a	107
emilmont	77:869cf507173a	108	uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
emilmont	77:869cf507173a	109	This parameter can be a value of @ref SPI_I2S_Standard */
emilmont	77:869cf507173a	110
emilmont	77:869cf507173a	111	uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
emilmont	77:869cf507173a	112	This parameter can be a value of @ref SPI_I2S_Data_Format */
emilmont	77:869cf507173a	113
emilmont	77:869cf507173a	114	uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
emilmont	77:869cf507173a	115	This parameter can be a value of @ref SPI_I2S_MCLK_Output */
emilmont	77:869cf507173a	116
emilmont	77:869cf507173a	117	uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
emilmont	77:869cf507173a	118	This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
emilmont	77:869cf507173a	119
emilmont	77:869cf507173a	120	uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
emilmont	77:869cf507173a	121	This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
emilmont	77:869cf507173a	122	}I2S_InitTypeDef;
emilmont	77:869cf507173a	123
emilmont	77:869cf507173a	124	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	125
emilmont	77:869cf507173a	126	/** @defgroup SPI_Exported_Constants
emilmont	77:869cf507173a	127	* @{
emilmont	77:869cf507173a	128	*/
emilmont	77:869cf507173a	129
emilmont	77:869cf507173a	130	#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) \|\| \
emilmont	77:869cf507173a	131	((PERIPH) == SPI2))
emilmont	77:869cf507173a	132
emilmont	77:869cf507173a	133	#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1))
emilmont	77:869cf507173a	134
emilmont	77:869cf507173a	135	/** @defgroup SPI_data_direction
emilmont	77:869cf507173a	136	* @{
emilmont	77:869cf507173a	137	*/
emilmont	77:869cf507173a	138
emilmont	77:869cf507173a	139	#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
emilmont	77:869cf507173a	140	#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
emilmont	77:869cf507173a	141	#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
emilmont	77:869cf507173a	142	#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
emilmont	77:869cf507173a	143	#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) \|\| \
emilmont	77:869cf507173a	144	((MODE) == SPI_Direction_2Lines_RxOnly) \|\| \
emilmont	77:869cf507173a	145	((MODE) == SPI_Direction_1Line_Rx) \|\| \
emilmont	77:869cf507173a	146	((MODE) == SPI_Direction_1Line_Tx))
emilmont	77:869cf507173a	147	/**
emilmont	77:869cf507173a	148	* @}
emilmont	77:869cf507173a	149	*/
emilmont	77:869cf507173a	150
emilmont	77:869cf507173a	151	/** @defgroup SPI_mode
emilmont	77:869cf507173a	152	* @{
emilmont	77:869cf507173a	153	*/
emilmont	77:869cf507173a	154
emilmont	77:869cf507173a	155	#define SPI_Mode_Master ((uint16_t)0x0104)
emilmont	77:869cf507173a	156	#define SPI_Mode_Slave ((uint16_t)0x0000)
emilmont	77:869cf507173a	157	#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) \|\| \
emilmont	77:869cf507173a	158	((MODE) == SPI_Mode_Slave))
emilmont	77:869cf507173a	159	/**
emilmont	77:869cf507173a	160	* @}
emilmont	77:869cf507173a	161	*/
emilmont	77:869cf507173a	162
emilmont	77:869cf507173a	163	/** @defgroup SPI_data_size
emilmont	77:869cf507173a	164	* @{
emilmont	77:869cf507173a	165	*/
emilmont	77:869cf507173a	166
emilmont	77:869cf507173a	167	#define SPI_DataSize_4b ((uint16_t)0x0300)
emilmont	77:869cf507173a	168	#define SPI_DataSize_5b ((uint16_t)0x0400)
emilmont	77:869cf507173a	169	#define SPI_DataSize_6b ((uint16_t)0x0500)
emilmont	77:869cf507173a	170	#define SPI_DataSize_7b ((uint16_t)0x0600)
emilmont	77:869cf507173a	171	#define SPI_DataSize_8b ((uint16_t)0x0700)
emilmont	77:869cf507173a	172	#define SPI_DataSize_9b ((uint16_t)0x0800)
emilmont	77:869cf507173a	173	#define SPI_DataSize_10b ((uint16_t)0x0900)
emilmont	77:869cf507173a	174	#define SPI_DataSize_11b ((uint16_t)0x0A00)
emilmont	77:869cf507173a	175	#define SPI_DataSize_12b ((uint16_t)0x0B00)
emilmont	77:869cf507173a	176	#define SPI_DataSize_13b ((uint16_t)0x0C00)
emilmont	77:869cf507173a	177	#define SPI_DataSize_14b ((uint16_t)0x0D00)
emilmont	77:869cf507173a	178	#define SPI_DataSize_15b ((uint16_t)0x0E00)
emilmont	77:869cf507173a	179	#define SPI_DataSize_16b ((uint16_t)0x0F00)
emilmont	77:869cf507173a	180	#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) \|\| \
emilmont	77:869cf507173a	181	((SIZE) == SPI_DataSize_5b) \|\| \
emilmont	77:869cf507173a	182	((SIZE) == SPI_DataSize_6b) \|\| \
emilmont	77:869cf507173a	183	((SIZE) == SPI_DataSize_7b) \|\| \
emilmont	77:869cf507173a	184	((SIZE) == SPI_DataSize_8b) \|\| \
emilmont	77:869cf507173a	185	((SIZE) == SPI_DataSize_9b) \|\| \
emilmont	77:869cf507173a	186	((SIZE) == SPI_DataSize_10b) \|\| \
emilmont	77:869cf507173a	187	((SIZE) == SPI_DataSize_11b) \|\| \
emilmont	77:869cf507173a	188	((SIZE) == SPI_DataSize_12b) \|\| \
emilmont	77:869cf507173a	189	((SIZE) == SPI_DataSize_13b) \|\| \
emilmont	77:869cf507173a	190	((SIZE) == SPI_DataSize_14b) \|\| \
emilmont	77:869cf507173a	191	((SIZE) == SPI_DataSize_15b) \|\| \
emilmont	77:869cf507173a	192	((SIZE) == SPI_DataSize_16b))
emilmont	77:869cf507173a	193	/**
emilmont	77:869cf507173a	194	* @}
emilmont	77:869cf507173a	195	*/
emilmont	77:869cf507173a	196
emilmont	77:869cf507173a	197	/** @defgroup SPI_CRC_length
emilmont	77:869cf507173a	198	* @{
emilmont	77:869cf507173a	199	*/
emilmont	77:869cf507173a	200
emilmont	77:869cf507173a	201	#define SPI_CRCLength_8b ((uint16_t)0x0000)
emilmont	77:869cf507173a	202	#define SPI_CRCLength_16b SPI_CR1_CRCL
emilmont	77:869cf507173a	203	#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) \|\| \
emilmont	77:869cf507173a	204	((LENGTH) == SPI_CRCLength_16b))
emilmont	77:869cf507173a	205	/**
emilmont	77:869cf507173a	206	* @}
emilmont	77:869cf507173a	207	*/
emilmont	77:869cf507173a	208
emilmont	77:869cf507173a	209	/** @defgroup SPI_Clock_Polarity
emilmont	77:869cf507173a	210	* @{
emilmont	77:869cf507173a	211	*/
emilmont	77:869cf507173a	212
emilmont	77:869cf507173a	213	#define SPI_CPOL_Low ((uint16_t)0x0000)
emilmont	77:869cf507173a	214	#define SPI_CPOL_High SPI_CR1_CPOL
emilmont	77:869cf507173a	215	#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) \|\| \
emilmont	77:869cf507173a	216	((CPOL) == SPI_CPOL_High))
emilmont	77:869cf507173a	217	/**
emilmont	77:869cf507173a	218	* @}
emilmont	77:869cf507173a	219	*/
emilmont	77:869cf507173a	220
emilmont	77:869cf507173a	221	/** @defgroup SPI_Clock_Phase
emilmont	77:869cf507173a	222	* @{
emilmont	77:869cf507173a	223	*/
emilmont	77:869cf507173a	224
emilmont	77:869cf507173a	225	#define SPI_CPHA_1Edge ((uint16_t)0x0000)
emilmont	77:869cf507173a	226	#define SPI_CPHA_2Edge SPI_CR1_CPHA
emilmont	77:869cf507173a	227	#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) \|\| \
emilmont	77:869cf507173a	228	((CPHA) == SPI_CPHA_2Edge))
emilmont	77:869cf507173a	229	/**
emilmont	77:869cf507173a	230	* @}
emilmont	77:869cf507173a	231	*/
emilmont	77:869cf507173a	232
emilmont	77:869cf507173a	233	/** @defgroup SPI_Slave_Select_management
emilmont	77:869cf507173a	234	* @{
emilmont	77:869cf507173a	235	*/
emilmont	77:869cf507173a	236
emilmont	77:869cf507173a	237	#define SPI_NSS_Soft SPI_CR1_SSM
emilmont	77:869cf507173a	238	#define SPI_NSS_Hard ((uint16_t)0x0000)
emilmont	77:869cf507173a	239	#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) \|\| \
emilmont	77:869cf507173a	240	((NSS) == SPI_NSS_Hard))
emilmont	77:869cf507173a	241	/**
emilmont	77:869cf507173a	242	* @}
emilmont	77:869cf507173a	243	*/
emilmont	77:869cf507173a	244
emilmont	77:869cf507173a	245	/** @defgroup SPI_BaudRate_Prescaler
emilmont	77:869cf507173a	246	* @{
emilmont	77:869cf507173a	247	*/
emilmont	77:869cf507173a	248
emilmont	77:869cf507173a	249	#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
emilmont	77:869cf507173a	250	#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
emilmont	77:869cf507173a	251	#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
emilmont	77:869cf507173a	252	#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
emilmont	77:869cf507173a	253	#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
emilmont	77:869cf507173a	254	#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
emilmont	77:869cf507173a	255	#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
emilmont	77:869cf507173a	256	#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
emilmont	77:869cf507173a	257	#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) \|\| \
emilmont	77:869cf507173a	258	((PRESCALER) == SPI_BaudRatePrescaler_4) \|\| \
emilmont	77:869cf507173a	259	((PRESCALER) == SPI_BaudRatePrescaler_8) \|\| \
emilmont	77:869cf507173a	260	((PRESCALER) == SPI_BaudRatePrescaler_16) \|\| \
emilmont	77:869cf507173a	261	((PRESCALER) == SPI_BaudRatePrescaler_32) \|\| \
emilmont	77:869cf507173a	262	((PRESCALER) == SPI_BaudRatePrescaler_64) \|\| \
emilmont	77:869cf507173a	263	((PRESCALER) == SPI_BaudRatePrescaler_128) \|\| \
emilmont	77:869cf507173a	264	((PRESCALER) == SPI_BaudRatePrescaler_256))
emilmont	77:869cf507173a	265	/**
emilmont	77:869cf507173a	266	* @}
emilmont	77:869cf507173a	267	*/
emilmont	77:869cf507173a	268
emilmont	77:869cf507173a	269	/** @defgroup SPI_MSB_LSB_transmission
emilmont	77:869cf507173a	270	* @{
emilmont	77:869cf507173a	271	*/
emilmont	77:869cf507173a	272
emilmont	77:869cf507173a	273	#define SPI_FirstBit_MSB ((uint16_t)0x0000)
emilmont	77:869cf507173a	274	#define SPI_FirstBit_LSB SPI_CR1_LSBFIRST
emilmont	77:869cf507173a	275	#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) \|\| \
emilmont	77:869cf507173a	276	((BIT) == SPI_FirstBit_LSB))
emilmont	77:869cf507173a	277	/**
emilmont	77:869cf507173a	278	* @}
emilmont	77:869cf507173a	279	*/
emilmont	77:869cf507173a	280
emilmont	77:869cf507173a	281	/** @defgroup SPI_I2S_Mode
emilmont	77:869cf507173a	282	* @{
emilmont	77:869cf507173a	283	*/
emilmont	77:869cf507173a	284
emilmont	77:869cf507173a	285	#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
emilmont	77:869cf507173a	286	#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
emilmont	77:869cf507173a	287	#define I2S_Mode_MasterTx ((uint16_t)0x0200)
emilmont	77:869cf507173a	288	#define I2S_Mode_MasterRx ((uint16_t)0x0300)
emilmont	77:869cf507173a	289	#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) \|\| \
emilmont	77:869cf507173a	290	((MODE) == I2S_Mode_SlaveRx) \|\| \
emilmont	77:869cf507173a	291	((MODE) == I2S_Mode_MasterTx)\|\| \
emilmont	77:869cf507173a	292	((MODE) == I2S_Mode_MasterRx))
emilmont	77:869cf507173a	293	/**
emilmont	77:869cf507173a	294	* @}
emilmont	77:869cf507173a	295	*/
emilmont	77:869cf507173a	296
emilmont	77:869cf507173a	297	/** @defgroup SPI_I2S_Standard
emilmont	77:869cf507173a	298	* @{
emilmont	77:869cf507173a	299	*/
emilmont	77:869cf507173a	300
emilmont	77:869cf507173a	301	#define I2S_Standard_Phillips ((uint16_t)0x0000)
emilmont	77:869cf507173a	302	#define I2S_Standard_MSB ((uint16_t)0x0010)
emilmont	77:869cf507173a	303	#define I2S_Standard_LSB ((uint16_t)0x0020)
emilmont	77:869cf507173a	304	#define I2S_Standard_PCMShort ((uint16_t)0x0030)
emilmont	77:869cf507173a	305	#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
emilmont	77:869cf507173a	306	#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) \|\| \
emilmont	77:869cf507173a	307	((STANDARD) == I2S_Standard_MSB) \|\| \
emilmont	77:869cf507173a	308	((STANDARD) == I2S_Standard_LSB) \|\| \
emilmont	77:869cf507173a	309	((STANDARD) == I2S_Standard_PCMShort) \|\| \
emilmont	77:869cf507173a	310	((STANDARD) == I2S_Standard_PCMLong))
emilmont	77:869cf507173a	311	/**
emilmont	77:869cf507173a	312	* @}
emilmont	77:869cf507173a	313	*/
emilmont	77:869cf507173a	314
emilmont	77:869cf507173a	315	/** @defgroup SPI_I2S_Data_Format
emilmont	77:869cf507173a	316	* @{
emilmont	77:869cf507173a	317	*/
emilmont	77:869cf507173a	318
emilmont	77:869cf507173a	319	#define I2S_DataFormat_16b ((uint16_t)0x0000)
emilmont	77:869cf507173a	320	#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
emilmont	77:869cf507173a	321	#define I2S_DataFormat_24b ((uint16_t)0x0003)
emilmont	77:869cf507173a	322	#define I2S_DataFormat_32b ((uint16_t)0x0005)
emilmont	77:869cf507173a	323	#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) \|\| \
emilmont	77:869cf507173a	324	((FORMAT) == I2S_DataFormat_16bextended) \|\| \
emilmont	77:869cf507173a	325	((FORMAT) == I2S_DataFormat_24b) \|\| \
emilmont	77:869cf507173a	326	((FORMAT) == I2S_DataFormat_32b))
emilmont	77:869cf507173a	327	/**
emilmont	77:869cf507173a	328	* @}
emilmont	77:869cf507173a	329	*/
emilmont	77:869cf507173a	330
emilmont	77:869cf507173a	331	/** @defgroup SPI_I2S_MCLK_Output
emilmont	77:869cf507173a	332	* @{
emilmont	77:869cf507173a	333	*/
emilmont	77:869cf507173a	334
emilmont	77:869cf507173a	335	#define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE
emilmont	77:869cf507173a	336	#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	337	#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) \|\| \
emilmont	77:869cf507173a	338	((OUTPUT) == I2S_MCLKOutput_Disable))
emilmont	77:869cf507173a	339	/**
emilmont	77:869cf507173a	340	* @}
emilmont	77:869cf507173a	341	*/
emilmont	77:869cf507173a	342
emilmont	77:869cf507173a	343	/** @defgroup SPI_I2S_Audio_Frequency
emilmont	77:869cf507173a	344	* @{
emilmont	77:869cf507173a	345	*/
emilmont	77:869cf507173a	346
emilmont	77:869cf507173a	347	#define I2S_AudioFreq_192k ((uint32_t)192000)
emilmont	77:869cf507173a	348	#define I2S_AudioFreq_96k ((uint32_t)96000)
emilmont	77:869cf507173a	349	#define I2S_AudioFreq_48k ((uint32_t)48000)
emilmont	77:869cf507173a	350	#define I2S_AudioFreq_44k ((uint32_t)44100)
emilmont	77:869cf507173a	351	#define I2S_AudioFreq_32k ((uint32_t)32000)
emilmont	77:869cf507173a	352	#define I2S_AudioFreq_22k ((uint32_t)22050)
emilmont	77:869cf507173a	353	#define I2S_AudioFreq_16k ((uint32_t)16000)
emilmont	77:869cf507173a	354	#define I2S_AudioFreq_11k ((uint32_t)11025)
emilmont	77:869cf507173a	355	#define I2S_AudioFreq_8k ((uint32_t)8000)
emilmont	77:869cf507173a	356	#define I2S_AudioFreq_Default ((uint32_t)2)
emilmont	77:869cf507173a	357
emilmont	77:869cf507173a	358	#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
emilmont	77:869cf507173a	359	((FREQ) <= I2S_AudioFreq_192k)) \|\| \
emilmont	77:869cf507173a	360	((FREQ) == I2S_AudioFreq_Default))
emilmont	77:869cf507173a	361	/**
emilmont	77:869cf507173a	362	* @}
emilmont	77:869cf507173a	363	*/
emilmont	77:869cf507173a	364
emilmont	77:869cf507173a	365	/** @defgroup SPI_I2S_Clock_Polarity
emilmont	77:869cf507173a	366	* @{
emilmont	77:869cf507173a	367	*/
emilmont	77:869cf507173a	368
emilmont	77:869cf507173a	369	#define I2S_CPOL_Low ((uint16_t)0x0000)
emilmont	77:869cf507173a	370	#define I2S_CPOL_High SPI_I2SCFGR_CKPOL
emilmont	77:869cf507173a	371	#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) \|\| \
emilmont	77:869cf507173a	372	((CPOL) == I2S_CPOL_High))
emilmont	77:869cf507173a	373	/**
emilmont	77:869cf507173a	374	* @}
emilmont	77:869cf507173a	375	*/
emilmont	77:869cf507173a	376
emilmont	77:869cf507173a	377	/** @defgroup SPI_FIFO_reception_threshold
emilmont	77:869cf507173a	378	* @{
emilmont	77:869cf507173a	379	*/
emilmont	77:869cf507173a	380
emilmont	77:869cf507173a	381	#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
emilmont	77:869cf507173a	382	#define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH
emilmont	77:869cf507173a	383	#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) \|\| \
emilmont	77:869cf507173a	384	((THRESHOLD) == SPI_RxFIFOThreshold_QF))
emilmont	77:869cf507173a	385	/**
emilmont	77:869cf507173a	386	* @}
emilmont	77:869cf507173a	387	*/
emilmont	77:869cf507173a	388
emilmont	77:869cf507173a	389	/** @defgroup SPI_I2S_DMA_transfer_requests
emilmont	77:869cf507173a	390	* @{
emilmont	77:869cf507173a	391	*/
emilmont	77:869cf507173a	392
emilmont	77:869cf507173a	393	#define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN
emilmont	77:869cf507173a	394	#define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN
emilmont	77:869cf507173a	395	#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
emilmont	77:869cf507173a	396	/**
emilmont	77:869cf507173a	397	* @}
emilmont	77:869cf507173a	398	*/
emilmont	77:869cf507173a	399
emilmont	77:869cf507173a	400	/** @defgroup SPI_last_DMA_transfers
emilmont	77:869cf507173a	401	* @{
emilmont	77:869cf507173a	402	*/
emilmont	77:869cf507173a	403
emilmont	77:869cf507173a	404	#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
emilmont	77:869cf507173a	405	#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
emilmont	77:869cf507173a	406	#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
emilmont	77:869cf507173a	407	#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
emilmont	77:869cf507173a	408	#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) \|\| \
emilmont	77:869cf507173a	409	((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) \|\| \
emilmont	77:869cf507173a	410	((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) \|\| \
emilmont	77:869cf507173a	411	((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
emilmont	77:869cf507173a	412	/**
emilmont	77:869cf507173a	413	* @}
emilmont	77:869cf507173a	414	*/
emilmont	77:869cf507173a	415	/** @defgroup SPI_NSS_internal_software_management
emilmont	77:869cf507173a	416	* @{
emilmont	77:869cf507173a	417	*/
emilmont	77:869cf507173a	418
emilmont	77:869cf507173a	419	#define SPI_NSSInternalSoft_Set SPI_CR1_SSI
emilmont	77:869cf507173a	420	#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
emilmont	77:869cf507173a	421	#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) \|\| \
emilmont	77:869cf507173a	422	((INTERNAL) == SPI_NSSInternalSoft_Reset))
emilmont	77:869cf507173a	423	/**
emilmont	77:869cf507173a	424	* @}
emilmont	77:869cf507173a	425	*/
emilmont	77:869cf507173a	426
emilmont	77:869cf507173a	427	/** @defgroup SPI_CRC_Transmit_Receive
emilmont	77:869cf507173a	428	* @{
emilmont	77:869cf507173a	429	*/
emilmont	77:869cf507173a	430
emilmont	77:869cf507173a	431	#define SPI_CRC_Tx ((uint8_t)0x00)
emilmont	77:869cf507173a	432	#define SPI_CRC_Rx ((uint8_t)0x01)
emilmont	77:869cf507173a	433	#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) \|\| ((CRC) == SPI_CRC_Rx))
emilmont	77:869cf507173a	434	/**
emilmont	77:869cf507173a	435	* @}
emilmont	77:869cf507173a	436	*/
emilmont	77:869cf507173a	437
emilmont	77:869cf507173a	438	/** @defgroup SPI_direction_transmit_receive
emilmont	77:869cf507173a	439	* @{
emilmont	77:869cf507173a	440	*/
emilmont	77:869cf507173a	441
emilmont	77:869cf507173a	442	#define SPI_Direction_Rx ((uint16_t)0xBFFF)
emilmont	77:869cf507173a	443	#define SPI_Direction_Tx ((uint16_t)0x4000)
emilmont	77:869cf507173a	444	#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) \|\| \
emilmont	77:869cf507173a	445	((DIRECTION) == SPI_Direction_Tx))
emilmont	77:869cf507173a	446	/**
emilmont	77:869cf507173a	447	* @}
emilmont	77:869cf507173a	448	*/
emilmont	77:869cf507173a	449
emilmont	77:869cf507173a	450	/** @defgroup SPI_I2S_interrupts_definition
emilmont	77:869cf507173a	451	* @{
emilmont	77:869cf507173a	452	*/
emilmont	77:869cf507173a	453
emilmont	77:869cf507173a	454	#define SPI_I2S_IT_TXE ((uint8_t)0x71)
emilmont	77:869cf507173a	455	#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
emilmont	77:869cf507173a	456	#define SPI_I2S_IT_ERR ((uint8_t)0x50)
emilmont	77:869cf507173a	457
emilmont	77:869cf507173a	458	#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) \|\| \
emilmont	77:869cf507173a	459	((IT) == SPI_I2S_IT_RXNE) \|\| \
emilmont	77:869cf507173a	460	((IT) == SPI_I2S_IT_ERR))
emilmont	77:869cf507173a	461
emilmont	77:869cf507173a	462	#define I2S_IT_UDR ((uint8_t)0x53)
emilmont	77:869cf507173a	463	#define SPI_IT_MODF ((uint8_t)0x55)
emilmont	77:869cf507173a	464	#define SPI_I2S_IT_OVR ((uint8_t)0x56)
emilmont	77:869cf507173a	465	#define SPI_I2S_IT_FRE ((uint8_t)0x58)
emilmont	77:869cf507173a	466
emilmont	77:869cf507173a	467	#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) \|\| ((IT) == SPI_I2S_IT_TXE) \|\| \
emilmont	77:869cf507173a	468	((IT) == SPI_I2S_IT_OVR) \|\| ((IT) == SPI_IT_MODF) \|\| \
emilmont	77:869cf507173a	469	((IT) == SPI_I2S_IT_FRE)\|\| ((IT) == I2S_IT_UDR))
emilmont	77:869cf507173a	470	/**
emilmont	77:869cf507173a	471	* @}
emilmont	77:869cf507173a	472	*/
emilmont	77:869cf507173a	473
emilmont	77:869cf507173a	474
emilmont	77:869cf507173a	475	/** @defgroup SPI_transmission_fifo_status_level
emilmont	77:869cf507173a	476	* @{
emilmont	77:869cf507173a	477	*/
emilmont	77:869cf507173a	478
emilmont	77:869cf507173a	479	#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
emilmont	77:869cf507173a	480	#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
emilmont	77:869cf507173a	481	#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
emilmont	77:869cf507173a	482	#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
emilmont	77:869cf507173a	483
emilmont	77:869cf507173a	484	/**
emilmont	77:869cf507173a	485	* @}
emilmont	77:869cf507173a	486	*/
emilmont	77:869cf507173a	487
emilmont	77:869cf507173a	488	/** @defgroup SPI_reception_fifo_status_level
emilmont	77:869cf507173a	489	* @{
emilmont	77:869cf507173a	490	*/
emilmont	77:869cf507173a	491	#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
emilmont	77:869cf507173a	492	#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
emilmont	77:869cf507173a	493	#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
emilmont	77:869cf507173a	494	#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
emilmont	77:869cf507173a	495
emilmont	77:869cf507173a	496	/**
emilmont	77:869cf507173a	497	* @}
emilmont	77:869cf507173a	498	*/
emilmont	77:869cf507173a	499
emilmont	77:869cf507173a	500
emilmont	77:869cf507173a	501	/** @defgroup SPI_I2S_flags_definition
emilmont	77:869cf507173a	502	* @{
emilmont	77:869cf507173a	503	*/
emilmont	77:869cf507173a	504
emilmont	77:869cf507173a	505	#define SPI_I2S_FLAG_RXNE SPI_SR_RXNE
emilmont	77:869cf507173a	506	#define SPI_I2S_FLAG_TXE SPI_SR_TXE
emilmont	77:869cf507173a	507	#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
emilmont	77:869cf507173a	508	#define I2S_FLAG_UDR SPI_SR_UDR
emilmont	77:869cf507173a	509	#define SPI_FLAG_CRCERR SPI_SR_CRCERR
emilmont	77:869cf507173a	510	#define SPI_FLAG_MODF SPI_SR_MODF
emilmont	77:869cf507173a	511	#define SPI_I2S_FLAG_OVR SPI_SR_OVR
emilmont	77:869cf507173a	512	#define SPI_I2S_FLAG_BSY SPI_SR_BSY
emilmont	77:869cf507173a	513	#define SPI_I2S_FLAG_FRE SPI_SR_FRE
emilmont	77:869cf507173a	514
emilmont	77:869cf507173a	515
emilmont	77:869cf507173a	516
emilmont	77:869cf507173a	517	#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
emilmont	77:869cf507173a	518	#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) \|\| ((FLAG) == SPI_I2S_FLAG_OVR) \|\| \
emilmont	77:869cf507173a	519	((FLAG) == SPI_FLAG_MODF) \|\| ((FLAG) == SPI_FLAG_CRCERR) \|\| \
emilmont	77:869cf507173a	520	((FLAG) == SPI_I2S_FLAG_TXE) \|\| ((FLAG) == SPI_I2S_FLAG_RXNE)\|\| \
emilmont	77:869cf507173a	521	((FLAG) == SPI_I2S_FLAG_FRE)\|\| ((FLAG) == I2S_FLAG_CHSIDE)\|\| \
emilmont	77:869cf507173a	522	((FLAG) == I2S_FLAG_UDR))
emilmont	77:869cf507173a	523	/**
emilmont	77:869cf507173a	524	* @}
emilmont	77:869cf507173a	525	*/
emilmont	77:869cf507173a	526
emilmont	77:869cf507173a	527	/** @defgroup SPI_CRC_polynomial
emilmont	77:869cf507173a	528	* @{
emilmont	77:869cf507173a	529	*/
emilmont	77:869cf507173a	530
emilmont	77:869cf507173a	531	#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
emilmont	77:869cf507173a	532	/**
emilmont	77:869cf507173a	533	* @}
emilmont	77:869cf507173a	534	*/
emilmont	77:869cf507173a	535
emilmont	77:869cf507173a	536	/**
emilmont	77:869cf507173a	537	* @}
emilmont	77:869cf507173a	538	*/
emilmont	77:869cf507173a	539
emilmont	77:869cf507173a	540	/* Exported macro ------------------------------------------------------------*/
emilmont	77:869cf507173a	541	/* Exported functions ------------------------------------------------------- */
emilmont	77:869cf507173a	542
emilmont	77:869cf507173a	543	/* Initialization and Configuration functions *********************************/
emilmont	77:869cf507173a	544	void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
emilmont	77:869cf507173a	545	void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
emilmont	77:869cf507173a	546	void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); /!< Not applicable for STM32F030 devices /
emilmont	77:869cf507173a	547	void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
emilmont	77:869cf507173a	548	void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); /!< Not applicable for STM32F030 devices /
emilmont	77:869cf507173a	549	void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
emilmont	77:869cf507173a	550	void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
emilmont	77:869cf507173a	551	void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
emilmont	77:869cf507173a	552	void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); /!< Not applicable for STM32F030 devices /
emilmont	77:869cf507173a	553	void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
emilmont	77:869cf507173a	554	void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
emilmont	77:869cf507173a	555	void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
emilmont	77:869cf507173a	556	void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
emilmont	77:869cf507173a	557	void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
emilmont	77:869cf507173a	558
emilmont	77:869cf507173a	559	/* Data transfers functions ***************************************************/
emilmont	77:869cf507173a	560	void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
emilmont	77:869cf507173a	561	void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
emilmont	77:869cf507173a	562	uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
emilmont	77:869cf507173a	563	uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
emilmont	77:869cf507173a	564
emilmont	77:869cf507173a	565	/* Hardware CRC Calculation functions *****************************************/
emilmont	77:869cf507173a	566	void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
emilmont	77:869cf507173a	567	void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
emilmont	77:869cf507173a	568	void SPI_TransmitCRC(SPI_TypeDef* SPIx);
emilmont	77:869cf507173a	569	uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
emilmont	77:869cf507173a	570	uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
emilmont	77:869cf507173a	571
emilmont	77:869cf507173a	572	/* DMA transfers management functions *****************************************/
emilmont	77:869cf507173a	573	void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
emilmont	77:869cf507173a	574	void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
emilmont	77:869cf507173a	575
emilmont	77:869cf507173a	576	/* Interrupts and flags management functions **********************************/
emilmont	77:869cf507173a	577	void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
emilmont	77:869cf507173a	578	uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
emilmont	77:869cf507173a	579	uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
emilmont	77:869cf507173a	580	FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
emilmont	77:869cf507173a	581	void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
emilmont	77:869cf507173a	582	ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
emilmont	77:869cf507173a	583
emilmont	77:869cf507173a	584	#ifdef __cplusplus
emilmont	77:869cf507173a	585	}
emilmont	77:869cf507173a	586	#endif
emilmont	77:869cf507173a	587
emilmont	77:869cf507173a	588	#endif /__STM32F0XX_SPI_H /
emilmont	77:869cf507173a	589
emilmont	77:869cf507173a	590	/**
emilmont	77:869cf507173a	591	* @}
emilmont	77:869cf507173a	592	*/
emilmont	77:869cf507173a	593
emilmont	77:869cf507173a	594	/**
emilmont	77:869cf507173a	595	* @}
emilmont	77:869cf507173a	596	*/
emilmont	77:869cf507173a	597
emilmont	77:869cf507173a	598	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/