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TARGET_NRF51_DK/core_cm0.h@91:031413cf7a89, 2014-10-29 (annotated)

Committer:
Kojto
Date:
Wed Oct 29 11:02:04 2014 +0000
Revision:
91:031413cf7a89
Child:
110:165afa46840b
Release 91 of the mbed library



Changes:



- RBLAB_NANO - new target addition

- NRF51_DK - new target addition

- NRF51_DONGLE - new target addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 91:031413cf7a89 1 /**************************************************************************//**
Kojto 91:031413cf7a89 2 * @file core_cm0.h
Kojto 91:031413cf7a89 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 91:031413cf7a89 4 * @version V3.20
Kojto 91:031413cf7a89 5 * @date 25. February 2013
Kojto 91:031413cf7a89 6 *
Kojto 91:031413cf7a89 7 * @note
Kojto 91:031413cf7a89 8 *
Kojto 91:031413cf7a89 9 ******************************************************************************/
Kojto 91:031413cf7a89 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 91:031413cf7a89 11
Kojto 91:031413cf7a89 12 All rights reserved.
Kojto 91:031413cf7a89 13 Redistribution and use in source and binary forms, with or without
Kojto 91:031413cf7a89 14 modification, are permitted provided that the following conditions are met:
Kojto 91:031413cf7a89 15 - Redistributions of source code must retain the above copyright
Kojto 91:031413cf7a89 16 notice, this list of conditions and the following disclaimer.
Kojto 91:031413cf7a89 17 - Redistributions in binary form must reproduce the above copyright
Kojto 91:031413cf7a89 18 notice, this list of conditions and the following disclaimer in the
Kojto 91:031413cf7a89 19 documentation and/or other materials provided with the distribution.
Kojto 91:031413cf7a89 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 91:031413cf7a89 21 to endorse or promote products derived from this software without
Kojto 91:031413cf7a89 22 specific prior written permission.
Kojto 91:031413cf7a89 23 *
Kojto 91:031413cf7a89 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 91:031413cf7a89 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 91:031413cf7a89 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 91:031413cf7a89 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 91:031413cf7a89 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 91:031413cf7a89 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 91:031413cf7a89 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 91:031413cf7a89 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 91:031413cf7a89 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 91:031413cf7a89 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 91:031413cf7a89 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 91:031413cf7a89 35 ---------------------------------------------------------------------------*/
Kojto 91:031413cf7a89 36
Kojto 91:031413cf7a89 37
Kojto 91:031413cf7a89 38 #if defined ( __ICCARM__ )
Kojto 91:031413cf7a89 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 91:031413cf7a89 40 #endif
Kojto 91:031413cf7a89 41
Kojto 91:031413cf7a89 42 #ifdef __cplusplus
Kojto 91:031413cf7a89 43 extern "C" {
Kojto 91:031413cf7a89 44 #endif
Kojto 91:031413cf7a89 45
Kojto 91:031413cf7a89 46 #ifndef __CORE_CM0_H_GENERIC
Kojto 91:031413cf7a89 47 #define __CORE_CM0_H_GENERIC
Kojto 91:031413cf7a89 48
Kojto 91:031413cf7a89 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 91:031413cf7a89 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 91:031413cf7a89 51
Kojto 91:031413cf7a89 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 91:031413cf7a89 53 Function definitions in header files are used to allow 'inlining'.
Kojto 91:031413cf7a89 54
Kojto 91:031413cf7a89 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 91:031413cf7a89 56 Unions are used for effective representation of core registers.
Kojto 91:031413cf7a89 57
Kojto 91:031413cf7a89 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 91:031413cf7a89 59 Function-like macros are used to allow more efficient code.
Kojto 91:031413cf7a89 60 */
Kojto 91:031413cf7a89 61
Kojto 91:031413cf7a89 62
Kojto 91:031413cf7a89 63 /*******************************************************************************
Kojto 91:031413cf7a89 64 * CMSIS definitions
Kojto 91:031413cf7a89 65 ******************************************************************************/
Kojto 91:031413cf7a89 66 /** \ingroup Cortex_M0
Kojto 91:031413cf7a89 67 @{
Kojto 91:031413cf7a89 68 */
Kojto 91:031413cf7a89 69
Kojto 91:031413cf7a89 70 /* CMSIS CM0 definitions */
Kojto 91:031413cf7a89 71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
Kojto 91:031413cf7a89 72 #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
Kojto 91:031413cf7a89 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
Kojto 91:031413cf7a89 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 91:031413cf7a89 75
Kojto 91:031413cf7a89 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 91:031413cf7a89 77
Kojto 91:031413cf7a89 78
Kojto 91:031413cf7a89 79 #if defined ( __CC_ARM )
Kojto 91:031413cf7a89 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 91:031413cf7a89 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 91:031413cf7a89 82 #define __STATIC_INLINE static __inline
Kojto 91:031413cf7a89 83
Kojto 91:031413cf7a89 84 #elif defined ( __ICCARM__ )
Kojto 91:031413cf7a89 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 91:031413cf7a89 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 91:031413cf7a89 87 #define __STATIC_INLINE static inline
Kojto 91:031413cf7a89 88
Kojto 91:031413cf7a89 89 #elif defined ( __GNUC__ )
Kojto 91:031413cf7a89 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 91:031413cf7a89 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 91:031413cf7a89 92 #define __STATIC_INLINE static inline
Kojto 91:031413cf7a89 93
Kojto 91:031413cf7a89 94 #elif defined ( __TASKING__ )
Kojto 91:031413cf7a89 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 91:031413cf7a89 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 91:031413cf7a89 97 #define __STATIC_INLINE static inline
Kojto 91:031413cf7a89 98
Kojto 91:031413cf7a89 99 #endif
Kojto 91:031413cf7a89 100
Kojto 91:031413cf7a89 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Kojto 91:031413cf7a89 102 */
Kojto 91:031413cf7a89 103 #define __FPU_USED 0
Kojto 91:031413cf7a89 104
Kojto 91:031413cf7a89 105 #if defined ( __CC_ARM )
Kojto 91:031413cf7a89 106 #if defined __TARGET_FPU_VFP
Kojto 91:031413cf7a89 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 91:031413cf7a89 108 #endif
Kojto 91:031413cf7a89 109
Kojto 91:031413cf7a89 110 #elif defined ( __ICCARM__ )
Kojto 91:031413cf7a89 111 #if defined __ARMVFP__
Kojto 91:031413cf7a89 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 91:031413cf7a89 113 #endif
Kojto 91:031413cf7a89 114
Kojto 91:031413cf7a89 115 #elif defined ( __GNUC__ )
Kojto 91:031413cf7a89 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 91:031413cf7a89 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 91:031413cf7a89 118 #endif
Kojto 91:031413cf7a89 119
Kojto 91:031413cf7a89 120 #elif defined ( __TASKING__ )
Kojto 91:031413cf7a89 121 #if defined __FPU_VFP__
Kojto 91:031413cf7a89 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 91:031413cf7a89 123 #endif
Kojto 91:031413cf7a89 124 #endif
Kojto 91:031413cf7a89 125
Kojto 91:031413cf7a89 126 #include <stdint.h> /* standard types definitions */
Kojto 91:031413cf7a89 127 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 91:031413cf7a89 128 #include <core_cmFunc.h> /* Core Function Access */
Kojto 91:031413cf7a89 129
Kojto 91:031413cf7a89 130 #endif /* __CORE_CM0_H_GENERIC */
Kojto 91:031413cf7a89 131
Kojto 91:031413cf7a89 132 #ifndef __CMSIS_GENERIC
Kojto 91:031413cf7a89 133
Kojto 91:031413cf7a89 134 #ifndef __CORE_CM0_H_DEPENDANT
Kojto 91:031413cf7a89 135 #define __CORE_CM0_H_DEPENDANT
Kojto 91:031413cf7a89 136
Kojto 91:031413cf7a89 137 /* check device defines and use defaults */
Kojto 91:031413cf7a89 138 #if defined __CHECK_DEVICE_DEFINES
Kojto 91:031413cf7a89 139 #ifndef __CM0_REV
Kojto 91:031413cf7a89 140 #define __CM0_REV 0x0000
Kojto 91:031413cf7a89 141 #warning "__CM0_REV not defined in device header file; using default!"
Kojto 91:031413cf7a89 142 #endif
Kojto 91:031413cf7a89 143
Kojto 91:031413cf7a89 144 #ifndef __NVIC_PRIO_BITS
Kojto 91:031413cf7a89 145 #define __NVIC_PRIO_BITS 2
Kojto 91:031413cf7a89 146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 91:031413cf7a89 147 #endif
Kojto 91:031413cf7a89 148
Kojto 91:031413cf7a89 149 #ifndef __Vendor_SysTickConfig
Kojto 91:031413cf7a89 150 #define __Vendor_SysTickConfig 0
Kojto 91:031413cf7a89 151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 91:031413cf7a89 152 #endif
Kojto 91:031413cf7a89 153 #endif
Kojto 91:031413cf7a89 154
Kojto 91:031413cf7a89 155 /* IO definitions (access restrictions to peripheral registers) */
Kojto 91:031413cf7a89 156 /**
Kojto 91:031413cf7a89 157 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 91:031413cf7a89 158
Kojto 91:031413cf7a89 159 <strong>IO Type Qualifiers</strong> are used
Kojto 91:031413cf7a89 160 \li to specify the access to peripheral variables.
Kojto 91:031413cf7a89 161 \li for automatic generation of peripheral register debug information.
Kojto 91:031413cf7a89 162 */
Kojto 91:031413cf7a89 163 #ifdef __cplusplus
Kojto 91:031413cf7a89 164 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 91:031413cf7a89 165 #else
Kojto 91:031413cf7a89 166 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 91:031413cf7a89 167 #endif
Kojto 91:031413cf7a89 168 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 91:031413cf7a89 169 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 91:031413cf7a89 170
Kojto 91:031413cf7a89 171 /*@} end of group Cortex_M0 */
Kojto 91:031413cf7a89 172
Kojto 91:031413cf7a89 173
Kojto 91:031413cf7a89 174
Kojto 91:031413cf7a89 175 /*******************************************************************************
Kojto 91:031413cf7a89 176 * Register Abstraction
Kojto 91:031413cf7a89 177 Core Register contain:
Kojto 91:031413cf7a89 178 - Core Register
Kojto 91:031413cf7a89 179 - Core NVIC Register
Kojto 91:031413cf7a89 180 - Core SCB Register
Kojto 91:031413cf7a89 181 - Core SysTick Register
Kojto 91:031413cf7a89 182 ******************************************************************************/
Kojto 91:031413cf7a89 183 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 91:031413cf7a89 184 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 91:031413cf7a89 185 */
Kojto 91:031413cf7a89 186
Kojto 91:031413cf7a89 187 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 188 \defgroup CMSIS_CORE Status and Control Registers
Kojto 91:031413cf7a89 189 \brief Core Register type definitions.
Kojto 91:031413cf7a89 190 @{
Kojto 91:031413cf7a89 191 */
Kojto 91:031413cf7a89 192
Kojto 91:031413cf7a89 193 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 91:031413cf7a89 194 */
Kojto 91:031413cf7a89 195 typedef union
Kojto 91:031413cf7a89 196 {
Kojto 91:031413cf7a89 197 struct
Kojto 91:031413cf7a89 198 {
Kojto 91:031413cf7a89 199 #if (__CORTEX_M != 0x04)
Kojto 91:031413cf7a89 200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 91:031413cf7a89 201 #else
Kojto 91:031413cf7a89 202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 91:031413cf7a89 203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 91:031413cf7a89 204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 91:031413cf7a89 205 #endif
Kojto 91:031413cf7a89 206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 91:031413cf7a89 207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 91:031413cf7a89 208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 91:031413cf7a89 209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 91:031413cf7a89 210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 91:031413cf7a89 211 } b; /*!< Structure used for bit access */
Kojto 91:031413cf7a89 212 uint32_t w; /*!< Type used for word access */
Kojto 91:031413cf7a89 213 } APSR_Type;
Kojto 91:031413cf7a89 214
Kojto 91:031413cf7a89 215
Kojto 91:031413cf7a89 216 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 91:031413cf7a89 217 */
Kojto 91:031413cf7a89 218 typedef union
Kojto 91:031413cf7a89 219 {
Kojto 91:031413cf7a89 220 struct
Kojto 91:031413cf7a89 221 {
Kojto 91:031413cf7a89 222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 91:031413cf7a89 223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 91:031413cf7a89 224 } b; /*!< Structure used for bit access */
Kojto 91:031413cf7a89 225 uint32_t w; /*!< Type used for word access */
Kojto 91:031413cf7a89 226 } IPSR_Type;
Kojto 91:031413cf7a89 227
Kojto 91:031413cf7a89 228
Kojto 91:031413cf7a89 229 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 91:031413cf7a89 230 */
Kojto 91:031413cf7a89 231 typedef union
Kojto 91:031413cf7a89 232 {
Kojto 91:031413cf7a89 233 struct
Kojto 91:031413cf7a89 234 {
Kojto 91:031413cf7a89 235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 91:031413cf7a89 236 #if (__CORTEX_M != 0x04)
Kojto 91:031413cf7a89 237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 91:031413cf7a89 238 #else
Kojto 91:031413cf7a89 239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 91:031413cf7a89 240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 91:031413cf7a89 241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 91:031413cf7a89 242 #endif
Kojto 91:031413cf7a89 243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 91:031413cf7a89 244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 91:031413cf7a89 245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 91:031413cf7a89 246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 91:031413cf7a89 247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 91:031413cf7a89 248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 91:031413cf7a89 249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 91:031413cf7a89 250 } b; /*!< Structure used for bit access */
Kojto 91:031413cf7a89 251 uint32_t w; /*!< Type used for word access */
Kojto 91:031413cf7a89 252 } xPSR_Type;
Kojto 91:031413cf7a89 253
Kojto 91:031413cf7a89 254
Kojto 91:031413cf7a89 255 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 91:031413cf7a89 256 */
Kojto 91:031413cf7a89 257 typedef union
Kojto 91:031413cf7a89 258 {
Kojto 91:031413cf7a89 259 struct
Kojto 91:031413cf7a89 260 {
Kojto 91:031413cf7a89 261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 91:031413cf7a89 262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 91:031413cf7a89 263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 91:031413cf7a89 264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 91:031413cf7a89 265 } b; /*!< Structure used for bit access */
Kojto 91:031413cf7a89 266 uint32_t w; /*!< Type used for word access */
Kojto 91:031413cf7a89 267 } CONTROL_Type;
Kojto 91:031413cf7a89 268
Kojto 91:031413cf7a89 269 /*@} end of group CMSIS_CORE */
Kojto 91:031413cf7a89 270
Kojto 91:031413cf7a89 271
Kojto 91:031413cf7a89 272 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 91:031413cf7a89 274 \brief Type definitions for the NVIC Registers
Kojto 91:031413cf7a89 275 @{
Kojto 91:031413cf7a89 276 */
Kojto 91:031413cf7a89 277
Kojto 91:031413cf7a89 278 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 91:031413cf7a89 279 */
Kojto 91:031413cf7a89 280 typedef struct
Kojto 91:031413cf7a89 281 {
Kojto 91:031413cf7a89 282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 91:031413cf7a89 283 uint32_t RESERVED0[31];
Kojto 91:031413cf7a89 284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 91:031413cf7a89 285 uint32_t RSERVED1[31];
Kojto 91:031413cf7a89 286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 91:031413cf7a89 287 uint32_t RESERVED2[31];
Kojto 91:031413cf7a89 288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 91:031413cf7a89 289 uint32_t RESERVED3[31];
Kojto 91:031413cf7a89 290 uint32_t RESERVED4[64];
Kojto 91:031413cf7a89 291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 91:031413cf7a89 292 } NVIC_Type;
Kojto 91:031413cf7a89 293
Kojto 91:031413cf7a89 294 /*@} end of group CMSIS_NVIC */
Kojto 91:031413cf7a89 295
Kojto 91:031413cf7a89 296
Kojto 91:031413cf7a89 297 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 298 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 91:031413cf7a89 299 \brief Type definitions for the System Control Block Registers
Kojto 91:031413cf7a89 300 @{
Kojto 91:031413cf7a89 301 */
Kojto 91:031413cf7a89 302
Kojto 91:031413cf7a89 303 /** \brief Structure type to access the System Control Block (SCB).
Kojto 91:031413cf7a89 304 */
Kojto 91:031413cf7a89 305 typedef struct
Kojto 91:031413cf7a89 306 {
Kojto 91:031413cf7a89 307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 91:031413cf7a89 308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 91:031413cf7a89 309 uint32_t RESERVED0;
Kojto 91:031413cf7a89 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 91:031413cf7a89 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 91:031413cf7a89 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 91:031413cf7a89 313 uint32_t RESERVED1;
Kojto 91:031413cf7a89 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 91:031413cf7a89 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 91:031413cf7a89 316 } SCB_Type;
Kojto 91:031413cf7a89 317
Kojto 91:031413cf7a89 318 /* SCB CPUID Register Definitions */
Kojto 91:031413cf7a89 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 91:031413cf7a89 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 91:031413cf7a89 321
Kojto 91:031413cf7a89 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 91:031413cf7a89 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 91:031413cf7a89 324
Kojto 91:031413cf7a89 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 91:031413cf7a89 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 91:031413cf7a89 327
Kojto 91:031413cf7a89 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 91:031413cf7a89 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 91:031413cf7a89 330
Kojto 91:031413cf7a89 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 91:031413cf7a89 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Kojto 91:031413cf7a89 333
Kojto 91:031413cf7a89 334 /* SCB Interrupt Control State Register Definitions */
Kojto 91:031413cf7a89 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 91:031413cf7a89 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 91:031413cf7a89 337
Kojto 91:031413cf7a89 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 91:031413cf7a89 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 91:031413cf7a89 340
Kojto 91:031413cf7a89 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 91:031413cf7a89 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 91:031413cf7a89 343
Kojto 91:031413cf7a89 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 91:031413cf7a89 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 91:031413cf7a89 346
Kojto 91:031413cf7a89 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 91:031413cf7a89 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 91:031413cf7a89 349
Kojto 91:031413cf7a89 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 91:031413cf7a89 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 91:031413cf7a89 352
Kojto 91:031413cf7a89 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 91:031413cf7a89 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 91:031413cf7a89 355
Kojto 91:031413cf7a89 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 91:031413cf7a89 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 91:031413cf7a89 358
Kojto 91:031413cf7a89 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 91:031413cf7a89 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 91:031413cf7a89 361
Kojto 91:031413cf7a89 362 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 91:031413cf7a89 363 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 91:031413cf7a89 364 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 91:031413cf7a89 365
Kojto 91:031413cf7a89 366 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 91:031413cf7a89 367 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 91:031413cf7a89 368
Kojto 91:031413cf7a89 369 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 91:031413cf7a89 370 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 91:031413cf7a89 371
Kojto 91:031413cf7a89 372 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 91:031413cf7a89 373 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 91:031413cf7a89 374
Kojto 91:031413cf7a89 375 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 91:031413cf7a89 376 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 91:031413cf7a89 377
Kojto 91:031413cf7a89 378 /* SCB System Control Register Definitions */
Kojto 91:031413cf7a89 379 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 91:031413cf7a89 380 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 91:031413cf7a89 381
Kojto 91:031413cf7a89 382 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 91:031413cf7a89 383 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 91:031413cf7a89 384
Kojto 91:031413cf7a89 385 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 91:031413cf7a89 386 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 91:031413cf7a89 387
Kojto 91:031413cf7a89 388 /* SCB Configuration Control Register Definitions */
Kojto 91:031413cf7a89 389 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 91:031413cf7a89 390 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 91:031413cf7a89 391
Kojto 91:031413cf7a89 392 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 91:031413cf7a89 393 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 91:031413cf7a89 394
Kojto 91:031413cf7a89 395 /* SCB System Handler Control and State Register Definitions */
Kojto 91:031413cf7a89 396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 91:031413cf7a89 397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 91:031413cf7a89 398
Kojto 91:031413cf7a89 399 /*@} end of group CMSIS_SCB */
Kojto 91:031413cf7a89 400
Kojto 91:031413cf7a89 401
Kojto 91:031413cf7a89 402 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 91:031413cf7a89 404 \brief Type definitions for the System Timer Registers.
Kojto 91:031413cf7a89 405 @{
Kojto 91:031413cf7a89 406 */
Kojto 91:031413cf7a89 407
Kojto 91:031413cf7a89 408 /** \brief Structure type to access the System Timer (SysTick).
Kojto 91:031413cf7a89 409 */
Kojto 91:031413cf7a89 410 typedef struct
Kojto 91:031413cf7a89 411 {
Kojto 91:031413cf7a89 412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 91:031413cf7a89 413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 91:031413cf7a89 414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 91:031413cf7a89 415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 91:031413cf7a89 416 } SysTick_Type;
Kojto 91:031413cf7a89 417
Kojto 91:031413cf7a89 418 /* SysTick Control / Status Register Definitions */
Kojto 91:031413cf7a89 419 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 91:031413cf7a89 420 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 91:031413cf7a89 421
Kojto 91:031413cf7a89 422 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 91:031413cf7a89 423 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 91:031413cf7a89 424
Kojto 91:031413cf7a89 425 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 91:031413cf7a89 426 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 91:031413cf7a89 427
Kojto 91:031413cf7a89 428 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 91:031413cf7a89 429 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Kojto 91:031413cf7a89 430
Kojto 91:031413cf7a89 431 /* SysTick Reload Register Definitions */
Kojto 91:031413cf7a89 432 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 91:031413cf7a89 433 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Kojto 91:031413cf7a89 434
Kojto 91:031413cf7a89 435 /* SysTick Current Register Definitions */
Kojto 91:031413cf7a89 436 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 91:031413cf7a89 437 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Kojto 91:031413cf7a89 438
Kojto 91:031413cf7a89 439 /* SysTick Calibration Register Definitions */
Kojto 91:031413cf7a89 440 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 91:031413cf7a89 441 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 91:031413cf7a89 442
Kojto 91:031413cf7a89 443 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 91:031413cf7a89 444 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 91:031413cf7a89 445
Kojto 91:031413cf7a89 446 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 91:031413cf7a89 447 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Kojto 91:031413cf7a89 448
Kojto 91:031413cf7a89 449 /*@} end of group CMSIS_SysTick */
Kojto 91:031413cf7a89 450
Kojto 91:031413cf7a89 451
Kojto 91:031413cf7a89 452 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 91:031413cf7a89 454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 91:031413cf7a89 455 are only accessible over DAP and not via processor. Therefore
Kojto 91:031413cf7a89 456 they are not covered by the Cortex-M0 header file.
Kojto 91:031413cf7a89 457 @{
Kojto 91:031413cf7a89 458 */
Kojto 91:031413cf7a89 459 /*@} end of group CMSIS_CoreDebug */
Kojto 91:031413cf7a89 460
Kojto 91:031413cf7a89 461
Kojto 91:031413cf7a89 462 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 463 \defgroup CMSIS_core_base Core Definitions
Kojto 91:031413cf7a89 464 \brief Definitions for base addresses, unions, and structures.
Kojto 91:031413cf7a89 465 @{
Kojto 91:031413cf7a89 466 */
Kojto 91:031413cf7a89 467
Kojto 91:031413cf7a89 468 /* Memory mapping of Cortex-M0 Hardware */
Kojto 91:031413cf7a89 469 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 91:031413cf7a89 470 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 91:031413cf7a89 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 91:031413cf7a89 472 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 91:031413cf7a89 473
Kojto 91:031413cf7a89 474 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 91:031413cf7a89 475 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 91:031413cf7a89 476 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 91:031413cf7a89 477
Kojto 91:031413cf7a89 478
Kojto 91:031413cf7a89 479 /*@} */
Kojto 91:031413cf7a89 480
Kojto 91:031413cf7a89 481
Kojto 91:031413cf7a89 482
Kojto 91:031413cf7a89 483 /*******************************************************************************
Kojto 91:031413cf7a89 484 * Hardware Abstraction Layer
Kojto 91:031413cf7a89 485 Core Function Interface contains:
Kojto 91:031413cf7a89 486 - Core NVIC Functions
Kojto 91:031413cf7a89 487 - Core SysTick Functions
Kojto 91:031413cf7a89 488 - Core Register Access Functions
Kojto 91:031413cf7a89 489 ******************************************************************************/
Kojto 91:031413cf7a89 490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 91:031413cf7a89 491 */
Kojto 91:031413cf7a89 492
Kojto 91:031413cf7a89 493
Kojto 91:031413cf7a89 494
Kojto 91:031413cf7a89 495 /* ########################## NVIC functions #################################### */
Kojto 91:031413cf7a89 496 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 91:031413cf7a89 497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 91:031413cf7a89 498 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 91:031413cf7a89 499 @{
Kojto 91:031413cf7a89 500 */
Kojto 91:031413cf7a89 501
Kojto 91:031413cf7a89 502 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 91:031413cf7a89 503 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 91:031413cf7a89 504 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
Kojto 91:031413cf7a89 505 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
Kojto 91:031413cf7a89 506 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
Kojto 91:031413cf7a89 507
Kojto 91:031413cf7a89 508
Kojto 91:031413cf7a89 509 /** \brief Enable External Interrupt
Kojto 91:031413cf7a89 510
Kojto 91:031413cf7a89 511 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 91:031413cf7a89 512
Kojto 91:031413cf7a89 513 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 91:031413cf7a89 514 */
Kojto 91:031413cf7a89 515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 91:031413cf7a89 516 {
Kojto 91:031413cf7a89 517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 91:031413cf7a89 518 }
Kojto 91:031413cf7a89 519
Kojto 91:031413cf7a89 520
Kojto 91:031413cf7a89 521 /** \brief Disable External Interrupt
Kojto 91:031413cf7a89 522
Kojto 91:031413cf7a89 523 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 91:031413cf7a89 524
Kojto 91:031413cf7a89 525 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 91:031413cf7a89 526 */
Kojto 91:031413cf7a89 527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 91:031413cf7a89 528 {
Kojto 91:031413cf7a89 529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 91:031413cf7a89 530 }
Kojto 91:031413cf7a89 531
Kojto 91:031413cf7a89 532
Kojto 91:031413cf7a89 533 /** \brief Get Pending Interrupt
Kojto 91:031413cf7a89 534
Kojto 91:031413cf7a89 535 The function reads the pending register in the NVIC and returns the pending bit
Kojto 91:031413cf7a89 536 for the specified interrupt.
Kojto 91:031413cf7a89 537
Kojto 91:031413cf7a89 538 \param [in] IRQn Interrupt number.
Kojto 91:031413cf7a89 539
Kojto 91:031413cf7a89 540 \return 0 Interrupt status is not pending.
Kojto 91:031413cf7a89 541 \return 1 Interrupt status is pending.
Kojto 91:031413cf7a89 542 */
Kojto 91:031413cf7a89 543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 91:031413cf7a89 544 {
Kojto 91:031413cf7a89 545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
Kojto 91:031413cf7a89 546 }
Kojto 91:031413cf7a89 547
Kojto 91:031413cf7a89 548
Kojto 91:031413cf7a89 549 /** \brief Set Pending Interrupt
Kojto 91:031413cf7a89 550
Kojto 91:031413cf7a89 551 The function sets the pending bit of an external interrupt.
Kojto 91:031413cf7a89 552
Kojto 91:031413cf7a89 553 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 91:031413cf7a89 554 */
Kojto 91:031413cf7a89 555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 91:031413cf7a89 556 {
Kojto 91:031413cf7a89 557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 91:031413cf7a89 558 }
Kojto 91:031413cf7a89 559
Kojto 91:031413cf7a89 560
Kojto 91:031413cf7a89 561 /** \brief Clear Pending Interrupt
Kojto 91:031413cf7a89 562
Kojto 91:031413cf7a89 563 The function clears the pending bit of an external interrupt.
Kojto 91:031413cf7a89 564
Kojto 91:031413cf7a89 565 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 91:031413cf7a89 566 */
Kojto 91:031413cf7a89 567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 91:031413cf7a89 568 {
Kojto 91:031413cf7a89 569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kojto 91:031413cf7a89 570 }
Kojto 91:031413cf7a89 571
Kojto 91:031413cf7a89 572
Kojto 91:031413cf7a89 573 /** \brief Set Interrupt Priority
Kojto 91:031413cf7a89 574
Kojto 91:031413cf7a89 575 The function sets the priority of an interrupt.
Kojto 91:031413cf7a89 576
Kojto 91:031413cf7a89 577 \note The priority cannot be set for every core interrupt.
Kojto 91:031413cf7a89 578
Kojto 91:031413cf7a89 579 \param [in] IRQn Interrupt number.
Kojto 91:031413cf7a89 580 \param [in] priority Priority to set.
Kojto 91:031413cf7a89 581 */
Kojto 91:031413cf7a89 582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 91:031413cf7a89 583 {
Kojto 91:031413cf7a89 584 if(IRQn < 0) {
Kojto 91:031413cf7a89 585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 91:031413cf7a89 586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 91:031413cf7a89 587 else {
Kojto 91:031413cf7a89 588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 91:031413cf7a89 589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 91:031413cf7a89 590 }
Kojto 91:031413cf7a89 591
Kojto 91:031413cf7a89 592
Kojto 91:031413cf7a89 593 /** \brief Get Interrupt Priority
Kojto 91:031413cf7a89 594
Kojto 91:031413cf7a89 595 The function reads the priority of an interrupt. The interrupt
Kojto 91:031413cf7a89 596 number can be positive to specify an external (device specific)
Kojto 91:031413cf7a89 597 interrupt, or negative to specify an internal (core) interrupt.
Kojto 91:031413cf7a89 598
Kojto 91:031413cf7a89 599
Kojto 91:031413cf7a89 600 \param [in] IRQn Interrupt number.
Kojto 91:031413cf7a89 601 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 91:031413cf7a89 602 priority bits of the microcontroller.
Kojto 91:031413cf7a89 603 */
Kojto 91:031413cf7a89 604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 91:031413cf7a89 605 {
Kojto 91:031413cf7a89 606
Kojto 91:031413cf7a89 607 if(IRQn < 0) {
Kojto 91:031413cf7a89 608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
Kojto 91:031413cf7a89 609 else {
Kojto 91:031413cf7a89 610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kojto 91:031413cf7a89 611 }
Kojto 91:031413cf7a89 612
Kojto 91:031413cf7a89 613
Kojto 91:031413cf7a89 614 /** \brief System Reset
Kojto 91:031413cf7a89 615
Kojto 91:031413cf7a89 616 The function initiates a system reset request to reset the MCU.
Kojto 91:031413cf7a89 617 */
Kojto 91:031413cf7a89 618 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 91:031413cf7a89 619 {
Kojto 91:031413cf7a89 620 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 91:031413cf7a89 621 buffered write are completed before reset */
Kojto 91:031413cf7a89 622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kojto 91:031413cf7a89 623 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 91:031413cf7a89 624 __DSB(); /* Ensure completion of memory access */
Kojto 91:031413cf7a89 625 while(1); /* wait until reset */
Kojto 91:031413cf7a89 626 }
Kojto 91:031413cf7a89 627
Kojto 91:031413cf7a89 628 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 91:031413cf7a89 629
Kojto 91:031413cf7a89 630
Kojto 91:031413cf7a89 631
Kojto 91:031413cf7a89 632 /* ################################## SysTick function ############################################ */
Kojto 91:031413cf7a89 633 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 91:031413cf7a89 634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 91:031413cf7a89 635 \brief Functions that configure the System.
Kojto 91:031413cf7a89 636 @{
Kojto 91:031413cf7a89 637 */
Kojto 91:031413cf7a89 638
Kojto 91:031413cf7a89 639 #if (__Vendor_SysTickConfig == 0)
Kojto 91:031413cf7a89 640
Kojto 91:031413cf7a89 641 /** \brief System Tick Configuration
Kojto 91:031413cf7a89 642
Kojto 91:031413cf7a89 643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 91:031413cf7a89 644 Counter is in free running mode to generate periodic interrupts.
Kojto 91:031413cf7a89 645
Kojto 91:031413cf7a89 646 \param [in] ticks Number of ticks between two interrupts.
Kojto 91:031413cf7a89 647
Kojto 91:031413cf7a89 648 \return 0 Function succeeded.
Kojto 91:031413cf7a89 649 \return 1 Function failed.
Kojto 91:031413cf7a89 650
Kojto 91:031413cf7a89 651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 91:031413cf7a89 652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 91:031413cf7a89 653 must contain a vendor-specific implementation of this function.
Kojto 91:031413cf7a89 654
Kojto 91:031413cf7a89 655 */
Kojto 91:031413cf7a89 656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 91:031413cf7a89 657 {
Kojto 91:031413cf7a89 658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kojto 91:031413cf7a89 659
Kojto 91:031413cf7a89 660 SysTick->LOAD = ticks - 1; /* set reload register */
Kojto 91:031413cf7a89 661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Kojto 91:031413cf7a89 662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kojto 91:031413cf7a89 663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 91:031413cf7a89 664 SysTick_CTRL_TICKINT_Msk |
Kojto 91:031413cf7a89 665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 91:031413cf7a89 666 return (0); /* Function successful */
Kojto 91:031413cf7a89 667 }
Kojto 91:031413cf7a89 668
Kojto 91:031413cf7a89 669 #endif
Kojto 91:031413cf7a89 670
Kojto 91:031413cf7a89 671 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 91:031413cf7a89 672
Kojto 91:031413cf7a89 673
Kojto 91:031413cf7a89 674
Kojto 91:031413cf7a89 675
Kojto 91:031413cf7a89 676 #endif /* __CORE_CM0_H_DEPENDANT */
Kojto 91:031413cf7a89 677
Kojto 91:031413cf7a89 678 #endif /* __CMSIS_GENERIC */
Kojto 91:031413cf7a89 679
Kojto 91:031413cf7a89 680 #ifdef __cplusplus
Kojto 91:031413cf7a89 681 }
Kojto 91:031413cf7a89 682 #endif