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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_NXP/TARGET_LPC176X/spi_api.c@440:8a0b45cd594f, 2014-12-16 (annotated)

Committer:
mbed_official
Date:
Tue Dec 16 08:15:08 2014 +0000
Revision:
440:8a0b45cd594f
Parent:
285:31249416b6f9
Child:
552:a1b9575155a3
Synchronized with git revision 67fbbf0b635d0c0d93fbe433306c537c2ad206aa



Full URL: https://github.com/mbedmicro/mbed/commit/67fbbf0b635d0c0d93fbe433306c537c2ad206aa/



Targets: nrf51 - updating app_timer.c from Norid'c SDKv7.1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
mbed_official 227:7bd0639b8911 16 #include "mbed_assert.h"
emilmont 10:3bc89ef62ce7 17 #include <math.h>
emilmont 10:3bc89ef62ce7 18
emilmont 10:3bc89ef62ce7 19 #include "spi_api.h"
emilmont 10:3bc89ef62ce7 20 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 21 #include "pinmap.h"
mbed_official 285:31249416b6f9 22 #include "mbed_error.h"
emilmont 10:3bc89ef62ce7 23
emilmont 10:3bc89ef62ce7 24 static const PinMap PinMap_SPI_SCLK[] = {
emilmont 10:3bc89ef62ce7 25 {P0_7 , SPI_1, 2},
emilmont 10:3bc89ef62ce7 26 {P0_15, SPI_0, 2},
emilmont 10:3bc89ef62ce7 27 {P1_20, SPI_0, 3},
emilmont 10:3bc89ef62ce7 28 {P1_31, SPI_1, 2},
emilmont 10:3bc89ef62ce7 29 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 30 };
emilmont 10:3bc89ef62ce7 31
emilmont 10:3bc89ef62ce7 32 static const PinMap PinMap_SPI_MOSI[] = {
emilmont 10:3bc89ef62ce7 33 {P0_9 , SPI_1, 2},
emilmont 10:3bc89ef62ce7 34 {P0_13, SPI_1, 2},
emilmont 10:3bc89ef62ce7 35 {P0_18, SPI_0, 2},
emilmont 10:3bc89ef62ce7 36 {P1_24, SPI_0, 3},
emilmont 10:3bc89ef62ce7 37 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 38 };
emilmont 10:3bc89ef62ce7 39
emilmont 10:3bc89ef62ce7 40 static const PinMap PinMap_SPI_MISO[] = {
emilmont 10:3bc89ef62ce7 41 {P0_8 , SPI_1, 2},
emilmont 10:3bc89ef62ce7 42 {P0_12, SPI_1, 2},
emilmont 10:3bc89ef62ce7 43 {P0_17, SPI_0, 2},
emilmont 10:3bc89ef62ce7 44 {P1_23, SPI_0, 3},
emilmont 10:3bc89ef62ce7 45 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 46 };
emilmont 10:3bc89ef62ce7 47
emilmont 10:3bc89ef62ce7 48 static const PinMap PinMap_SPI_SSEL[] = {
emilmont 10:3bc89ef62ce7 49 {P0_6 , SPI_1, 2},
emilmont 10:3bc89ef62ce7 50 {P0_11, SPI_1, 2},
emilmont 10:3bc89ef62ce7 51 {P0_16, SPI_0, 2},
emilmont 10:3bc89ef62ce7 52 {P1_21, SPI_0, 3},
emilmont 10:3bc89ef62ce7 53 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 54 };
emilmont 10:3bc89ef62ce7 55
emilmont 10:3bc89ef62ce7 56 static inline int ssp_disable(spi_t *obj);
emilmont 10:3bc89ef62ce7 57 static inline int ssp_enable(spi_t *obj);
emilmont 10:3bc89ef62ce7 58
emilmont 10:3bc89ef62ce7 59 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
emilmont 10:3bc89ef62ce7 60 // determine the SPI to use
emilmont 10:3bc89ef62ce7 61 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
emilmont 10:3bc89ef62ce7 62 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
emilmont 10:3bc89ef62ce7 63 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
emilmont 10:3bc89ef62ce7 64 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
emilmont 10:3bc89ef62ce7 65 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
emilmont 10:3bc89ef62ce7 66 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
emilmont 10:3bc89ef62ce7 67 obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
mbed_official 227:7bd0639b8911 68 MBED_ASSERT((int)obj->spi != NC);
emilmont 10:3bc89ef62ce7 69
emilmont 10:3bc89ef62ce7 70 // enable power and clocking
emilmont 10:3bc89ef62ce7 71 switch ((int)obj->spi) {
emilmont 10:3bc89ef62ce7 72 case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
emilmont 10:3bc89ef62ce7 73 case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
emilmont 10:3bc89ef62ce7 74 }
emilmont 10:3bc89ef62ce7 75
emilmont 10:3bc89ef62ce7 76 // set default format and frequency
emilmont 10:3bc89ef62ce7 77 if (ssel == NC) {
emilmont 10:3bc89ef62ce7 78 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
emilmont 10:3bc89ef62ce7 79 } else {
emilmont 10:3bc89ef62ce7 80 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
emilmont 10:3bc89ef62ce7 81 }
emilmont 10:3bc89ef62ce7 82 spi_frequency(obj, 1000000);
emilmont 10:3bc89ef62ce7 83
emilmont 10:3bc89ef62ce7 84 // enable the ssp channel
emilmont 10:3bc89ef62ce7 85 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 86
emilmont 10:3bc89ef62ce7 87 // pin out the spi pins
emilmont 10:3bc89ef62ce7 88 pinmap_pinout(mosi, PinMap_SPI_MOSI);
emilmont 10:3bc89ef62ce7 89 pinmap_pinout(miso, PinMap_SPI_MISO);
emilmont 10:3bc89ef62ce7 90 pinmap_pinout(sclk, PinMap_SPI_SCLK);
emilmont 10:3bc89ef62ce7 91 if (ssel != NC) {
emilmont 10:3bc89ef62ce7 92 pinmap_pinout(ssel, PinMap_SPI_SSEL);
emilmont 10:3bc89ef62ce7 93 }
emilmont 10:3bc89ef62ce7 94 }
emilmont 10:3bc89ef62ce7 95
emilmont 10:3bc89ef62ce7 96 void spi_free(spi_t *obj) {}
emilmont 10:3bc89ef62ce7 97
emilmont 10:3bc89ef62ce7 98 void spi_format(spi_t *obj, int bits, int mode, int slave) {
emilmont 10:3bc89ef62ce7 99 ssp_disable(obj);
mbed_official 227:7bd0639b8911 100 MBED_ASSERT(((bits >= 4) && (bits <= 16)) && (mode >= 0 && mode <= 3));
emilmont 10:3bc89ef62ce7 101
emilmont 10:3bc89ef62ce7 102 int polarity = (mode & 0x2) ? 1 : 0;
emilmont 10:3bc89ef62ce7 103 int phase = (mode & 0x1) ? 1 : 0;
emilmont 10:3bc89ef62ce7 104
emilmont 10:3bc89ef62ce7 105 // set it up
emilmont 10:3bc89ef62ce7 106 int DSS = bits - 1; // DSS (data select size)
emilmont 10:3bc89ef62ce7 107 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
emilmont 10:3bc89ef62ce7 108 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
emilmont 10:3bc89ef62ce7 109
emilmont 10:3bc89ef62ce7 110 int FRF = 0; // FRF (frame format) = SPI
emilmont 10:3bc89ef62ce7 111 uint32_t tmp = obj->spi->CR0;
emilmont 10:3bc89ef62ce7 112 tmp &= ~(0xFFFF);
emilmont 10:3bc89ef62ce7 113 tmp |= DSS << 0
emilmont 10:3bc89ef62ce7 114 | FRF << 4
emilmont 10:3bc89ef62ce7 115 | SPO << 6
emilmont 10:3bc89ef62ce7 116 | SPH << 7;
emilmont 10:3bc89ef62ce7 117 obj->spi->CR0 = tmp;
emilmont 10:3bc89ef62ce7 118
emilmont 10:3bc89ef62ce7 119 tmp = obj->spi->CR1;
emilmont 10:3bc89ef62ce7 120 tmp &= ~(0xD);
emilmont 10:3bc89ef62ce7 121 tmp |= 0 << 0 // LBM - loop back mode - off
emilmont 10:3bc89ef62ce7 122 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
emilmont 10:3bc89ef62ce7 123 | 0 << 3; // SOD - slave output disable - na
emilmont 10:3bc89ef62ce7 124 obj->spi->CR1 = tmp;
emilmont 10:3bc89ef62ce7 125
emilmont 10:3bc89ef62ce7 126 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 127 }
emilmont 10:3bc89ef62ce7 128
emilmont 10:3bc89ef62ce7 129 void spi_frequency(spi_t *obj, int hz) {
emilmont 10:3bc89ef62ce7 130 ssp_disable(obj);
emilmont 10:3bc89ef62ce7 131
emilmont 10:3bc89ef62ce7 132 // setup the spi clock diveder to /1
emilmont 10:3bc89ef62ce7 133 switch ((int)obj->spi) {
emilmont 10:3bc89ef62ce7 134 case SPI_0:
emilmont 10:3bc89ef62ce7 135 LPC_SC->PCLKSEL1 &= ~(3 << 10);
emilmont 10:3bc89ef62ce7 136 LPC_SC->PCLKSEL1 |= (1 << 10);
emilmont 10:3bc89ef62ce7 137 break;
emilmont 10:3bc89ef62ce7 138 case SPI_1:
emilmont 10:3bc89ef62ce7 139 LPC_SC->PCLKSEL0 &= ~(3 << 20);
emilmont 10:3bc89ef62ce7 140 LPC_SC->PCLKSEL0 |= (1 << 20);
emilmont 10:3bc89ef62ce7 141 break;
emilmont 10:3bc89ef62ce7 142 }
emilmont 10:3bc89ef62ce7 143
emilmont 10:3bc89ef62ce7 144 uint32_t PCLK = SystemCoreClock;
emilmont 10:3bc89ef62ce7 145
emilmont 10:3bc89ef62ce7 146 int prescaler;
emilmont 10:3bc89ef62ce7 147
emilmont 10:3bc89ef62ce7 148 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
emilmont 10:3bc89ef62ce7 149 int prescale_hz = PCLK / prescaler;
emilmont 10:3bc89ef62ce7 150
emilmont 10:3bc89ef62ce7 151 // calculate the divider
emilmont 10:3bc89ef62ce7 152 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
emilmont 10:3bc89ef62ce7 153
emilmont 10:3bc89ef62ce7 154 // check we can support the divider
emilmont 10:3bc89ef62ce7 155 if (divider < 256) {
emilmont 10:3bc89ef62ce7 156 // prescaler
emilmont 10:3bc89ef62ce7 157 obj->spi->CPSR = prescaler;
emilmont 10:3bc89ef62ce7 158
emilmont 10:3bc89ef62ce7 159 // divider
emilmont 10:3bc89ef62ce7 160 obj->spi->CR0 &= ~(0xFFFF << 8);
emilmont 10:3bc89ef62ce7 161 obj->spi->CR0 |= (divider - 1) << 8;
emilmont 10:3bc89ef62ce7 162 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 163 return;
emilmont 10:3bc89ef62ce7 164 }
emilmont 10:3bc89ef62ce7 165 }
emilmont 10:3bc89ef62ce7 166 error("Couldn't setup requested SPI frequency");
emilmont 10:3bc89ef62ce7 167 }
emilmont 10:3bc89ef62ce7 168
emilmont 10:3bc89ef62ce7 169 static inline int ssp_disable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 170 return obj->spi->CR1 &= ~(1 << 1);
emilmont 10:3bc89ef62ce7 171 }
emilmont 10:3bc89ef62ce7 172
emilmont 10:3bc89ef62ce7 173 static inline int ssp_enable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 174 return obj->spi->CR1 |= (1 << 1);
emilmont 10:3bc89ef62ce7 175 }
emilmont 10:3bc89ef62ce7 176
emilmont 10:3bc89ef62ce7 177 static inline int ssp_readable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 178 return obj->spi->SR & (1 << 2);
emilmont 10:3bc89ef62ce7 179 }
emilmont 10:3bc89ef62ce7 180
emilmont 10:3bc89ef62ce7 181 static inline int ssp_writeable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 182 return obj->spi->SR & (1 << 1);
emilmont 10:3bc89ef62ce7 183 }
emilmont 10:3bc89ef62ce7 184
emilmont 10:3bc89ef62ce7 185 static inline void ssp_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 186 while (!ssp_writeable(obj));
emilmont 10:3bc89ef62ce7 187 obj->spi->DR = value;
emilmont 10:3bc89ef62ce7 188 }
emilmont 10:3bc89ef62ce7 189
emilmont 10:3bc89ef62ce7 190 static inline int ssp_read(spi_t *obj) {
emilmont 10:3bc89ef62ce7 191 while (!ssp_readable(obj));
emilmont 10:3bc89ef62ce7 192 return obj->spi->DR;
emilmont 10:3bc89ef62ce7 193 }
emilmont 10:3bc89ef62ce7 194
emilmont 10:3bc89ef62ce7 195 static inline int ssp_busy(spi_t *obj) {
emilmont 10:3bc89ef62ce7 196 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
emilmont 10:3bc89ef62ce7 197 }
emilmont 10:3bc89ef62ce7 198
emilmont 10:3bc89ef62ce7 199 int spi_master_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 200 ssp_write(obj, value);
emilmont 10:3bc89ef62ce7 201 return ssp_read(obj);
emilmont 10:3bc89ef62ce7 202 }
emilmont 10:3bc89ef62ce7 203
emilmont 10:3bc89ef62ce7 204 int spi_slave_receive(spi_t *obj) {
emilmont 10:3bc89ef62ce7 205 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
mbed_official 81:a9456fdf72fa 206 }
emilmont 10:3bc89ef62ce7 207
emilmont 10:3bc89ef62ce7 208 int spi_slave_read(spi_t *obj) {
emilmont 10:3bc89ef62ce7 209 return obj->spi->DR;
emilmont 10:3bc89ef62ce7 210 }
emilmont 10:3bc89ef62ce7 211
emilmont 10:3bc89ef62ce7 212 void spi_slave_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 213 while (ssp_writeable(obj) == 0) ;
emilmont 10:3bc89ef62ce7 214 obj->spi->DR = value;
emilmont 10:3bc89ef62ce7 215 }
emilmont 10:3bc89ef62ce7 216
emilmont 10:3bc89ef62ce7 217 int spi_busy(spi_t *obj) {
emilmont 10:3bc89ef62ce7 218 return ssp_busy(obj);
emilmont 10:3bc89ef62ce7 219 }