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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_NXP/TARGET_LPC176X/pwmout_api.c@440:8a0b45cd594f, 2014-12-16 (annotated)

Committer:
mbed_official
Date:
Tue Dec 16 08:15:08 2014 +0000
Revision:
440:8a0b45cd594f
Parent:
227:7bd0639b8911 
Synchronized with git revision 67fbbf0b635d0c0d93fbe433306c537c2ad206aa



Full URL: https://github.com/mbedmicro/mbed/commit/67fbbf0b635d0c0d93fbe433306c537c2ad206aa/



Targets: nrf51 - updating app_timer.c from Norid'c SDKv7.1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
mbed_official 227:7bd0639b8911 16 #include "mbed_assert.h"
emilmont 10:3bc89ef62ce7 17 #include "pwmout_api.h"
emilmont 10:3bc89ef62ce7 18 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 19 #include "pinmap.h"
emilmont 10:3bc89ef62ce7 20
emilmont 10:3bc89ef62ce7 21 #define TCR_CNT_EN 0x00000001
emilmont 10:3bc89ef62ce7 22 #define TCR_RESET 0x00000002
emilmont 10:3bc89ef62ce7 23
emilmont 10:3bc89ef62ce7 24 // PORT ID, PWM ID, Pin function
emilmont 10:3bc89ef62ce7 25 static const PinMap PinMap_PWM[] = {
emilmont 10:3bc89ef62ce7 26 {P1_18, PWM_1, 2},
emilmont 10:3bc89ef62ce7 27 {P1_20, PWM_2, 2},
emilmont 10:3bc89ef62ce7 28 {P1_21, PWM_3, 2},
emilmont 10:3bc89ef62ce7 29 {P1_23, PWM_4, 2},
emilmont 10:3bc89ef62ce7 30 {P1_24, PWM_5, 2},
emilmont 10:3bc89ef62ce7 31 {P1_26, PWM_6, 2},
emilmont 10:3bc89ef62ce7 32 {P2_0 , PWM_1, 1},
emilmont 10:3bc89ef62ce7 33 {P2_1 , PWM_2, 1},
emilmont 10:3bc89ef62ce7 34 {P2_2 , PWM_3, 1},
emilmont 10:3bc89ef62ce7 35 {P2_3 , PWM_4, 1},
emilmont 10:3bc89ef62ce7 36 {P2_4 , PWM_5, 1},
emilmont 10:3bc89ef62ce7 37 {P2_5 , PWM_6, 1},
emilmont 10:3bc89ef62ce7 38 {P3_25, PWM_2, 3},
emilmont 10:3bc89ef62ce7 39 {P3_26, PWM_3, 3},
emilmont 10:3bc89ef62ce7 40 {NC, NC, 0}
emilmont 10:3bc89ef62ce7 41 };
emilmont 10:3bc89ef62ce7 42
emilmont 10:3bc89ef62ce7 43 __IO uint32_t *PWM_MATCH[] = {
emilmont 10:3bc89ef62ce7 44 &(LPC_PWM1->MR0),
emilmont 10:3bc89ef62ce7 45 &(LPC_PWM1->MR1),
emilmont 10:3bc89ef62ce7 46 &(LPC_PWM1->MR2),
emilmont 10:3bc89ef62ce7 47 &(LPC_PWM1->MR3),
emilmont 10:3bc89ef62ce7 48 &(LPC_PWM1->MR4),
emilmont 10:3bc89ef62ce7 49 &(LPC_PWM1->MR5),
emilmont 10:3bc89ef62ce7 50 &(LPC_PWM1->MR6)
emilmont 10:3bc89ef62ce7 51 };
emilmont 10:3bc89ef62ce7 52
emilmont 10:3bc89ef62ce7 53 #define TCR_PWM_EN 0x00000008
emilmont 10:3bc89ef62ce7 54
emilmont 10:3bc89ef62ce7 55 static unsigned int pwm_clock_mhz;
emilmont 10:3bc89ef62ce7 56
emilmont 10:3bc89ef62ce7 57 void pwmout_init(pwmout_t* obj, PinName pin) {
emilmont 10:3bc89ef62ce7 58 // determine the channel
emilmont 10:3bc89ef62ce7 59 PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
mbed_official 227:7bd0639b8911 60 MBED_ASSERT(pwm != (PWMName)NC);
mbed_official 227:7bd0639b8911 61
emilmont 10:3bc89ef62ce7 62 obj->pwm = pwm;
emilmont 10:3bc89ef62ce7 63 obj->MR = PWM_MATCH[pwm];
emilmont 10:3bc89ef62ce7 64
emilmont 10:3bc89ef62ce7 65 // ensure the power is on
emilmont 10:3bc89ef62ce7 66 LPC_SC->PCONP |= 1 << 6;
emilmont 10:3bc89ef62ce7 67
emilmont 10:3bc89ef62ce7 68 // ensure clock to /4
emilmont 10:3bc89ef62ce7 69 LPC_SC->PCLKSEL0 &= ~(0x3 << 12); // pclk = /4
emilmont 10:3bc89ef62ce7 70 LPC_PWM1->PR = 0; // no pre-scale
emilmont 10:3bc89ef62ce7 71
emilmont 10:3bc89ef62ce7 72 // ensure single PWM mode
emilmont 10:3bc89ef62ce7 73 LPC_PWM1->MCR = 1 << 1; // reset TC on match 0
emilmont 10:3bc89ef62ce7 74
emilmont 10:3bc89ef62ce7 75 // enable the specific PWM output
emilmont 10:3bc89ef62ce7 76 LPC_PWM1->PCR |= 1 << (8 + pwm);
emilmont 10:3bc89ef62ce7 77
emilmont 10:3bc89ef62ce7 78 pwm_clock_mhz = SystemCoreClock / 4000000;
emilmont 10:3bc89ef62ce7 79
emilmont 10:3bc89ef62ce7 80 // default to 20ms: standard for servos, and fine for e.g. brightness control
emilmont 10:3bc89ef62ce7 81 pwmout_period_ms(obj, 20);
emilmont 10:3bc89ef62ce7 82 pwmout_write (obj, 0);
emilmont 10:3bc89ef62ce7 83
emilmont 10:3bc89ef62ce7 84 // Wire pinout
emilmont 10:3bc89ef62ce7 85 pinmap_pinout(pin, PinMap_PWM);
emilmont 10:3bc89ef62ce7 86 }
emilmont 10:3bc89ef62ce7 87
emilmont 10:3bc89ef62ce7 88 void pwmout_free(pwmout_t* obj) {
emilmont 10:3bc89ef62ce7 89 // [TODO]
emilmont 10:3bc89ef62ce7 90 }
emilmont 10:3bc89ef62ce7 91
emilmont 10:3bc89ef62ce7 92 void pwmout_write(pwmout_t* obj, float value) {
emilmont 10:3bc89ef62ce7 93 if (value < 0.0f) {
emilmont 10:3bc89ef62ce7 94 value = 0.0;
emilmont 10:3bc89ef62ce7 95 } else if (value > 1.0f) {
emilmont 10:3bc89ef62ce7 96 value = 1.0;
emilmont 10:3bc89ef62ce7 97 }
emilmont 10:3bc89ef62ce7 98
emilmont 10:3bc89ef62ce7 99 // set channel match to percentage
emilmont 10:3bc89ef62ce7 100 uint32_t v = (uint32_t)((float)(LPC_PWM1->MR0) * value);
emilmont 10:3bc89ef62ce7 101
emilmont 10:3bc89ef62ce7 102 // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
emilmont 10:3bc89ef62ce7 103 if (v == LPC_PWM1->MR0) {
emilmont 10:3bc89ef62ce7 104 v++;
emilmont 10:3bc89ef62ce7 105 }
emilmont 10:3bc89ef62ce7 106
emilmont 10:3bc89ef62ce7 107 *obj->MR = v;
emilmont 10:3bc89ef62ce7 108
emilmont 10:3bc89ef62ce7 109 // accept on next period start
emilmont 10:3bc89ef62ce7 110 LPC_PWM1->LER |= 1 << obj->pwm;
emilmont 10:3bc89ef62ce7 111 }
emilmont 10:3bc89ef62ce7 112
emilmont 10:3bc89ef62ce7 113 float pwmout_read(pwmout_t* obj) {
emilmont 10:3bc89ef62ce7 114 float v = (float)(*obj->MR) / (float)(LPC_PWM1->MR0);
emilmont 10:3bc89ef62ce7 115 return (v > 1.0f) ? (1.0f) : (v);
emilmont 10:3bc89ef62ce7 116 }
emilmont 10:3bc89ef62ce7 117
emilmont 10:3bc89ef62ce7 118 void pwmout_period(pwmout_t* obj, float seconds) {
emilmont 10:3bc89ef62ce7 119 pwmout_period_us(obj, seconds * 1000000.0f);
emilmont 10:3bc89ef62ce7 120 }
emilmont 10:3bc89ef62ce7 121
emilmont 10:3bc89ef62ce7 122 void pwmout_period_ms(pwmout_t* obj, int ms) {
emilmont 10:3bc89ef62ce7 123 pwmout_period_us(obj, ms * 1000);
emilmont 10:3bc89ef62ce7 124 }
emilmont 10:3bc89ef62ce7 125
emilmont 10:3bc89ef62ce7 126 // Set the PWM period, keeping the duty cycle the same.
emilmont 10:3bc89ef62ce7 127 void pwmout_period_us(pwmout_t* obj, int us) {
emilmont 10:3bc89ef62ce7 128 // calculate number of ticks
emilmont 10:3bc89ef62ce7 129 uint32_t ticks = pwm_clock_mhz * us;
emilmont 10:3bc89ef62ce7 130
emilmont 10:3bc89ef62ce7 131 // set reset
emilmont 10:3bc89ef62ce7 132 LPC_PWM1->TCR = TCR_RESET;
emilmont 10:3bc89ef62ce7 133
emilmont 10:3bc89ef62ce7 134 // set the global match register
emilmont 10:3bc89ef62ce7 135 LPC_PWM1->MR0 = ticks;
emilmont 10:3bc89ef62ce7 136
emilmont 10:3bc89ef62ce7 137 // Scale the pulse width to preserve the duty ratio
emilmont 10:3bc89ef62ce7 138 if (LPC_PWM1->MR0 > 0) {
emilmont 10:3bc89ef62ce7 139 *obj->MR = (*obj->MR * ticks) / LPC_PWM1->MR0;
emilmont 10:3bc89ef62ce7 140 }
emilmont 10:3bc89ef62ce7 141
emilmont 10:3bc89ef62ce7 142 // set the channel latch to update value at next period start
emilmont 10:3bc89ef62ce7 143 LPC_PWM1->LER |= 1 << 0;
emilmont 10:3bc89ef62ce7 144
emilmont 10:3bc89ef62ce7 145 // enable counter and pwm, clear reset
emilmont 10:3bc89ef62ce7 146 LPC_PWM1->TCR = TCR_CNT_EN | TCR_PWM_EN;
emilmont 10:3bc89ef62ce7 147 }
emilmont 10:3bc89ef62ce7 148
emilmont 10:3bc89ef62ce7 149 void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
emilmont 10:3bc89ef62ce7 150 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
emilmont 10:3bc89ef62ce7 151 }
emilmont 10:3bc89ef62ce7 152
emilmont 10:3bc89ef62ce7 153 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
emilmont 10:3bc89ef62ce7 154 pwmout_pulsewidth_us(obj, ms * 1000);
emilmont 10:3bc89ef62ce7 155 }
emilmont 10:3bc89ef62ce7 156
emilmont 10:3bc89ef62ce7 157 void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
emilmont 10:3bc89ef62ce7 158 // calculate number of ticks
emilmont 10:3bc89ef62ce7 159 uint32_t v = pwm_clock_mhz * us;
emilmont 10:3bc89ef62ce7 160
emilmont 10:3bc89ef62ce7 161 // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
emilmont 10:3bc89ef62ce7 162 if (v == LPC_PWM1->MR0) {
emilmont 10:3bc89ef62ce7 163 v++;
emilmont 10:3bc89ef62ce7 164 }
emilmont 10:3bc89ef62ce7 165
emilmont 10:3bc89ef62ce7 166 // set the match register value
emilmont 10:3bc89ef62ce7 167 *obj->MR = v;
emilmont 10:3bc89ef62ce7 168
emilmont 10:3bc89ef62ce7 169 // set the channel latch to update value at next period start
emilmont 10:3bc89ef62ce7 170 LPC_PWM1->LER |= 1 << obj->pwm;
emilmont 10:3bc89ef62ce7 171 }