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targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h@501:36015dec7d16, 2015-04-07 (annotated)

Committer:: mbed_official
Date:: Tue Apr 07 06:45:07 2015 +0100
Revision:: 501:36015dec7d16
Parent:: 270:e2babe29baf8

Synchronized with git revision 40d3a79298f37284b863f90e33e261986340964e

Full URL: https://github.com/mbedmicro/mbed/commit/40d3a79298f37284b863f90e33e261986340964e/

fixes #984: updating to v7.1 of the Nordic SDK.

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	501:36015dec7d16	1	/* Copyright (c) 2013, Nordic Semiconductor ASA
mbed_official	501:36015dec7d16	2	* All rights reserved.
mbed_official	501:36015dec7d16	3	*
mbed_official	501:36015dec7d16	4	* Redistribution and use in source and binary forms, with or without
mbed_official	501:36015dec7d16	5	* modification, are permitted provided that the following conditions are met:
mbed_official	501:36015dec7d16	6	*
mbed_official	501:36015dec7d16	7	* * Redistributions of source code must retain the above copyright notice, this
mbed_official	501:36015dec7d16	8	* list of conditions and the following disclaimer.
mbed_official	501:36015dec7d16	9	*
mbed_official	501:36015dec7d16	10	* * Redistributions in binary form must reproduce the above copyright notice,
mbed_official	501:36015dec7d16	11	* this list of conditions and the following disclaimer in the documentation
mbed_official	501:36015dec7d16	12	* and/or other materials provided with the distribution.
mbed_official	85:e1a8e879a6a9	13	*
mbed_official	501:36015dec7d16	14	* * Neither the name of Nordic Semiconductor ASA nor the names of its
mbed_official	501:36015dec7d16	15	* contributors may be used to endorse or promote products derived from
mbed_official	501:36015dec7d16	16	* this software without specific prior written permission.
mbed_official	85:e1a8e879a6a9	17	*
mbed_official	501:36015dec7d16	18	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	501:36015dec7d16	19	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	501:36015dec7d16	20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	501:36015dec7d16	21	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	501:36015dec7d16	22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	501:36015dec7d16	23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	501:36015dec7d16	24	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	501:36015dec7d16	25	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	501:36015dec7d16	26	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	501:36015dec7d16	27	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	85:e1a8e879a6a9	28	*
mbed_official	85:e1a8e879a6a9	29	*/
mbed_official	85:e1a8e879a6a9	30	#ifndef __NRF51_BITS_H
mbed_official	85:e1a8e879a6a9	31	#define __NRF51_BITS_H
mbed_official	85:e1a8e879a6a9	32
mbed_official	85:e1a8e879a6a9	33	/lint ++flb "Enter library region /
mbed_official	85:e1a8e879a6a9	34
mbed_official	501:36015dec7d16	35	#include <core_cm0.h>
mbed_official	85:e1a8e879a6a9	36
mbed_official	85:e1a8e879a6a9	37	/* Peripheral: AAR */
mbed_official	85:e1a8e879a6a9	38	/* Description: Accelerated Address Resolver. */
mbed_official	85:e1a8e879a6a9	39
mbed_official	85:e1a8e879a6a9	40	/* Register: AAR_INTENSET */
mbed_official	85:e1a8e879a6a9	41	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	42
mbed_official	85:e1a8e879a6a9	43	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
mbed_official	85:e1a8e879a6a9	44	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
mbed_official	85:e1a8e879a6a9	45	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
mbed_official	85:e1a8e879a6a9	46	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	47	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	48	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	49
mbed_official	85:e1a8e879a6a9	50	/* Bit 1 : Enable interrupt on RESOLVED event. */
mbed_official	85:e1a8e879a6a9	51	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
mbed_official	85:e1a8e879a6a9	52	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
mbed_official	85:e1a8e879a6a9	53	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	54	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	55	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	56
mbed_official	85:e1a8e879a6a9	57	/* Bit 0 : Enable interrupt on END event. */
mbed_official	85:e1a8e879a6a9	58	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
mbed_official	85:e1a8e879a6a9	59	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
mbed_official	85:e1a8e879a6a9	60	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	61	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	62	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	63
mbed_official	85:e1a8e879a6a9	64	/* Register: AAR_INTENCLR */
mbed_official	85:e1a8e879a6a9	65	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	66
mbed_official	85:e1a8e879a6a9	67	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
mbed_official	85:e1a8e879a6a9	68	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
mbed_official	85:e1a8e879a6a9	69	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
mbed_official	85:e1a8e879a6a9	70	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	71	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	72	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	73
mbed_official	85:e1a8e879a6a9	74	/* Bit 1 : Disable interrupt on RESOLVED event. */
mbed_official	85:e1a8e879a6a9	75	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
mbed_official	85:e1a8e879a6a9	76	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
mbed_official	85:e1a8e879a6a9	77	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	78	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	79	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	80
mbed_official	85:e1a8e879a6a9	81	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
mbed_official	85:e1a8e879a6a9	82	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
mbed_official	85:e1a8e879a6a9	83	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
mbed_official	85:e1a8e879a6a9	84	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	85	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	86	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	87
mbed_official	85:e1a8e879a6a9	88	/* Register: AAR_STATUS */
mbed_official	85:e1a8e879a6a9	89	/* Description: Resolution status. */
mbed_official	85:e1a8e879a6a9	90
mbed_official	85:e1a8e879a6a9	91	/* Bits 3..0 : The IRK used last time an address was resolved. */
mbed_official	85:e1a8e879a6a9	92	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
mbed_official	85:e1a8e879a6a9	93	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
mbed_official	85:e1a8e879a6a9	94
mbed_official	85:e1a8e879a6a9	95	/* Register: AAR_ENABLE */
mbed_official	85:e1a8e879a6a9	96	/* Description: Enable AAR. */
mbed_official	85:e1a8e879a6a9	97
mbed_official	85:e1a8e879a6a9	98	/* Bits 1..0 : Enable AAR. */
mbed_official	85:e1a8e879a6a9	99	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
mbed_official	85:e1a8e879a6a9	100	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
mbed_official	85:e1a8e879a6a9	101	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
mbed_official	85:e1a8e879a6a9	102	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
mbed_official	85:e1a8e879a6a9	103
mbed_official	85:e1a8e879a6a9	104	/* Register: AAR_NIRK */
mbed_official	85:e1a8e879a6a9	105	/* Description: Number of Identity root Keys in the IRK data structure. */
mbed_official	85:e1a8e879a6a9	106
mbed_official	85:e1a8e879a6a9	107	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
mbed_official	85:e1a8e879a6a9	108	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
mbed_official	85:e1a8e879a6a9	109	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
mbed_official	85:e1a8e879a6a9	110
mbed_official	85:e1a8e879a6a9	111	/* Register: AAR_POWER */
mbed_official	85:e1a8e879a6a9	112	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	113
mbed_official	85:e1a8e879a6a9	114	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	115	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	116	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	117	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	118	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	119
mbed_official	85:e1a8e879a6a9	120
mbed_official	85:e1a8e879a6a9	121	/* Peripheral: ADC */
mbed_official	85:e1a8e879a6a9	122	/* Description: Analog to digital converter. */
mbed_official	85:e1a8e879a6a9	123
mbed_official	85:e1a8e879a6a9	124	/* Register: ADC_INTENSET */
mbed_official	85:e1a8e879a6a9	125	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	126
mbed_official	85:e1a8e879a6a9	127	/* Bit 0 : Enable interrupt on END event. */
mbed_official	85:e1a8e879a6a9	128	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
mbed_official	85:e1a8e879a6a9	129	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
mbed_official	85:e1a8e879a6a9	130	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	131	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	132	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	133
mbed_official	85:e1a8e879a6a9	134	/* Register: ADC_INTENCLR */
mbed_official	85:e1a8e879a6a9	135	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	136
mbed_official	85:e1a8e879a6a9	137	/* Bit 0 : Disable interrupt on END event. */
mbed_official	85:e1a8e879a6a9	138	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
mbed_official	85:e1a8e879a6a9	139	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
mbed_official	85:e1a8e879a6a9	140	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	141	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	142	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	143
mbed_official	85:e1a8e879a6a9	144	/* Register: ADC_BUSY */
mbed_official	85:e1a8e879a6a9	145	/* Description: ADC busy register. */
mbed_official	85:e1a8e879a6a9	146
mbed_official	85:e1a8e879a6a9	147	/* Bit 0 : ADC busy register. */
mbed_official	85:e1a8e879a6a9	148	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
mbed_official	85:e1a8e879a6a9	149	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
mbed_official	85:e1a8e879a6a9	150	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
mbed_official	85:e1a8e879a6a9	151	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
mbed_official	85:e1a8e879a6a9	152
mbed_official	85:e1a8e879a6a9	153	/* Register: ADC_ENABLE */
mbed_official	85:e1a8e879a6a9	154	/* Description: ADC enable. */
mbed_official	85:e1a8e879a6a9	155
mbed_official	85:e1a8e879a6a9	156	/* Bits 1..0 : ADC enable. */
mbed_official	85:e1a8e879a6a9	157	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
mbed_official	85:e1a8e879a6a9	158	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
mbed_official	85:e1a8e879a6a9	159	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
mbed_official	85:e1a8e879a6a9	160	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
mbed_official	85:e1a8e879a6a9	161
mbed_official	85:e1a8e879a6a9	162	/* Register: ADC_CONFIG */
mbed_official	85:e1a8e879a6a9	163	/* Description: ADC configuration register. */
mbed_official	85:e1a8e879a6a9	164
mbed_official	85:e1a8e879a6a9	165	/* Bits 17..16 : ADC external reference pin selection. */
mbed_official	85:e1a8e879a6a9	166	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
mbed_official	85:e1a8e879a6a9	167	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
mbed_official	85:e1a8e879a6a9	168	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
mbed_official	85:e1a8e879a6a9	169	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
mbed_official	85:e1a8e879a6a9	170	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
mbed_official	85:e1a8e879a6a9	171
mbed_official	85:e1a8e879a6a9	172	/* Bits 15..8 : ADC analog pin selection. */
mbed_official	85:e1a8e879a6a9	173	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
mbed_official	85:e1a8e879a6a9	174	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
mbed_official	85:e1a8e879a6a9	175	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
mbed_official	85:e1a8e879a6a9	176	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
mbed_official	85:e1a8e879a6a9	177	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
mbed_official	85:e1a8e879a6a9	178	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
mbed_official	85:e1a8e879a6a9	179	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
mbed_official	85:e1a8e879a6a9	180	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
mbed_official	85:e1a8e879a6a9	181	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
mbed_official	85:e1a8e879a6a9	182	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
mbed_official	85:e1a8e879a6a9	183	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
mbed_official	85:e1a8e879a6a9	184
mbed_official	85:e1a8e879a6a9	185	/* Bits 6..5 : ADC reference selection. */
mbed_official	85:e1a8e879a6a9	186	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
mbed_official	85:e1a8e879a6a9	187	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
mbed_official	85:e1a8e879a6a9	188	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
mbed_official	85:e1a8e879a6a9	189	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
mbed_official	85:e1a8e879a6a9	190	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
mbed_official	85:e1a8e879a6a9	191	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
mbed_official	85:e1a8e879a6a9	192
mbed_official	85:e1a8e879a6a9	193	/* Bits 4..2 : ADC input selection. */
mbed_official	85:e1a8e879a6a9	194	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
mbed_official	85:e1a8e879a6a9	195	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
mbed_official	85:e1a8e879a6a9	196	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
mbed_official	85:e1a8e879a6a9	197	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
mbed_official	85:e1a8e879a6a9	198	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
mbed_official	85:e1a8e879a6a9	199	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
mbed_official	85:e1a8e879a6a9	200	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
mbed_official	85:e1a8e879a6a9	201
mbed_official	85:e1a8e879a6a9	202	/* Bits 1..0 : ADC resolution. */
mbed_official	85:e1a8e879a6a9	203	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
mbed_official	85:e1a8e879a6a9	204	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
mbed_official	85:e1a8e879a6a9	205	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
mbed_official	85:e1a8e879a6a9	206	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
mbed_official	85:e1a8e879a6a9	207	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
mbed_official	85:e1a8e879a6a9	208
mbed_official	85:e1a8e879a6a9	209	/* Register: ADC_RESULT */
mbed_official	85:e1a8e879a6a9	210	/* Description: Result of ADC conversion. */
mbed_official	85:e1a8e879a6a9	211
mbed_official	85:e1a8e879a6a9	212	/* Bits 9..0 : Result of ADC conversion. */
mbed_official	85:e1a8e879a6a9	213	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
mbed_official	85:e1a8e879a6a9	214	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
mbed_official	85:e1a8e879a6a9	215
mbed_official	85:e1a8e879a6a9	216	/* Register: ADC_POWER */
mbed_official	85:e1a8e879a6a9	217	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	218
mbed_official	85:e1a8e879a6a9	219	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	220	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	221	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	222	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	223	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	224
mbed_official	85:e1a8e879a6a9	225
mbed_official	85:e1a8e879a6a9	226	/* Peripheral: AMLI */
mbed_official	85:e1a8e879a6a9	227	/* Description: AHB Multi-Layer Interface. */
mbed_official	85:e1a8e879a6a9	228
mbed_official	85:e1a8e879a6a9	229	/* Register: AMLI_RAMPRI_CPU0 */
mbed_official	85:e1a8e879a6a9	230	/* Description: Configurable priority configuration register for CPU0. */
mbed_official	85:e1a8e879a6a9	231
mbed_official	501:36015dec7d16	232	/* Bits 31..28 : Configuration field for RAM block 7. */
mbed_official	501:36015dec7d16	233	#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /!< Position of RAM7 field. /
mbed_official	501:36015dec7d16	234	#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /!< Bit mask of RAM7 field. /
mbed_official	501:36015dec7d16	235	#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	236	#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	237	#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	238	#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	239	#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	240	#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	241	#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	242	#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	243
mbed_official	501:36015dec7d16	244	/* Bits 27..24 : Configuration field for RAM block 6. */
mbed_official	501:36015dec7d16	245	#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /!< Position of RAM6 field. /
mbed_official	501:36015dec7d16	246	#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /!< Bit mask of RAM6 field. /
mbed_official	501:36015dec7d16	247	#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	248	#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	249	#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	250	#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	251	#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	252	#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	253	#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	254	#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	255
mbed_official	501:36015dec7d16	256	/* Bits 23..20 : Configuration field for RAM block 5. */
mbed_official	501:36015dec7d16	257	#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /!< Position of RAM5 field. /
mbed_official	501:36015dec7d16	258	#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /!< Bit mask of RAM5 field. /
mbed_official	501:36015dec7d16	259	#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	260	#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	261	#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	262	#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	263	#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	264	#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	265	#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	266	#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	267
mbed_official	501:36015dec7d16	268	/* Bits 19..16 : Configuration field for RAM block 4. */
mbed_official	501:36015dec7d16	269	#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /!< Position of RAM4 field. /
mbed_official	501:36015dec7d16	270	#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /!< Bit mask of RAM4 field. /
mbed_official	501:36015dec7d16	271	#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	272	#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	273	#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	274	#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	275	#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	276	#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	277	#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	278	#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	279
mbed_official	85:e1a8e879a6a9	280	/* Bits 15..12 : Configuration field for RAM block 3. */
mbed_official	85:e1a8e879a6a9	281	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
mbed_official	85:e1a8e879a6a9	282	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
mbed_official	501:36015dec7d16	283	#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	284	#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	285	#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	286	#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	287	#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	288	#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	289	#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	290	#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	291
mbed_official	85:e1a8e879a6a9	292	/* Bits 11..8 : Configuration field for RAM block 2. */
mbed_official	85:e1a8e879a6a9	293	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
mbed_official	85:e1a8e879a6a9	294	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
mbed_official	501:36015dec7d16	295	#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	296	#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	297	#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	298	#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	299	#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	300	#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	301	#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	302	#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	303
mbed_official	85:e1a8e879a6a9	304	/* Bits 7..4 : Configuration field for RAM block 1. */
mbed_official	85:e1a8e879a6a9	305	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
mbed_official	85:e1a8e879a6a9	306	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
mbed_official	501:36015dec7d16	307	#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	308	#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	309	#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	310	#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	311	#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	312	#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	313	#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	314	#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	315
mbed_official	85:e1a8e879a6a9	316	/* Bits 3..0 : Configuration field for RAM block 0. */
mbed_official	85:e1a8e879a6a9	317	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
mbed_official	85:e1a8e879a6a9	318	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
mbed_official	501:36015dec7d16	319	#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	320	#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	321	#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	322	#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	323	#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	324	#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	325	#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	326	#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	327
mbed_official	85:e1a8e879a6a9	328	/* Register: AMLI_RAMPRI_SPIS1 */
mbed_official	85:e1a8e879a6a9	329	/* Description: Configurable priority configuration register for SPIS1. */
mbed_official	85:e1a8e879a6a9	330
mbed_official	501:36015dec7d16	331	/* Bits 31..28 : Configuration field for RAM block 7. */
mbed_official	501:36015dec7d16	332	#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /!< Position of RAM7 field. /
mbed_official	501:36015dec7d16	333	#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /!< Bit mask of RAM7 field. /
mbed_official	501:36015dec7d16	334	#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	335	#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	336	#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	337	#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	338	#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	339	#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	340	#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	341	#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	342
mbed_official	501:36015dec7d16	343	/* Bits 27..24 : Configuration field for RAM block 6. */
mbed_official	501:36015dec7d16	344	#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /!< Position of RAM6 field. /
mbed_official	501:36015dec7d16	345	#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /!< Bit mask of RAM6 field. /
mbed_official	501:36015dec7d16	346	#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	347	#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	348	#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	349	#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	350	#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	351	#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	352	#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	353	#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	354
mbed_official	501:36015dec7d16	355	/* Bits 23..20 : Configuration field for RAM block 5. */
mbed_official	501:36015dec7d16	356	#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /!< Position of RAM5 field. /
mbed_official	501:36015dec7d16	357	#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /!< Bit mask of RAM5 field. /
mbed_official	501:36015dec7d16	358	#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	359	#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	360	#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	361	#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	362	#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	363	#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	364	#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	365	#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	366
mbed_official	501:36015dec7d16	367	/* Bits 19..16 : Configuration field for RAM block 4. */
mbed_official	501:36015dec7d16	368	#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /!< Position of RAM4 field. /
mbed_official	501:36015dec7d16	369	#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /!< Bit mask of RAM4 field. /
mbed_official	501:36015dec7d16	370	#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	371	#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	372	#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	373	#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	374	#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	375	#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	376	#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	377	#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	378
mbed_official	85:e1a8e879a6a9	379	/* Bits 15..12 : Configuration field for RAM block 3. */
mbed_official	85:e1a8e879a6a9	380	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
mbed_official	85:e1a8e879a6a9	381	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
mbed_official	501:36015dec7d16	382	#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	383	#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	384	#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	385	#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	386	#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	387	#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	388	#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	389	#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	390
mbed_official	85:e1a8e879a6a9	391	/* Bits 11..8 : Configuration field for RAM block 2. */
mbed_official	85:e1a8e879a6a9	392	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
mbed_official	85:e1a8e879a6a9	393	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
mbed_official	501:36015dec7d16	394	#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	395	#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	396	#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	397	#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	398	#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	399	#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	400	#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	401	#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	402
mbed_official	85:e1a8e879a6a9	403	/* Bits 7..4 : Configuration field for RAM block 1. */
mbed_official	85:e1a8e879a6a9	404	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
mbed_official	85:e1a8e879a6a9	405	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
mbed_official	501:36015dec7d16	406	#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	407	#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	408	#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	409	#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	410	#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	411	#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	412	#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	413	#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	414
mbed_official	85:e1a8e879a6a9	415	/* Bits 3..0 : Configuration field for RAM block 0. */
mbed_official	85:e1a8e879a6a9	416	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
mbed_official	85:e1a8e879a6a9	417	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
mbed_official	501:36015dec7d16	418	#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	419	#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	420	#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	421	#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	422	#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	423	#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	424	#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	425	#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	426
mbed_official	85:e1a8e879a6a9	427	/* Register: AMLI_RAMPRI_RADIO */
mbed_official	85:e1a8e879a6a9	428	/* Description: Configurable priority configuration register for RADIO. */
mbed_official	85:e1a8e879a6a9	429
mbed_official	501:36015dec7d16	430	/* Bits 31..28 : Configuration field for RAM block 7. */
mbed_official	501:36015dec7d16	431	#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /!< Position of RAM7 field. /
mbed_official	501:36015dec7d16	432	#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /!< Bit mask of RAM7 field. /
mbed_official	501:36015dec7d16	433	#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	434	#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	435	#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	436	#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	437	#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	438	#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	439	#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	440	#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	441
mbed_official	501:36015dec7d16	442	/* Bits 27..24 : Configuration field for RAM block 6. */
mbed_official	501:36015dec7d16	443	#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /!< Position of RAM6 field. /
mbed_official	501:36015dec7d16	444	#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /!< Bit mask of RAM6 field. /
mbed_official	501:36015dec7d16	445	#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	446	#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	447	#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	448	#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	449	#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	450	#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	451	#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	452	#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	453
mbed_official	501:36015dec7d16	454	/* Bits 23..20 : Configuration field for RAM block 5. */
mbed_official	501:36015dec7d16	455	#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /!< Position of RAM5 field. /
mbed_official	501:36015dec7d16	456	#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /!< Bit mask of RAM5 field. /
mbed_official	501:36015dec7d16	457	#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	458	#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	459	#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	460	#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	461	#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	462	#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	463	#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	464	#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	465
mbed_official	501:36015dec7d16	466	/* Bits 19..16 : Configuration field for RAM block 4. */
mbed_official	501:36015dec7d16	467	#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /!< Position of RAM4 field. /
mbed_official	501:36015dec7d16	468	#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /!< Bit mask of RAM4 field. /
mbed_official	501:36015dec7d16	469	#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	470	#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	471	#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	472	#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	473	#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	474	#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	475	#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	476	#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	477
mbed_official	85:e1a8e879a6a9	478	/* Bits 15..12 : Configuration field for RAM block 3. */
mbed_official	85:e1a8e879a6a9	479	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
mbed_official	85:e1a8e879a6a9	480	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
mbed_official	501:36015dec7d16	481	#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	482	#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	483	#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	484	#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	485	#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	486	#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	487	#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	488	#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	489
mbed_official	85:e1a8e879a6a9	490	/* Bits 11..8 : Configuration field for RAM block 2. */
mbed_official	85:e1a8e879a6a9	491	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
mbed_official	85:e1a8e879a6a9	492	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
mbed_official	501:36015dec7d16	493	#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	494	#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	495	#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	496	#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	497	#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	498	#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	499	#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	500	#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	501
mbed_official	85:e1a8e879a6a9	502	/* Bits 7..4 : Configuration field for RAM block 1. */
mbed_official	85:e1a8e879a6a9	503	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
mbed_official	85:e1a8e879a6a9	504	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
mbed_official	501:36015dec7d16	505	#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	506	#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	507	#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	508	#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	509	#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	510	#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	511	#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	512	#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	513
mbed_official	85:e1a8e879a6a9	514	/* Bits 3..0 : Configuration field for RAM block 0. */
mbed_official	85:e1a8e879a6a9	515	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
mbed_official	85:e1a8e879a6a9	516	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
mbed_official	501:36015dec7d16	517	#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	518	#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	519	#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	520	#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	521	#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	522	#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	523	#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	524	#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	525
mbed_official	85:e1a8e879a6a9	526	/* Register: AMLI_RAMPRI_ECB */
mbed_official	85:e1a8e879a6a9	527	/* Description: Configurable priority configuration register for ECB. */
mbed_official	85:e1a8e879a6a9	528
mbed_official	501:36015dec7d16	529	/* Bits 31..28 : Configuration field for RAM block 7. */
mbed_official	501:36015dec7d16	530	#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /!< Position of RAM7 field. /
mbed_official	501:36015dec7d16	531	#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /!< Bit mask of RAM7 field. /
mbed_official	501:36015dec7d16	532	#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	533	#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	534	#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	535	#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	536	#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	537	#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	538	#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	539	#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	540
mbed_official	501:36015dec7d16	541	/* Bits 27..24 : Configuration field for RAM block 6. */
mbed_official	501:36015dec7d16	542	#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /!< Position of RAM6 field. /
mbed_official	501:36015dec7d16	543	#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /!< Bit mask of RAM6 field. /
mbed_official	501:36015dec7d16	544	#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	545	#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	546	#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	547	#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	548	#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	549	#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	550	#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	551	#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	552
mbed_official	501:36015dec7d16	553	/* Bits 23..20 : Configuration field for RAM block 5. */
mbed_official	501:36015dec7d16	554	#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /!< Position of RAM5 field. /
mbed_official	501:36015dec7d16	555	#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /!< Bit mask of RAM5 field. /
mbed_official	501:36015dec7d16	556	#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	557	#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	558	#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	559	#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	560	#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	561	#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	562	#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	563	#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	564
mbed_official	501:36015dec7d16	565	/* Bits 19..16 : Configuration field for RAM block 4. */
mbed_official	501:36015dec7d16	566	#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /!< Position of RAM4 field. /
mbed_official	501:36015dec7d16	567	#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /!< Bit mask of RAM4 field. /
mbed_official	501:36015dec7d16	568	#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	569	#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	570	#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	571	#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	572	#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	573	#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	574	#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	575	#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	576
mbed_official	85:e1a8e879a6a9	577	/* Bits 15..12 : Configuration field for RAM block 3. */
mbed_official	85:e1a8e879a6a9	578	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
mbed_official	85:e1a8e879a6a9	579	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
mbed_official	501:36015dec7d16	580	#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	581	#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	582	#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	583	#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	584	#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	585	#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	586	#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	587	#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	588
mbed_official	85:e1a8e879a6a9	589	/* Bits 11..8 : Configuration field for RAM block 2. */
mbed_official	85:e1a8e879a6a9	590	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
mbed_official	85:e1a8e879a6a9	591	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
mbed_official	501:36015dec7d16	592	#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	593	#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	594	#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	595	#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	596	#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	597	#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	598	#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	599	#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	600
mbed_official	85:e1a8e879a6a9	601	/* Bits 7..4 : Configuration field for RAM block 1. */
mbed_official	85:e1a8e879a6a9	602	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
mbed_official	85:e1a8e879a6a9	603	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
mbed_official	501:36015dec7d16	604	#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	605	#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	606	#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	607	#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	608	#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	609	#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	610	#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	611	#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	612
mbed_official	85:e1a8e879a6a9	613	/* Bits 3..0 : Configuration field for RAM block 0. */
mbed_official	85:e1a8e879a6a9	614	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
mbed_official	85:e1a8e879a6a9	615	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
mbed_official	501:36015dec7d16	616	#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	617	#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	618	#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	619	#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	620	#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	621	#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	622	#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	623	#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	624
mbed_official	85:e1a8e879a6a9	625	/* Register: AMLI_RAMPRI_CCM */
mbed_official	85:e1a8e879a6a9	626	/* Description: Configurable priority configuration register for CCM. */
mbed_official	85:e1a8e879a6a9	627
mbed_official	501:36015dec7d16	628	/* Bits 31..28 : Configuration field for RAM block 7. */
mbed_official	501:36015dec7d16	629	#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /!< Position of RAM7 field. /
mbed_official	501:36015dec7d16	630	#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /!< Bit mask of RAM7 field. /
mbed_official	501:36015dec7d16	631	#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	632	#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	633	#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	634	#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	635	#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	636	#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	637	#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	638	#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	639
mbed_official	501:36015dec7d16	640	/* Bits 27..24 : Configuration field for RAM block 6. */
mbed_official	501:36015dec7d16	641	#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /!< Position of RAM6 field. /
mbed_official	501:36015dec7d16	642	#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /!< Bit mask of RAM6 field. /
mbed_official	501:36015dec7d16	643	#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	644	#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	645	#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	646	#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	647	#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	648	#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	649	#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	650	#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	651
mbed_official	501:36015dec7d16	652	/* Bits 23..20 : Configuration field for RAM block 5. */
mbed_official	501:36015dec7d16	653	#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /!< Position of RAM5 field. /
mbed_official	501:36015dec7d16	654	#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /!< Bit mask of RAM5 field. /
mbed_official	501:36015dec7d16	655	#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	656	#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	657	#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	658	#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	659	#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	660	#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	661	#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	662	#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	663
mbed_official	501:36015dec7d16	664	/* Bits 19..16 : Configuration field for RAM block 4. */
mbed_official	501:36015dec7d16	665	#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /!< Position of RAM4 field. /
mbed_official	501:36015dec7d16	666	#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /!< Bit mask of RAM4 field. /
mbed_official	501:36015dec7d16	667	#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	668	#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	669	#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	670	#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	671	#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	672	#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	673	#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	674	#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	675
mbed_official	85:e1a8e879a6a9	676	/* Bits 15..12 : Configuration field for RAM block 3. */
mbed_official	85:e1a8e879a6a9	677	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
mbed_official	85:e1a8e879a6a9	678	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
mbed_official	501:36015dec7d16	679	#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	680	#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	681	#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	682	#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	683	#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	684	#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	685	#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	686	#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	687
mbed_official	85:e1a8e879a6a9	688	/* Bits 11..8 : Configuration field for RAM block 2. */
mbed_official	85:e1a8e879a6a9	689	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
mbed_official	85:e1a8e879a6a9	690	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
mbed_official	501:36015dec7d16	691	#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	692	#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	693	#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	694	#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	695	#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	696	#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	697	#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	698	#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	699
mbed_official	85:e1a8e879a6a9	700	/* Bits 7..4 : Configuration field for RAM block 1. */
mbed_official	85:e1a8e879a6a9	701	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
mbed_official	85:e1a8e879a6a9	702	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
mbed_official	501:36015dec7d16	703	#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	704	#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	705	#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	706	#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	707	#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	708	#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	709	#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	710	#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	711
mbed_official	85:e1a8e879a6a9	712	/* Bits 3..0 : Configuration field for RAM block 0. */
mbed_official	85:e1a8e879a6a9	713	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
mbed_official	85:e1a8e879a6a9	714	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
mbed_official	501:36015dec7d16	715	#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	716	#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	717	#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	718	#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	719	#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	720	#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	721	#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	722	#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	723
mbed_official	85:e1a8e879a6a9	724	/* Register: AMLI_RAMPRI_AAR */
mbed_official	85:e1a8e879a6a9	725	/* Description: Configurable priority configuration register for AAR. */
mbed_official	85:e1a8e879a6a9	726
mbed_official	501:36015dec7d16	727	/* Bits 31..28 : Configuration field for RAM block 7. */
mbed_official	501:36015dec7d16	728	#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /!< Position of RAM7 field. /
mbed_official	501:36015dec7d16	729	#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /!< Bit mask of RAM7 field. /
mbed_official	501:36015dec7d16	730	#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	731	#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	732	#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	733	#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	734	#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	735	#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	736	#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	737	#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	738
mbed_official	501:36015dec7d16	739	/* Bits 27..24 : Configuration field for RAM block 6. */
mbed_official	501:36015dec7d16	740	#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /!< Position of RAM6 field. /
mbed_official	501:36015dec7d16	741	#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /!< Bit mask of RAM6 field. /
mbed_official	501:36015dec7d16	742	#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	743	#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	744	#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	745	#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	746	#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	747	#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	748	#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	749	#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	750
mbed_official	501:36015dec7d16	751	/* Bits 23..20 : Configuration field for RAM block 5. */
mbed_official	501:36015dec7d16	752	#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /!< Position of RAM5 field. /
mbed_official	501:36015dec7d16	753	#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /!< Bit mask of RAM5 field. /
mbed_official	501:36015dec7d16	754	#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	755	#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	756	#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	757	#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	758	#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	759	#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	760	#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	761	#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	762
mbed_official	501:36015dec7d16	763	/* Bits 19..16 : Configuration field for RAM block 4. */
mbed_official	501:36015dec7d16	764	#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /!< Position of RAM4 field. /
mbed_official	501:36015dec7d16	765	#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /!< Bit mask of RAM4 field. /
mbed_official	501:36015dec7d16	766	#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	767	#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	768	#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	769	#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	770	#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	771	#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	772	#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	773	#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	501:36015dec7d16	774
mbed_official	85:e1a8e879a6a9	775	/* Bits 15..12 : Configuration field for RAM block 3. */
mbed_official	85:e1a8e879a6a9	776	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
mbed_official	85:e1a8e879a6a9	777	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
mbed_official	501:36015dec7d16	778	#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	779	#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	780	#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	781	#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	782	#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	783	#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	784	#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	785	#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	786
mbed_official	85:e1a8e879a6a9	787	/* Bits 11..8 : Configuration field for RAM block 2. */
mbed_official	85:e1a8e879a6a9	788	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
mbed_official	85:e1a8e879a6a9	789	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
mbed_official	501:36015dec7d16	790	#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	791	#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	792	#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	793	#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	794	#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	795	#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	796	#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	797	#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	798
mbed_official	85:e1a8e879a6a9	799	/* Bits 7..4 : Configuration field for RAM block 1. */
mbed_official	85:e1a8e879a6a9	800	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
mbed_official	85:e1a8e879a6a9	801	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
mbed_official	501:36015dec7d16	802	#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	803	#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	804	#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	805	#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	806	#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	807	#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	808	#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	809	#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	810
mbed_official	85:e1a8e879a6a9	811	/* Bits 3..0 : Configuration field for RAM block 0. */
mbed_official	85:e1a8e879a6a9	812	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
mbed_official	85:e1a8e879a6a9	813	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
mbed_official	501:36015dec7d16	814	#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /!< Priority 0. /
mbed_official	501:36015dec7d16	815	#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /!< Priority 2. /
mbed_official	501:36015dec7d16	816	#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /!< Priority 4. /
mbed_official	501:36015dec7d16	817	#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /!< Priority 6. /
mbed_official	501:36015dec7d16	818	#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /!< Priority 8. /
mbed_official	501:36015dec7d16	819	#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /!< Priority 10. /
mbed_official	501:36015dec7d16	820	#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /!< Priority 12. /
mbed_official	501:36015dec7d16	821	#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /!< Priority 14. /
mbed_official	85:e1a8e879a6a9	822
mbed_official	85:e1a8e879a6a9	823	/* Peripheral: CCM */
mbed_official	85:e1a8e879a6a9	824	/* Description: AES CCM Mode Encryption. */
mbed_official	85:e1a8e879a6a9	825
mbed_official	85:e1a8e879a6a9	826	/* Register: CCM_SHORTS */
mbed_official	501:36015dec7d16	827	/* Description: Shortcuts for the CCM. */
mbed_official	501:36015dec7d16	828
mbed_official	501:36015dec7d16	829	/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
mbed_official	85:e1a8e879a6a9	830	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
mbed_official	85:e1a8e879a6a9	831	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
mbed_official	85:e1a8e879a6a9	832	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	833	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	834
mbed_official	85:e1a8e879a6a9	835	/* Register: CCM_INTENSET */
mbed_official	85:e1a8e879a6a9	836	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	837
mbed_official	85:e1a8e879a6a9	838	/* Bit 2 : Enable interrupt on ERROR event. */
mbed_official	85:e1a8e879a6a9	839	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
mbed_official	85:e1a8e879a6a9	840	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
mbed_official	85:e1a8e879a6a9	841	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	842	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	843	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	844
mbed_official	85:e1a8e879a6a9	845	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
mbed_official	85:e1a8e879a6a9	846	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
mbed_official	85:e1a8e879a6a9	847	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
mbed_official	85:e1a8e879a6a9	848	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	849	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	850	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	851
mbed_official	85:e1a8e879a6a9	852	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
mbed_official	85:e1a8e879a6a9	853	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
mbed_official	85:e1a8e879a6a9	854	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
mbed_official	85:e1a8e879a6a9	855	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	856	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	857	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	858
mbed_official	85:e1a8e879a6a9	859	/* Register: CCM_INTENCLR */
mbed_official	85:e1a8e879a6a9	860	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	861
mbed_official	85:e1a8e879a6a9	862	/* Bit 2 : Disable interrupt on ERROR event. */
mbed_official	85:e1a8e879a6a9	863	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
mbed_official	85:e1a8e879a6a9	864	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
mbed_official	85:e1a8e879a6a9	865	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	866	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	867	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	868
mbed_official	85:e1a8e879a6a9	869	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
mbed_official	85:e1a8e879a6a9	870	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
mbed_official	85:e1a8e879a6a9	871	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
mbed_official	85:e1a8e879a6a9	872	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	873	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	874	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	875
mbed_official	85:e1a8e879a6a9	876	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
mbed_official	85:e1a8e879a6a9	877	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
mbed_official	85:e1a8e879a6a9	878	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
mbed_official	85:e1a8e879a6a9	879	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	880	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	881	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	882
mbed_official	85:e1a8e879a6a9	883	/* Register: CCM_MICSTATUS */
mbed_official	85:e1a8e879a6a9	884	/* Description: CCM RX MIC check result. */
mbed_official	85:e1a8e879a6a9	885
mbed_official	85:e1a8e879a6a9	886	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
mbed_official	85:e1a8e879a6a9	887	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
mbed_official	85:e1a8e879a6a9	888	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
mbed_official	85:e1a8e879a6a9	889	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
mbed_official	85:e1a8e879a6a9	890	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
mbed_official	85:e1a8e879a6a9	891
mbed_official	85:e1a8e879a6a9	892	/* Register: CCM_ENABLE */
mbed_official	85:e1a8e879a6a9	893	/* Description: CCM enable. */
mbed_official	85:e1a8e879a6a9	894
mbed_official	85:e1a8e879a6a9	895	/* Bits 1..0 : CCM enable. */
mbed_official	85:e1a8e879a6a9	896	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
mbed_official	85:e1a8e879a6a9	897	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
mbed_official	85:e1a8e879a6a9	898	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
mbed_official	85:e1a8e879a6a9	899	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
mbed_official	85:e1a8e879a6a9	900
mbed_official	85:e1a8e879a6a9	901	/* Register: CCM_MODE */
mbed_official	85:e1a8e879a6a9	902	/* Description: Operation mode. */
mbed_official	85:e1a8e879a6a9	903
mbed_official	85:e1a8e879a6a9	904	/* Bit 0 : CCM mode operation. */
mbed_official	85:e1a8e879a6a9	905	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
mbed_official	85:e1a8e879a6a9	906	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
mbed_official	85:e1a8e879a6a9	907	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
mbed_official	85:e1a8e879a6a9	908	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
mbed_official	85:e1a8e879a6a9	909
mbed_official	85:e1a8e879a6a9	910	/* Register: CCM_POWER */
mbed_official	85:e1a8e879a6a9	911	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	912
mbed_official	85:e1a8e879a6a9	913	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	914	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	915	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	916	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	917	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	918
mbed_official	85:e1a8e879a6a9	919
mbed_official	85:e1a8e879a6a9	920	/* Peripheral: CLOCK */
mbed_official	85:e1a8e879a6a9	921	/* Description: Clock control. */
mbed_official	85:e1a8e879a6a9	922
mbed_official	85:e1a8e879a6a9	923	/* Register: CLOCK_INTENSET */
mbed_official	85:e1a8e879a6a9	924	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	925
mbed_official	85:e1a8e879a6a9	926	/* Bit 4 : Enable interrupt on CTTO event. */
mbed_official	85:e1a8e879a6a9	927	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
mbed_official	85:e1a8e879a6a9	928	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
mbed_official	85:e1a8e879a6a9	929	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	930	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	931	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	932
mbed_official	85:e1a8e879a6a9	933	/* Bit 3 : Enable interrupt on DONE event. */
mbed_official	85:e1a8e879a6a9	934	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
mbed_official	85:e1a8e879a6a9	935	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
mbed_official	85:e1a8e879a6a9	936	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	937	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	938	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	939
mbed_official	85:e1a8e879a6a9	940	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
mbed_official	85:e1a8e879a6a9	941	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
mbed_official	85:e1a8e879a6a9	942	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
mbed_official	85:e1a8e879a6a9	943	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	944	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	945	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	946
mbed_official	85:e1a8e879a6a9	947	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
mbed_official	85:e1a8e879a6a9	948	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
mbed_official	85:e1a8e879a6a9	949	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
mbed_official	85:e1a8e879a6a9	950	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	951	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	952	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	953
mbed_official	85:e1a8e879a6a9	954	/* Register: CLOCK_INTENCLR */
mbed_official	85:e1a8e879a6a9	955	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	956
mbed_official	85:e1a8e879a6a9	957	/* Bit 4 : Disable interrupt on CTTO event. */
mbed_official	85:e1a8e879a6a9	958	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
mbed_official	85:e1a8e879a6a9	959	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
mbed_official	85:e1a8e879a6a9	960	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	961	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	962	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	963
mbed_official	85:e1a8e879a6a9	964	/* Bit 3 : Disable interrupt on DONE event. */
mbed_official	85:e1a8e879a6a9	965	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
mbed_official	85:e1a8e879a6a9	966	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
mbed_official	85:e1a8e879a6a9	967	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	968	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	969	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	970
mbed_official	85:e1a8e879a6a9	971	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
mbed_official	85:e1a8e879a6a9	972	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
mbed_official	85:e1a8e879a6a9	973	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
mbed_official	85:e1a8e879a6a9	974	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	975	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	976	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	977
mbed_official	85:e1a8e879a6a9	978	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
mbed_official	85:e1a8e879a6a9	979	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
mbed_official	85:e1a8e879a6a9	980	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
mbed_official	85:e1a8e879a6a9	981	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	982	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	983	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	984
mbed_official	501:36015dec7d16	985	/* Register: CLOCK_HFCLKRUN */
mbed_official	501:36015dec7d16	986	/* Description: Task HFCLKSTART trigger status. */
mbed_official	501:36015dec7d16	987
mbed_official	501:36015dec7d16	988	/* Bit 0 : Task HFCLKSTART trigger status. */
mbed_official	501:36015dec7d16	989	#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
mbed_official	501:36015dec7d16	990	#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
mbed_official	501:36015dec7d16	991	#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /!< Task HFCLKSTART has not been triggered. /
mbed_official	501:36015dec7d16	992	#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /!< Task HFCLKSTART has been triggered. /
mbed_official	501:36015dec7d16	993
mbed_official	85:e1a8e879a6a9	994	/* Register: CLOCK_HFCLKSTAT */
mbed_official	85:e1a8e879a6a9	995	/* Description: High frequency clock status. */
mbed_official	85:e1a8e879a6a9	996
mbed_official	85:e1a8e879a6a9	997	/* Bit 16 : State for the HFCLK. */
mbed_official	85:e1a8e879a6a9	998	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
mbed_official	85:e1a8e879a6a9	999	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
mbed_official	85:e1a8e879a6a9	1000	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
mbed_official	85:e1a8e879a6a9	1001	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
mbed_official	85:e1a8e879a6a9	1002
mbed_official	85:e1a8e879a6a9	1003	/* Bit 0 : Active clock source for the HF clock. */
mbed_official	85:e1a8e879a6a9	1004	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
mbed_official	85:e1a8e879a6a9	1005	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
mbed_official	85:e1a8e879a6a9	1006	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
mbed_official	85:e1a8e879a6a9	1007	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
mbed_official	85:e1a8e879a6a9	1008
mbed_official	501:36015dec7d16	1009	/* Register: CLOCK_LFCLKRUN */
mbed_official	501:36015dec7d16	1010	/* Description: Task LFCLKSTART triggered status. */
mbed_official	501:36015dec7d16	1011
mbed_official	501:36015dec7d16	1012	/* Bit 0 : Task LFCLKSTART triggered status. */
mbed_official	501:36015dec7d16	1013	#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
mbed_official	501:36015dec7d16	1014	#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
mbed_official	501:36015dec7d16	1015	#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /!< Task LFCLKSTART has not been triggered. /
mbed_official	501:36015dec7d16	1016	#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /!< Task LFCLKSTART has been triggered. /
mbed_official	501:36015dec7d16	1017
mbed_official	85:e1a8e879a6a9	1018	/* Register: CLOCK_LFCLKSTAT */
mbed_official	85:e1a8e879a6a9	1019	/* Description: Low frequency clock status. */
mbed_official	85:e1a8e879a6a9	1020
mbed_official	85:e1a8e879a6a9	1021	/* Bit 16 : State for the LF clock. */
mbed_official	85:e1a8e879a6a9	1022	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
mbed_official	85:e1a8e879a6a9	1023	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
mbed_official	85:e1a8e879a6a9	1024	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
mbed_official	85:e1a8e879a6a9	1025	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
mbed_official	85:e1a8e879a6a9	1026
mbed_official	85:e1a8e879a6a9	1027	/* Bits 1..0 : Active clock source for the LF clock. */
mbed_official	85:e1a8e879a6a9	1028	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
mbed_official	85:e1a8e879a6a9	1029	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
mbed_official	85:e1a8e879a6a9	1030	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
mbed_official	85:e1a8e879a6a9	1031	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
mbed_official	85:e1a8e879a6a9	1032	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
mbed_official	85:e1a8e879a6a9	1033
mbed_official	501:36015dec7d16	1034	/* Register: CLOCK_LFCLKSRCCOPY */
mbed_official	501:36015dec7d16	1035	/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
mbed_official	501:36015dec7d16	1036
mbed_official	501:36015dec7d16	1037	/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
mbed_official	501:36015dec7d16	1038	#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /!< Position of SRC field. /
mbed_official	501:36015dec7d16	1039	#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /!< Bit mask of SRC field. /
mbed_official	501:36015dec7d16	1040	#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
mbed_official	501:36015dec7d16	1041	#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
mbed_official	501:36015dec7d16	1042	#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
mbed_official	501:36015dec7d16	1043
mbed_official	85:e1a8e879a6a9	1044	/* Register: CLOCK_LFCLKSRC */
mbed_official	85:e1a8e879a6a9	1045	/* Description: Clock source for the LFCLK clock. */
mbed_official	85:e1a8e879a6a9	1046
mbed_official	85:e1a8e879a6a9	1047	/* Bits 1..0 : Clock source. */
mbed_official	85:e1a8e879a6a9	1048	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
mbed_official	85:e1a8e879a6a9	1049	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
mbed_official	85:e1a8e879a6a9	1050	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
mbed_official	85:e1a8e879a6a9	1051	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
mbed_official	85:e1a8e879a6a9	1052	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
mbed_official	85:e1a8e879a6a9	1053
mbed_official	85:e1a8e879a6a9	1054	/* Register: CLOCK_CTIV */
mbed_official	85:e1a8e879a6a9	1055	/* Description: Calibration timer interval. */
mbed_official	85:e1a8e879a6a9	1056
mbed_official	85:e1a8e879a6a9	1057	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
mbed_official	85:e1a8e879a6a9	1058	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
mbed_official	85:e1a8e879a6a9	1059	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
mbed_official	85:e1a8e879a6a9	1060
mbed_official	85:e1a8e879a6a9	1061	/* Register: CLOCK_XTALFREQ */
mbed_official	85:e1a8e879a6a9	1062	/* Description: Crystal frequency. */
mbed_official	85:e1a8e879a6a9	1063
mbed_official	85:e1a8e879a6a9	1064	/* Bits 7..0 : External Xtal frequency selection. */
mbed_official	85:e1a8e879a6a9	1065	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
mbed_official	85:e1a8e879a6a9	1066	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
mbed_official	501:36015dec7d16	1067	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used as source for the HFCLK oscillator. /
mbed_official	501:36015dec7d16	1068	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used as source for the HFCLK oscillator. /
mbed_official	85:e1a8e879a6a9	1069
mbed_official	85:e1a8e879a6a9	1070
mbed_official	85:e1a8e879a6a9	1071	/* Peripheral: ECB */
mbed_official	85:e1a8e879a6a9	1072	/* Description: AES ECB Mode Encryption. */
mbed_official	85:e1a8e879a6a9	1073
mbed_official	85:e1a8e879a6a9	1074	/* Register: ECB_INTENSET */
mbed_official	85:e1a8e879a6a9	1075	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	1076
mbed_official	85:e1a8e879a6a9	1077	/* Bit 1 : Enable interrupt on ERRORECB event. */
mbed_official	85:e1a8e879a6a9	1078	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
mbed_official	85:e1a8e879a6a9	1079	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
mbed_official	85:e1a8e879a6a9	1080	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	1081	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	1082	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	1083
mbed_official	85:e1a8e879a6a9	1084	/* Bit 0 : Enable interrupt on ENDECB event. */
mbed_official	85:e1a8e879a6a9	1085	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
mbed_official	85:e1a8e879a6a9	1086	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
mbed_official	85:e1a8e879a6a9	1087	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	1088	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	1089	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	1090
mbed_official	85:e1a8e879a6a9	1091	/* Register: ECB_INTENCLR */
mbed_official	85:e1a8e879a6a9	1092	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	1093
mbed_official	85:e1a8e879a6a9	1094	/* Bit 1 : Disable interrupt on ERRORECB event. */
mbed_official	85:e1a8e879a6a9	1095	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
mbed_official	85:e1a8e879a6a9	1096	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
mbed_official	85:e1a8e879a6a9	1097	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	1098	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	1099	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	1100
mbed_official	85:e1a8e879a6a9	1101	/* Bit 0 : Disable interrupt on ENDECB event. */
mbed_official	85:e1a8e879a6a9	1102	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
mbed_official	85:e1a8e879a6a9	1103	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
mbed_official	85:e1a8e879a6a9	1104	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	1105	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	1106	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	1107
mbed_official	85:e1a8e879a6a9	1108	/* Register: ECB_POWER */
mbed_official	85:e1a8e879a6a9	1109	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	1110
mbed_official	85:e1a8e879a6a9	1111	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	1112	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	1113	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	1114	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	1115	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	1116
mbed_official	85:e1a8e879a6a9	1117
mbed_official	85:e1a8e879a6a9	1118	/* Peripheral: FICR */
mbed_official	85:e1a8e879a6a9	1119	/* Description: Factory Information Configuration. */
mbed_official	85:e1a8e879a6a9	1120
mbed_official	85:e1a8e879a6a9	1121	/* Register: FICR_PPFC */
mbed_official	85:e1a8e879a6a9	1122	/* Description: Pre-programmed factory code present. */
mbed_official	85:e1a8e879a6a9	1123
mbed_official	85:e1a8e879a6a9	1124	/* Bits 7..0 : Pre-programmed factory code present. */
mbed_official	85:e1a8e879a6a9	1125	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
mbed_official	85:e1a8e879a6a9	1126	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
mbed_official	85:e1a8e879a6a9	1127	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
mbed_official	85:e1a8e879a6a9	1128	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
mbed_official	85:e1a8e879a6a9	1129
mbed_official	85:e1a8e879a6a9	1130	/* Register: FICR_CONFIGID */
mbed_official	85:e1a8e879a6a9	1131	/* Description: Configuration identifier. */
mbed_official	85:e1a8e879a6a9	1132
mbed_official	85:e1a8e879a6a9	1133	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
mbed_official	85:e1a8e879a6a9	1134	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
mbed_official	85:e1a8e879a6a9	1135	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
mbed_official	85:e1a8e879a6a9	1136
mbed_official	85:e1a8e879a6a9	1137	/* Bits 15..0 : Hardware Identification Number. */
mbed_official	85:e1a8e879a6a9	1138	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
mbed_official	85:e1a8e879a6a9	1139	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
mbed_official	85:e1a8e879a6a9	1140
mbed_official	85:e1a8e879a6a9	1141	/* Register: FICR_DEVICEADDRTYPE */
mbed_official	85:e1a8e879a6a9	1142	/* Description: Device address type. */
mbed_official	85:e1a8e879a6a9	1143
mbed_official	85:e1a8e879a6a9	1144	/* Bit 0 : Device address type. */
mbed_official	85:e1a8e879a6a9	1145	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
mbed_official	85:e1a8e879a6a9	1146	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
mbed_official	85:e1a8e879a6a9	1147	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
mbed_official	85:e1a8e879a6a9	1148	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
mbed_official	85:e1a8e879a6a9	1149
mbed_official	85:e1a8e879a6a9	1150	/* Register: FICR_OVERRIDEEN */
mbed_official	85:e1a8e879a6a9	1151	/* Description: Radio calibration override enable. */
mbed_official	85:e1a8e879a6a9	1152
mbed_official	85:e1a8e879a6a9	1153	/* Bit 3 : Override default values for BLE_1Mbit mode. */
mbed_official	85:e1a8e879a6a9	1154	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
mbed_official	85:e1a8e879a6a9	1155	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
mbed_official	85:e1a8e879a6a9	1156	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
mbed_official	85:e1a8e879a6a9	1157	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
mbed_official	85:e1a8e879a6a9	1158
mbed_official	501:36015dec7d16	1159	/* Bit 0 : Override default values for NRF_1Mbit mode. */
mbed_official	501:36015dec7d16	1160	#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /!< Position of NRF_1MBIT field. /
mbed_official	501:36015dec7d16	1161	#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /!< Bit mask of NRF_1MBIT field. /
mbed_official	501:36015dec7d16	1162	#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /!< Override the default values for NRF_1Mbit mode. /
mbed_official	501:36015dec7d16	1163	#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /!< Do not override the default values for NRF_1Mbit mode. /
mbed_official	501:36015dec7d16	1164
mbed_official	501:36015dec7d16	1165	/* Register: FICR_INFO_PART */
mbed_official	501:36015dec7d16	1166	/* Description: Part code */
mbed_official	501:36015dec7d16	1167
mbed_official	501:36015dec7d16	1168	/* Bits 31..0 : Part code */
mbed_official	501:36015dec7d16	1169	#define FICR_INFO_PART_PART_Pos (0UL) /!< Position of PART field. /
mbed_official	501:36015dec7d16	1170	#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /!< Bit mask of PART field. /
mbed_official	501:36015dec7d16	1171	#define FICR_INFO_PART_PART_N51822 (0x51822UL) /!< nRF51822 /
mbed_official	501:36015dec7d16	1172	#define FICR_INFO_PART_PART_N51422 (0x51422UL) /!< nRF51422 /
mbed_official	501:36015dec7d16	1173	#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
mbed_official	501:36015dec7d16	1174
mbed_official	501:36015dec7d16	1175	/* Register: FICR_INFO_VARIANT */
mbed_official	501:36015dec7d16	1176	/* Description: Part variant */
mbed_official	501:36015dec7d16	1177
mbed_official	501:36015dec7d16	1178	/* Bits 31..0 : Part variant */
mbed_official	501:36015dec7d16	1179	#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /!< Position of VARIANT field. /
mbed_official	501:36015dec7d16	1180	#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /!< Bit mask of VARIANT field. /
mbed_official	501:36015dec7d16	1181	#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /!< nRF51-C (XLR3) /
mbed_official	501:36015dec7d16	1182	#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /!< nRF51-D (L3) /
mbed_official	501:36015dec7d16	1183	#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /!< nRF51-E (XLR3P) /
mbed_official	501:36015dec7d16	1184	#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
mbed_official	501:36015dec7d16	1185
mbed_official	501:36015dec7d16	1186	/* Register: FICR_INFO_PACKAGE */
mbed_official	501:36015dec7d16	1187	/* Description: Package option */
mbed_official	501:36015dec7d16	1188
mbed_official	501:36015dec7d16	1189	/* Bits 31..0 : Package option */
mbed_official	501:36015dec7d16	1190	#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /!< Position of PACKAGE field. /
mbed_official	501:36015dec7d16	1191	#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /!< Bit mask of PACKAGE field. /
mbed_official	501:36015dec7d16	1192	#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /!< 48-pin QFN with 31 GPIO /
mbed_official	501:36015dec7d16	1193	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /!< nRF51x22 CDxx - WLCSP 56 balls /
mbed_official	501:36015dec7d16	1194	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /!< nRF51x22 CExx - WLCSP 62 balls /
mbed_official	501:36015dec7d16	1195	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /!< nRF51x22 CFxx - WLCSP 62 balls /
mbed_official	501:36015dec7d16	1196	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /!< nRF51x22 CTxx - WLCSP 62 balls /
mbed_official	501:36015dec7d16	1197	#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
mbed_official	501:36015dec7d16	1198
mbed_official	501:36015dec7d16	1199	/* Register: FICR_INFO_RAM */
mbed_official	501:36015dec7d16	1200	/* Description: RAM variant */
mbed_official	501:36015dec7d16	1201
mbed_official	501:36015dec7d16	1202	/* Bits 31..0 : RAM variant */
mbed_official	501:36015dec7d16	1203	#define FICR_INFO_RAM_RAM_Pos (0UL) /!< Position of RAM field. /
mbed_official	501:36015dec7d16	1204	#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /!< Bit mask of RAM field. /
mbed_official	501:36015dec7d16	1205	#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
mbed_official	501:36015dec7d16	1206	#define FICR_INFO_RAM_RAM_K16 (16UL) /!< 16 kByte RAM. /
mbed_official	501:36015dec7d16	1207	#define FICR_INFO_RAM_RAM_K32 (32UL) /!< 32 kByte RAM. /
mbed_official	501:36015dec7d16	1208
mbed_official	501:36015dec7d16	1209	/* Register: FICR_INFO_FLASH */
mbed_official	501:36015dec7d16	1210	/* Description: Flash variant */
mbed_official	501:36015dec7d16	1211
mbed_official	501:36015dec7d16	1212	/* Bits 31..0 : Flash variant */
mbed_official	501:36015dec7d16	1213	#define FICR_INFO_FLASH_FLASH_Pos (0UL) /!< Position of FLASH field. /
mbed_official	501:36015dec7d16	1214	#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /!< Bit mask of FLASH field. /
mbed_official	501:36015dec7d16	1215	#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
mbed_official	501:36015dec7d16	1216	#define FICR_INFO_FLASH_FLASH_K128 (128UL) /!< 128 kByte FLASH. /
mbed_official	501:36015dec7d16	1217	#define FICR_INFO_FLASH_FLASH_K256 (256UL) /!< 256 kByte FLASH. /
mbed_official	501:36015dec7d16	1218
mbed_official	85:e1a8e879a6a9	1219
mbed_official	85:e1a8e879a6a9	1220	/* Peripheral: GPIO */
mbed_official	85:e1a8e879a6a9	1221	/* Description: General purpose input and output. */
mbed_official	85:e1a8e879a6a9	1222
mbed_official	85:e1a8e879a6a9	1223	/* Register: GPIO_OUT */
mbed_official	85:e1a8e879a6a9	1224	/* Description: Write GPIO port. */
mbed_official	85:e1a8e879a6a9	1225
mbed_official	85:e1a8e879a6a9	1226	/* Bit 31 : Pin 31. */
mbed_official	85:e1a8e879a6a9	1227	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
mbed_official	85:e1a8e879a6a9	1228	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
mbed_official	85:e1a8e879a6a9	1229	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1230	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1231
mbed_official	85:e1a8e879a6a9	1232	/* Bit 30 : Pin 30. */
mbed_official	85:e1a8e879a6a9	1233	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
mbed_official	85:e1a8e879a6a9	1234	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
mbed_official	85:e1a8e879a6a9	1235	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1236	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1237
mbed_official	85:e1a8e879a6a9	1238	/* Bit 29 : Pin 29. */
mbed_official	85:e1a8e879a6a9	1239	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
mbed_official	85:e1a8e879a6a9	1240	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
mbed_official	85:e1a8e879a6a9	1241	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1242	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1243
mbed_official	85:e1a8e879a6a9	1244	/* Bit 28 : Pin 28. */
mbed_official	85:e1a8e879a6a9	1245	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
mbed_official	85:e1a8e879a6a9	1246	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
mbed_official	85:e1a8e879a6a9	1247	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1248	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1249
mbed_official	85:e1a8e879a6a9	1250	/* Bit 27 : Pin 27. */
mbed_official	85:e1a8e879a6a9	1251	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
mbed_official	85:e1a8e879a6a9	1252	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
mbed_official	85:e1a8e879a6a9	1253	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1254	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1255
mbed_official	85:e1a8e879a6a9	1256	/* Bit 26 : Pin 26. */
mbed_official	85:e1a8e879a6a9	1257	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
mbed_official	85:e1a8e879a6a9	1258	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
mbed_official	85:e1a8e879a6a9	1259	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1260	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1261
mbed_official	85:e1a8e879a6a9	1262	/* Bit 25 : Pin 25. */
mbed_official	85:e1a8e879a6a9	1263	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
mbed_official	85:e1a8e879a6a9	1264	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
mbed_official	85:e1a8e879a6a9	1265	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1266	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1267
mbed_official	85:e1a8e879a6a9	1268	/* Bit 24 : Pin 24. */
mbed_official	85:e1a8e879a6a9	1269	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
mbed_official	85:e1a8e879a6a9	1270	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
mbed_official	85:e1a8e879a6a9	1271	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1272	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1273
mbed_official	85:e1a8e879a6a9	1274	/* Bit 23 : Pin 23. */
mbed_official	85:e1a8e879a6a9	1275	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
mbed_official	85:e1a8e879a6a9	1276	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
mbed_official	85:e1a8e879a6a9	1277	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1278	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1279
mbed_official	85:e1a8e879a6a9	1280	/* Bit 22 : Pin 22. */
mbed_official	85:e1a8e879a6a9	1281	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
mbed_official	85:e1a8e879a6a9	1282	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
mbed_official	85:e1a8e879a6a9	1283	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1284	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1285
mbed_official	85:e1a8e879a6a9	1286	/* Bit 21 : Pin 21. */
mbed_official	85:e1a8e879a6a9	1287	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
mbed_official	85:e1a8e879a6a9	1288	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
mbed_official	85:e1a8e879a6a9	1289	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1290	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1291
mbed_official	85:e1a8e879a6a9	1292	/* Bit 20 : Pin 20. */
mbed_official	85:e1a8e879a6a9	1293	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
mbed_official	85:e1a8e879a6a9	1294	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
mbed_official	85:e1a8e879a6a9	1295	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1296	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1297
mbed_official	85:e1a8e879a6a9	1298	/* Bit 19 : Pin 19. */
mbed_official	85:e1a8e879a6a9	1299	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
mbed_official	85:e1a8e879a6a9	1300	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
mbed_official	85:e1a8e879a6a9	1301	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1302	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1303
mbed_official	85:e1a8e879a6a9	1304	/* Bit 18 : Pin 18. */
mbed_official	85:e1a8e879a6a9	1305	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
mbed_official	85:e1a8e879a6a9	1306	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
mbed_official	85:e1a8e879a6a9	1307	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1308	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1309
mbed_official	85:e1a8e879a6a9	1310	/* Bit 17 : Pin 17. */
mbed_official	85:e1a8e879a6a9	1311	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
mbed_official	85:e1a8e879a6a9	1312	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
mbed_official	85:e1a8e879a6a9	1313	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1314	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1315
mbed_official	85:e1a8e879a6a9	1316	/* Bit 16 : Pin 16. */
mbed_official	85:e1a8e879a6a9	1317	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
mbed_official	85:e1a8e879a6a9	1318	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
mbed_official	85:e1a8e879a6a9	1319	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1320	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1321
mbed_official	85:e1a8e879a6a9	1322	/* Bit 15 : Pin 15. */
mbed_official	85:e1a8e879a6a9	1323	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
mbed_official	85:e1a8e879a6a9	1324	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
mbed_official	85:e1a8e879a6a9	1325	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1326	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1327
mbed_official	85:e1a8e879a6a9	1328	/* Bit 14 : Pin 14. */
mbed_official	85:e1a8e879a6a9	1329	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
mbed_official	85:e1a8e879a6a9	1330	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
mbed_official	85:e1a8e879a6a9	1331	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1332	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1333
mbed_official	85:e1a8e879a6a9	1334	/* Bit 13 : Pin 13. */
mbed_official	85:e1a8e879a6a9	1335	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
mbed_official	85:e1a8e879a6a9	1336	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
mbed_official	85:e1a8e879a6a9	1337	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1338	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1339
mbed_official	85:e1a8e879a6a9	1340	/* Bit 12 : Pin 12. */
mbed_official	85:e1a8e879a6a9	1341	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
mbed_official	85:e1a8e879a6a9	1342	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
mbed_official	85:e1a8e879a6a9	1343	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1344	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1345
mbed_official	85:e1a8e879a6a9	1346	/* Bit 11 : Pin 11. */
mbed_official	85:e1a8e879a6a9	1347	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
mbed_official	85:e1a8e879a6a9	1348	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
mbed_official	85:e1a8e879a6a9	1349	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1350	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1351
mbed_official	85:e1a8e879a6a9	1352	/* Bit 10 : Pin 10. */
mbed_official	85:e1a8e879a6a9	1353	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
mbed_official	85:e1a8e879a6a9	1354	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
mbed_official	85:e1a8e879a6a9	1355	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1356	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1357
mbed_official	85:e1a8e879a6a9	1358	/* Bit 9 : Pin 9. */
mbed_official	85:e1a8e879a6a9	1359	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
mbed_official	85:e1a8e879a6a9	1360	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
mbed_official	85:e1a8e879a6a9	1361	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1362	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1363
mbed_official	85:e1a8e879a6a9	1364	/* Bit 8 : Pin 8. */
mbed_official	85:e1a8e879a6a9	1365	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
mbed_official	85:e1a8e879a6a9	1366	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
mbed_official	85:e1a8e879a6a9	1367	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1368	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1369
mbed_official	85:e1a8e879a6a9	1370	/* Bit 7 : Pin 7. */
mbed_official	85:e1a8e879a6a9	1371	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
mbed_official	85:e1a8e879a6a9	1372	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
mbed_official	85:e1a8e879a6a9	1373	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1374	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1375
mbed_official	85:e1a8e879a6a9	1376	/* Bit 6 : Pin 6. */
mbed_official	85:e1a8e879a6a9	1377	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
mbed_official	85:e1a8e879a6a9	1378	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
mbed_official	85:e1a8e879a6a9	1379	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1380	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1381
mbed_official	85:e1a8e879a6a9	1382	/* Bit 5 : Pin 5. */
mbed_official	85:e1a8e879a6a9	1383	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
mbed_official	85:e1a8e879a6a9	1384	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
mbed_official	85:e1a8e879a6a9	1385	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1386	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1387
mbed_official	85:e1a8e879a6a9	1388	/* Bit 4 : Pin 4. */
mbed_official	85:e1a8e879a6a9	1389	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
mbed_official	85:e1a8e879a6a9	1390	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
mbed_official	85:e1a8e879a6a9	1391	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1392	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1393
mbed_official	85:e1a8e879a6a9	1394	/* Bit 3 : Pin 3. */
mbed_official	85:e1a8e879a6a9	1395	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
mbed_official	85:e1a8e879a6a9	1396	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
mbed_official	85:e1a8e879a6a9	1397	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1398	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1399
mbed_official	85:e1a8e879a6a9	1400	/* Bit 2 : Pin 2. */
mbed_official	85:e1a8e879a6a9	1401	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
mbed_official	85:e1a8e879a6a9	1402	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
mbed_official	85:e1a8e879a6a9	1403	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1404	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1405
mbed_official	85:e1a8e879a6a9	1406	/* Bit 1 : Pin 1. */
mbed_official	85:e1a8e879a6a9	1407	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
mbed_official	85:e1a8e879a6a9	1408	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
mbed_official	85:e1a8e879a6a9	1409	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1410	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1411
mbed_official	85:e1a8e879a6a9	1412	/* Bit 0 : Pin 0. */
mbed_official	85:e1a8e879a6a9	1413	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
mbed_official	85:e1a8e879a6a9	1414	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
mbed_official	85:e1a8e879a6a9	1415	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1416	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1417
mbed_official	85:e1a8e879a6a9	1418	/* Register: GPIO_OUTSET */
mbed_official	85:e1a8e879a6a9	1419	/* Description: Set individual bits in GPIO port. */
mbed_official	85:e1a8e879a6a9	1420
mbed_official	85:e1a8e879a6a9	1421	/* Bit 31 : Pin 31. */
mbed_official	85:e1a8e879a6a9	1422	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
mbed_official	85:e1a8e879a6a9	1423	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
mbed_official	85:e1a8e879a6a9	1424	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1425	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1426	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1427
mbed_official	85:e1a8e879a6a9	1428	/* Bit 30 : Pin 30. */
mbed_official	85:e1a8e879a6a9	1429	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
mbed_official	85:e1a8e879a6a9	1430	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
mbed_official	85:e1a8e879a6a9	1431	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1432	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1433	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1434
mbed_official	85:e1a8e879a6a9	1435	/* Bit 29 : Pin 29. */
mbed_official	85:e1a8e879a6a9	1436	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
mbed_official	85:e1a8e879a6a9	1437	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
mbed_official	85:e1a8e879a6a9	1438	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1439	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1440	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1441
mbed_official	85:e1a8e879a6a9	1442	/* Bit 28 : Pin 28. */
mbed_official	85:e1a8e879a6a9	1443	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
mbed_official	85:e1a8e879a6a9	1444	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
mbed_official	85:e1a8e879a6a9	1445	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1446	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1447	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1448
mbed_official	85:e1a8e879a6a9	1449	/* Bit 27 : Pin 27. */
mbed_official	85:e1a8e879a6a9	1450	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
mbed_official	85:e1a8e879a6a9	1451	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
mbed_official	85:e1a8e879a6a9	1452	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1453	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1454	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1455
mbed_official	85:e1a8e879a6a9	1456	/* Bit 26 : Pin 26. */
mbed_official	85:e1a8e879a6a9	1457	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
mbed_official	85:e1a8e879a6a9	1458	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
mbed_official	85:e1a8e879a6a9	1459	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1460	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1461	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1462
mbed_official	85:e1a8e879a6a9	1463	/* Bit 25 : Pin 25. */
mbed_official	85:e1a8e879a6a9	1464	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
mbed_official	85:e1a8e879a6a9	1465	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
mbed_official	85:e1a8e879a6a9	1466	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1467	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1468	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1469
mbed_official	85:e1a8e879a6a9	1470	/* Bit 24 : Pin 24. */
mbed_official	85:e1a8e879a6a9	1471	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
mbed_official	85:e1a8e879a6a9	1472	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
mbed_official	85:e1a8e879a6a9	1473	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1474	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1475	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1476
mbed_official	85:e1a8e879a6a9	1477	/* Bit 23 : Pin 23. */
mbed_official	85:e1a8e879a6a9	1478	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
mbed_official	85:e1a8e879a6a9	1479	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
mbed_official	85:e1a8e879a6a9	1480	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1481	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1482	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1483
mbed_official	85:e1a8e879a6a9	1484	/* Bit 22 : Pin 22. */
mbed_official	85:e1a8e879a6a9	1485	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
mbed_official	85:e1a8e879a6a9	1486	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
mbed_official	85:e1a8e879a6a9	1487	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1488	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1489	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1490
mbed_official	85:e1a8e879a6a9	1491	/* Bit 21 : Pin 21. */
mbed_official	85:e1a8e879a6a9	1492	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
mbed_official	85:e1a8e879a6a9	1493	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
mbed_official	85:e1a8e879a6a9	1494	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1495	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1496	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1497
mbed_official	85:e1a8e879a6a9	1498	/* Bit 20 : Pin 20. */
mbed_official	85:e1a8e879a6a9	1499	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
mbed_official	85:e1a8e879a6a9	1500	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
mbed_official	85:e1a8e879a6a9	1501	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1502	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1503	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1504
mbed_official	85:e1a8e879a6a9	1505	/* Bit 19 : Pin 19. */
mbed_official	85:e1a8e879a6a9	1506	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
mbed_official	85:e1a8e879a6a9	1507	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
mbed_official	85:e1a8e879a6a9	1508	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1509	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1510	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1511
mbed_official	85:e1a8e879a6a9	1512	/* Bit 18 : Pin 18. */
mbed_official	85:e1a8e879a6a9	1513	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
mbed_official	85:e1a8e879a6a9	1514	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
mbed_official	85:e1a8e879a6a9	1515	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1516	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1517	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1518
mbed_official	85:e1a8e879a6a9	1519	/* Bit 17 : Pin 17. */
mbed_official	85:e1a8e879a6a9	1520	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
mbed_official	85:e1a8e879a6a9	1521	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
mbed_official	85:e1a8e879a6a9	1522	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1523	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1524	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1525
mbed_official	85:e1a8e879a6a9	1526	/* Bit 16 : Pin 16. */
mbed_official	85:e1a8e879a6a9	1527	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
mbed_official	85:e1a8e879a6a9	1528	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
mbed_official	85:e1a8e879a6a9	1529	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1530	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1531	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1532
mbed_official	85:e1a8e879a6a9	1533	/* Bit 15 : Pin 15. */
mbed_official	85:e1a8e879a6a9	1534	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
mbed_official	85:e1a8e879a6a9	1535	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
mbed_official	85:e1a8e879a6a9	1536	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1537	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1538	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1539
mbed_official	85:e1a8e879a6a9	1540	/* Bit 14 : Pin 14. */
mbed_official	85:e1a8e879a6a9	1541	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
mbed_official	85:e1a8e879a6a9	1542	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
mbed_official	85:e1a8e879a6a9	1543	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1544	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1545	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1546
mbed_official	85:e1a8e879a6a9	1547	/* Bit 13 : Pin 13. */
mbed_official	85:e1a8e879a6a9	1548	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
mbed_official	85:e1a8e879a6a9	1549	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
mbed_official	85:e1a8e879a6a9	1550	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1551	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1552	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1553
mbed_official	85:e1a8e879a6a9	1554	/* Bit 12 : Pin 12. */
mbed_official	85:e1a8e879a6a9	1555	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
mbed_official	85:e1a8e879a6a9	1556	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
mbed_official	85:e1a8e879a6a9	1557	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1558	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1559	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1560
mbed_official	85:e1a8e879a6a9	1561	/* Bit 11 : Pin 11. */
mbed_official	85:e1a8e879a6a9	1562	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
mbed_official	85:e1a8e879a6a9	1563	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
mbed_official	85:e1a8e879a6a9	1564	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1565	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1566	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1567
mbed_official	85:e1a8e879a6a9	1568	/* Bit 10 : Pin 10. */
mbed_official	85:e1a8e879a6a9	1569	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
mbed_official	85:e1a8e879a6a9	1570	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
mbed_official	85:e1a8e879a6a9	1571	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1572	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1573	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1574
mbed_official	85:e1a8e879a6a9	1575	/* Bit 9 : Pin 9. */
mbed_official	85:e1a8e879a6a9	1576	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
mbed_official	85:e1a8e879a6a9	1577	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
mbed_official	85:e1a8e879a6a9	1578	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1579	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1580	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1581
mbed_official	85:e1a8e879a6a9	1582	/* Bit 8 : Pin 8. */
mbed_official	85:e1a8e879a6a9	1583	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
mbed_official	85:e1a8e879a6a9	1584	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
mbed_official	85:e1a8e879a6a9	1585	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1586	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1587	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1588
mbed_official	85:e1a8e879a6a9	1589	/* Bit 7 : Pin 7. */
mbed_official	85:e1a8e879a6a9	1590	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
mbed_official	85:e1a8e879a6a9	1591	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
mbed_official	85:e1a8e879a6a9	1592	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1593	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1594	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1595
mbed_official	85:e1a8e879a6a9	1596	/* Bit 6 : Pin 6. */
mbed_official	85:e1a8e879a6a9	1597	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
mbed_official	85:e1a8e879a6a9	1598	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
mbed_official	85:e1a8e879a6a9	1599	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1600	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1601	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1602
mbed_official	85:e1a8e879a6a9	1603	/* Bit 5 : Pin 5. */
mbed_official	85:e1a8e879a6a9	1604	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
mbed_official	85:e1a8e879a6a9	1605	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
mbed_official	85:e1a8e879a6a9	1606	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1607	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1608	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1609
mbed_official	85:e1a8e879a6a9	1610	/* Bit 4 : Pin 4. */
mbed_official	85:e1a8e879a6a9	1611	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
mbed_official	85:e1a8e879a6a9	1612	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
mbed_official	85:e1a8e879a6a9	1613	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1614	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1615	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1616
mbed_official	85:e1a8e879a6a9	1617	/* Bit 3 : Pin 3. */
mbed_official	85:e1a8e879a6a9	1618	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
mbed_official	85:e1a8e879a6a9	1619	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
mbed_official	85:e1a8e879a6a9	1620	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1621	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1622	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1623
mbed_official	85:e1a8e879a6a9	1624	/* Bit 2 : Pin 2. */
mbed_official	85:e1a8e879a6a9	1625	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
mbed_official	85:e1a8e879a6a9	1626	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
mbed_official	85:e1a8e879a6a9	1627	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1628	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1629	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1630
mbed_official	85:e1a8e879a6a9	1631	/* Bit 1 : Pin 1. */
mbed_official	85:e1a8e879a6a9	1632	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
mbed_official	85:e1a8e879a6a9	1633	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
mbed_official	85:e1a8e879a6a9	1634	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1635	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1636	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1637
mbed_official	85:e1a8e879a6a9	1638	/* Bit 0 : Pin 0. */
mbed_official	85:e1a8e879a6a9	1639	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
mbed_official	85:e1a8e879a6a9	1640	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
mbed_official	85:e1a8e879a6a9	1641	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1642	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1643	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
mbed_official	85:e1a8e879a6a9	1644
mbed_official	85:e1a8e879a6a9	1645	/* Register: GPIO_OUTCLR */
mbed_official	85:e1a8e879a6a9	1646	/* Description: Clear individual bits in GPIO port. */
mbed_official	85:e1a8e879a6a9	1647
mbed_official	85:e1a8e879a6a9	1648	/* Bit 31 : Pin 31. */
mbed_official	85:e1a8e879a6a9	1649	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
mbed_official	85:e1a8e879a6a9	1650	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
mbed_official	85:e1a8e879a6a9	1651	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1652	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1653	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1654
mbed_official	85:e1a8e879a6a9	1655	/* Bit 30 : Pin 30. */
mbed_official	85:e1a8e879a6a9	1656	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
mbed_official	85:e1a8e879a6a9	1657	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
mbed_official	85:e1a8e879a6a9	1658	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1659	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1660	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1661
mbed_official	85:e1a8e879a6a9	1662	/* Bit 29 : Pin 29. */
mbed_official	85:e1a8e879a6a9	1663	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
mbed_official	85:e1a8e879a6a9	1664	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
mbed_official	85:e1a8e879a6a9	1665	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1666	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1667	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1668
mbed_official	85:e1a8e879a6a9	1669	/* Bit 28 : Pin 28. */
mbed_official	85:e1a8e879a6a9	1670	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
mbed_official	85:e1a8e879a6a9	1671	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
mbed_official	85:e1a8e879a6a9	1672	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1673	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1674	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1675
mbed_official	85:e1a8e879a6a9	1676	/* Bit 27 : Pin 27. */
mbed_official	85:e1a8e879a6a9	1677	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
mbed_official	85:e1a8e879a6a9	1678	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
mbed_official	85:e1a8e879a6a9	1679	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1680	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1681	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1682
mbed_official	85:e1a8e879a6a9	1683	/* Bit 26 : Pin 26. */
mbed_official	85:e1a8e879a6a9	1684	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
mbed_official	85:e1a8e879a6a9	1685	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
mbed_official	85:e1a8e879a6a9	1686	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1687	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1688	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1689
mbed_official	85:e1a8e879a6a9	1690	/* Bit 25 : Pin 25. */
mbed_official	85:e1a8e879a6a9	1691	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
mbed_official	85:e1a8e879a6a9	1692	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
mbed_official	85:e1a8e879a6a9	1693	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1694	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1695	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1696
mbed_official	85:e1a8e879a6a9	1697	/* Bit 24 : Pin 24. */
mbed_official	85:e1a8e879a6a9	1698	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
mbed_official	85:e1a8e879a6a9	1699	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
mbed_official	85:e1a8e879a6a9	1700	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1701	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1702	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1703
mbed_official	85:e1a8e879a6a9	1704	/* Bit 23 : Pin 23. */
mbed_official	85:e1a8e879a6a9	1705	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
mbed_official	85:e1a8e879a6a9	1706	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
mbed_official	85:e1a8e879a6a9	1707	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1708	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1709	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1710
mbed_official	85:e1a8e879a6a9	1711	/* Bit 22 : Pin 22. */
mbed_official	85:e1a8e879a6a9	1712	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
mbed_official	85:e1a8e879a6a9	1713	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
mbed_official	85:e1a8e879a6a9	1714	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1715	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1716	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1717
mbed_official	85:e1a8e879a6a9	1718	/* Bit 21 : Pin 21. */
mbed_official	85:e1a8e879a6a9	1719	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
mbed_official	85:e1a8e879a6a9	1720	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
mbed_official	85:e1a8e879a6a9	1721	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1722	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1723	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1724
mbed_official	85:e1a8e879a6a9	1725	/* Bit 20 : Pin 20. */
mbed_official	85:e1a8e879a6a9	1726	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
mbed_official	85:e1a8e879a6a9	1727	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
mbed_official	85:e1a8e879a6a9	1728	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1729	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1730	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1731
mbed_official	85:e1a8e879a6a9	1732	/* Bit 19 : Pin 19. */
mbed_official	85:e1a8e879a6a9	1733	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
mbed_official	85:e1a8e879a6a9	1734	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
mbed_official	85:e1a8e879a6a9	1735	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1736	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1737	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1738
mbed_official	85:e1a8e879a6a9	1739	/* Bit 18 : Pin 18. */
mbed_official	85:e1a8e879a6a9	1740	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
mbed_official	85:e1a8e879a6a9	1741	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
mbed_official	85:e1a8e879a6a9	1742	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1743	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1744	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1745
mbed_official	85:e1a8e879a6a9	1746	/* Bit 17 : Pin 17. */
mbed_official	85:e1a8e879a6a9	1747	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
mbed_official	85:e1a8e879a6a9	1748	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
mbed_official	85:e1a8e879a6a9	1749	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1750	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1751	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1752
mbed_official	85:e1a8e879a6a9	1753	/* Bit 16 : Pin 16. */
mbed_official	85:e1a8e879a6a9	1754	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
mbed_official	85:e1a8e879a6a9	1755	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
mbed_official	85:e1a8e879a6a9	1756	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1757	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1758	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1759
mbed_official	85:e1a8e879a6a9	1760	/* Bit 15 : Pin 15. */
mbed_official	85:e1a8e879a6a9	1761	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
mbed_official	85:e1a8e879a6a9	1762	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
mbed_official	85:e1a8e879a6a9	1763	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1764	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1765	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1766
mbed_official	85:e1a8e879a6a9	1767	/* Bit 14 : Pin 14. */
mbed_official	85:e1a8e879a6a9	1768	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
mbed_official	85:e1a8e879a6a9	1769	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
mbed_official	85:e1a8e879a6a9	1770	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1771	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1772	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1773
mbed_official	85:e1a8e879a6a9	1774	/* Bit 13 : Pin 13. */
mbed_official	85:e1a8e879a6a9	1775	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
mbed_official	85:e1a8e879a6a9	1776	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
mbed_official	85:e1a8e879a6a9	1777	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1778	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1779	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1780
mbed_official	85:e1a8e879a6a9	1781	/* Bit 12 : Pin 12. */
mbed_official	85:e1a8e879a6a9	1782	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
mbed_official	85:e1a8e879a6a9	1783	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
mbed_official	85:e1a8e879a6a9	1784	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1785	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1786	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1787
mbed_official	85:e1a8e879a6a9	1788	/* Bit 11 : Pin 11. */
mbed_official	85:e1a8e879a6a9	1789	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
mbed_official	85:e1a8e879a6a9	1790	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
mbed_official	85:e1a8e879a6a9	1791	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1792	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1793	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1794
mbed_official	85:e1a8e879a6a9	1795	/* Bit 10 : Pin 10. */
mbed_official	85:e1a8e879a6a9	1796	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
mbed_official	85:e1a8e879a6a9	1797	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
mbed_official	85:e1a8e879a6a9	1798	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1799	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1800	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1801
mbed_official	85:e1a8e879a6a9	1802	/* Bit 9 : Pin 9. */
mbed_official	85:e1a8e879a6a9	1803	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
mbed_official	85:e1a8e879a6a9	1804	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
mbed_official	85:e1a8e879a6a9	1805	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1806	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1807	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1808
mbed_official	85:e1a8e879a6a9	1809	/* Bit 8 : Pin 8. */
mbed_official	85:e1a8e879a6a9	1810	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
mbed_official	85:e1a8e879a6a9	1811	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
mbed_official	85:e1a8e879a6a9	1812	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1813	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1814	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1815
mbed_official	85:e1a8e879a6a9	1816	/* Bit 7 : Pin 7. */
mbed_official	85:e1a8e879a6a9	1817	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
mbed_official	85:e1a8e879a6a9	1818	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
mbed_official	85:e1a8e879a6a9	1819	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1820	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1821	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1822
mbed_official	85:e1a8e879a6a9	1823	/* Bit 6 : Pin 6. */
mbed_official	85:e1a8e879a6a9	1824	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
mbed_official	85:e1a8e879a6a9	1825	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
mbed_official	85:e1a8e879a6a9	1826	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1827	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1828	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1829
mbed_official	85:e1a8e879a6a9	1830	/* Bit 5 : Pin 5. */
mbed_official	85:e1a8e879a6a9	1831	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
mbed_official	85:e1a8e879a6a9	1832	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
mbed_official	85:e1a8e879a6a9	1833	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1834	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1835	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1836
mbed_official	85:e1a8e879a6a9	1837	/* Bit 4 : Pin 4. */
mbed_official	85:e1a8e879a6a9	1838	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
mbed_official	85:e1a8e879a6a9	1839	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
mbed_official	85:e1a8e879a6a9	1840	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1841	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1842	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1843
mbed_official	85:e1a8e879a6a9	1844	/* Bit 3 : Pin 3. */
mbed_official	85:e1a8e879a6a9	1845	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
mbed_official	85:e1a8e879a6a9	1846	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
mbed_official	85:e1a8e879a6a9	1847	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1848	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1849	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1850
mbed_official	85:e1a8e879a6a9	1851	/* Bit 2 : Pin 2. */
mbed_official	85:e1a8e879a6a9	1852	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
mbed_official	85:e1a8e879a6a9	1853	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
mbed_official	85:e1a8e879a6a9	1854	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1855	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1856	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1857
mbed_official	85:e1a8e879a6a9	1858	/* Bit 1 : Pin 1. */
mbed_official	85:e1a8e879a6a9	1859	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
mbed_official	85:e1a8e879a6a9	1860	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
mbed_official	85:e1a8e879a6a9	1861	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1862	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1863	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1864
mbed_official	85:e1a8e879a6a9	1865	/* Bit 0 : Pin 0. */
mbed_official	85:e1a8e879a6a9	1866	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
mbed_official	85:e1a8e879a6a9	1867	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
mbed_official	85:e1a8e879a6a9	1868	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
mbed_official	85:e1a8e879a6a9	1869	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
mbed_official	85:e1a8e879a6a9	1870	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
mbed_official	85:e1a8e879a6a9	1871
mbed_official	85:e1a8e879a6a9	1872	/* Register: GPIO_IN */
mbed_official	85:e1a8e879a6a9	1873	/* Description: Read GPIO port. */
mbed_official	85:e1a8e879a6a9	1874
mbed_official	85:e1a8e879a6a9	1875	/* Bit 31 : Pin 31. */
mbed_official	85:e1a8e879a6a9	1876	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
mbed_official	85:e1a8e879a6a9	1877	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
mbed_official	85:e1a8e879a6a9	1878	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1879	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1880
mbed_official	85:e1a8e879a6a9	1881	/* Bit 30 : Pin 30. */
mbed_official	85:e1a8e879a6a9	1882	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
mbed_official	85:e1a8e879a6a9	1883	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
mbed_official	85:e1a8e879a6a9	1884	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1885	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1886
mbed_official	85:e1a8e879a6a9	1887	/* Bit 29 : Pin 29. */
mbed_official	85:e1a8e879a6a9	1888	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
mbed_official	85:e1a8e879a6a9	1889	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
mbed_official	85:e1a8e879a6a9	1890	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1891	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1892
mbed_official	85:e1a8e879a6a9	1893	/* Bit 28 : Pin 28. */
mbed_official	85:e1a8e879a6a9	1894	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
mbed_official	85:e1a8e879a6a9	1895	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
mbed_official	85:e1a8e879a6a9	1896	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1897	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1898
mbed_official	85:e1a8e879a6a9	1899	/* Bit 27 : Pin 27. */
mbed_official	85:e1a8e879a6a9	1900	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
mbed_official	85:e1a8e879a6a9	1901	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
mbed_official	85:e1a8e879a6a9	1902	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1903	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1904
mbed_official	85:e1a8e879a6a9	1905	/* Bit 26 : Pin 26. */
mbed_official	85:e1a8e879a6a9	1906	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
mbed_official	85:e1a8e879a6a9	1907	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
mbed_official	85:e1a8e879a6a9	1908	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1909	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1910
mbed_official	85:e1a8e879a6a9	1911	/* Bit 25 : Pin 25. */
mbed_official	85:e1a8e879a6a9	1912	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
mbed_official	85:e1a8e879a6a9	1913	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
mbed_official	85:e1a8e879a6a9	1914	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1915	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1916
mbed_official	85:e1a8e879a6a9	1917	/* Bit 24 : Pin 24. */
mbed_official	85:e1a8e879a6a9	1918	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
mbed_official	85:e1a8e879a6a9	1919	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
mbed_official	85:e1a8e879a6a9	1920	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1921	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1922
mbed_official	85:e1a8e879a6a9	1923	/* Bit 23 : Pin 23. */
mbed_official	85:e1a8e879a6a9	1924	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
mbed_official	85:e1a8e879a6a9	1925	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
mbed_official	85:e1a8e879a6a9	1926	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1927	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1928
mbed_official	85:e1a8e879a6a9	1929	/* Bit 22 : Pin 22. */
mbed_official	85:e1a8e879a6a9	1930	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
mbed_official	85:e1a8e879a6a9	1931	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
mbed_official	85:e1a8e879a6a9	1932	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1933	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1934
mbed_official	85:e1a8e879a6a9	1935	/* Bit 21 : Pin 21. */
mbed_official	85:e1a8e879a6a9	1936	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
mbed_official	85:e1a8e879a6a9	1937	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
mbed_official	85:e1a8e879a6a9	1938	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1939	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1940
mbed_official	85:e1a8e879a6a9	1941	/* Bit 20 : Pin 20. */
mbed_official	85:e1a8e879a6a9	1942	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
mbed_official	85:e1a8e879a6a9	1943	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
mbed_official	85:e1a8e879a6a9	1944	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1945	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1946
mbed_official	85:e1a8e879a6a9	1947	/* Bit 19 : Pin 19. */
mbed_official	85:e1a8e879a6a9	1948	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
mbed_official	85:e1a8e879a6a9	1949	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
mbed_official	85:e1a8e879a6a9	1950	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1951	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1952
mbed_official	85:e1a8e879a6a9	1953	/* Bit 18 : Pin 18. */
mbed_official	85:e1a8e879a6a9	1954	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
mbed_official	85:e1a8e879a6a9	1955	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
mbed_official	85:e1a8e879a6a9	1956	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1957	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1958
mbed_official	85:e1a8e879a6a9	1959	/* Bit 17 : Pin 17. */
mbed_official	85:e1a8e879a6a9	1960	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
mbed_official	85:e1a8e879a6a9	1961	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
mbed_official	85:e1a8e879a6a9	1962	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1963	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1964
mbed_official	85:e1a8e879a6a9	1965	/* Bit 16 : Pin 16. */
mbed_official	85:e1a8e879a6a9	1966	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
mbed_official	85:e1a8e879a6a9	1967	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
mbed_official	85:e1a8e879a6a9	1968	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1969	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1970
mbed_official	85:e1a8e879a6a9	1971	/* Bit 15 : Pin 15. */
mbed_official	85:e1a8e879a6a9	1972	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
mbed_official	85:e1a8e879a6a9	1973	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
mbed_official	85:e1a8e879a6a9	1974	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1975	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1976
mbed_official	85:e1a8e879a6a9	1977	/* Bit 14 : Pin 14. */
mbed_official	85:e1a8e879a6a9	1978	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
mbed_official	85:e1a8e879a6a9	1979	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
mbed_official	85:e1a8e879a6a9	1980	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1981	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1982
mbed_official	85:e1a8e879a6a9	1983	/* Bit 13 : Pin 13. */
mbed_official	85:e1a8e879a6a9	1984	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
mbed_official	85:e1a8e879a6a9	1985	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
mbed_official	85:e1a8e879a6a9	1986	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1987	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1988
mbed_official	85:e1a8e879a6a9	1989	/* Bit 12 : Pin 12. */
mbed_official	85:e1a8e879a6a9	1990	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
mbed_official	85:e1a8e879a6a9	1991	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
mbed_official	85:e1a8e879a6a9	1992	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1993	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	1994
mbed_official	85:e1a8e879a6a9	1995	/* Bit 11 : Pin 11. */
mbed_official	85:e1a8e879a6a9	1996	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
mbed_official	85:e1a8e879a6a9	1997	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
mbed_official	85:e1a8e879a6a9	1998	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	1999	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	2000
mbed_official	85:e1a8e879a6a9	2001	/* Bit 10 : Pin 10. */
mbed_official	85:e1a8e879a6a9	2002	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
mbed_official	85:e1a8e879a6a9	2003	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
mbed_official	85:e1a8e879a6a9	2004	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	2005	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	2006
mbed_official	85:e1a8e879a6a9	2007	/* Bit 9 : Pin 9. */
mbed_official	85:e1a8e879a6a9	2008	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
mbed_official	85:e1a8e879a6a9	2009	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
mbed_official	85:e1a8e879a6a9	2010	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	2011	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	2012
mbed_official	85:e1a8e879a6a9	2013	/* Bit 8 : Pin 8. */
mbed_official	85:e1a8e879a6a9	2014	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
mbed_official	85:e1a8e879a6a9	2015	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
mbed_official	85:e1a8e879a6a9	2016	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	2017	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	2018
mbed_official	85:e1a8e879a6a9	2019	/* Bit 7 : Pin 7. */
mbed_official	85:e1a8e879a6a9	2020	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
mbed_official	85:e1a8e879a6a9	2021	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
mbed_official	85:e1a8e879a6a9	2022	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	2023	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	2024
mbed_official	85:e1a8e879a6a9	2025	/* Bit 6 : Pin 6. */
mbed_official	85:e1a8e879a6a9	2026	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
mbed_official	85:e1a8e879a6a9	2027	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
mbed_official	85:e1a8e879a6a9	2028	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	2029	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	2030
mbed_official	85:e1a8e879a6a9	2031	/* Bit 5 : Pin 5. */
mbed_official	85:e1a8e879a6a9	2032	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
mbed_official	85:e1a8e879a6a9	2033	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
mbed_official	85:e1a8e879a6a9	2034	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	2035	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	2036
mbed_official	85:e1a8e879a6a9	2037	/* Bit 4 : Pin 4. */
mbed_official	85:e1a8e879a6a9	2038	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
mbed_official	85:e1a8e879a6a9	2039	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
mbed_official	85:e1a8e879a6a9	2040	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	2041	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	2042
mbed_official	85:e1a8e879a6a9	2043	/* Bit 3 : Pin 3. */
mbed_official	85:e1a8e879a6a9	2044	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
mbed_official	85:e1a8e879a6a9	2045	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
mbed_official	85:e1a8e879a6a9	2046	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	2047	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	2048
mbed_official	85:e1a8e879a6a9	2049	/* Bit 2 : Pin 2. */
mbed_official	85:e1a8e879a6a9	2050	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
mbed_official	85:e1a8e879a6a9	2051	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
mbed_official	85:e1a8e879a6a9	2052	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	2053	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	2054
mbed_official	85:e1a8e879a6a9	2055	/* Bit 1 : Pin 1. */
mbed_official	85:e1a8e879a6a9	2056	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
mbed_official	85:e1a8e879a6a9	2057	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
mbed_official	85:e1a8e879a6a9	2058	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	2059	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	2060
mbed_official	85:e1a8e879a6a9	2061	/* Bit 0 : Pin 0. */
mbed_official	85:e1a8e879a6a9	2062	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
mbed_official	85:e1a8e879a6a9	2063	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
mbed_official	85:e1a8e879a6a9	2064	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
mbed_official	85:e1a8e879a6a9	2065	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
mbed_official	85:e1a8e879a6a9	2066
mbed_official	85:e1a8e879a6a9	2067	/* Register: GPIO_DIR */
mbed_official	85:e1a8e879a6a9	2068	/* Description: Direction of GPIO pins. */
mbed_official	85:e1a8e879a6a9	2069
mbed_official	85:e1a8e879a6a9	2070	/* Bit 31 : Pin 31. */
mbed_official	85:e1a8e879a6a9	2071	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
mbed_official	85:e1a8e879a6a9	2072	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
mbed_official	85:e1a8e879a6a9	2073	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2074	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2075
mbed_official	85:e1a8e879a6a9	2076	/* Bit 30 : Pin 30. */
mbed_official	85:e1a8e879a6a9	2077	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
mbed_official	85:e1a8e879a6a9	2078	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
mbed_official	85:e1a8e879a6a9	2079	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2080	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2081
mbed_official	85:e1a8e879a6a9	2082	/* Bit 29 : Pin 29. */
mbed_official	85:e1a8e879a6a9	2083	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
mbed_official	85:e1a8e879a6a9	2084	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
mbed_official	85:e1a8e879a6a9	2085	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2086	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2087
mbed_official	85:e1a8e879a6a9	2088	/* Bit 28 : Pin 28. */
mbed_official	85:e1a8e879a6a9	2089	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
mbed_official	85:e1a8e879a6a9	2090	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
mbed_official	85:e1a8e879a6a9	2091	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2092	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2093
mbed_official	85:e1a8e879a6a9	2094	/* Bit 27 : Pin 27. */
mbed_official	85:e1a8e879a6a9	2095	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
mbed_official	85:e1a8e879a6a9	2096	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
mbed_official	85:e1a8e879a6a9	2097	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2098	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2099
mbed_official	85:e1a8e879a6a9	2100	/* Bit 26 : Pin 26. */
mbed_official	85:e1a8e879a6a9	2101	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
mbed_official	85:e1a8e879a6a9	2102	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
mbed_official	85:e1a8e879a6a9	2103	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2104	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2105
mbed_official	85:e1a8e879a6a9	2106	/* Bit 25 : Pin 25. */
mbed_official	85:e1a8e879a6a9	2107	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
mbed_official	85:e1a8e879a6a9	2108	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
mbed_official	85:e1a8e879a6a9	2109	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2110	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2111
mbed_official	85:e1a8e879a6a9	2112	/* Bit 24 : Pin 24. */
mbed_official	85:e1a8e879a6a9	2113	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
mbed_official	85:e1a8e879a6a9	2114	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
mbed_official	85:e1a8e879a6a9	2115	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2116	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2117
mbed_official	85:e1a8e879a6a9	2118	/* Bit 23 : Pin 23. */
mbed_official	85:e1a8e879a6a9	2119	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
mbed_official	85:e1a8e879a6a9	2120	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
mbed_official	85:e1a8e879a6a9	2121	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2122	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2123
mbed_official	85:e1a8e879a6a9	2124	/* Bit 22 : Pin 22. */
mbed_official	85:e1a8e879a6a9	2125	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
mbed_official	85:e1a8e879a6a9	2126	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
mbed_official	85:e1a8e879a6a9	2127	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2128	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2129
mbed_official	85:e1a8e879a6a9	2130	/* Bit 21 : Pin 21. */
mbed_official	85:e1a8e879a6a9	2131	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
mbed_official	85:e1a8e879a6a9	2132	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
mbed_official	85:e1a8e879a6a9	2133	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2134	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2135
mbed_official	85:e1a8e879a6a9	2136	/* Bit 20 : Pin 20. */
mbed_official	85:e1a8e879a6a9	2137	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
mbed_official	85:e1a8e879a6a9	2138	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
mbed_official	85:e1a8e879a6a9	2139	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2140	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2141
mbed_official	85:e1a8e879a6a9	2142	/* Bit 19 : Pin 19. */
mbed_official	85:e1a8e879a6a9	2143	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
mbed_official	85:e1a8e879a6a9	2144	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
mbed_official	85:e1a8e879a6a9	2145	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2146	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2147
mbed_official	85:e1a8e879a6a9	2148	/* Bit 18 : Pin 18. */
mbed_official	85:e1a8e879a6a9	2149	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
mbed_official	85:e1a8e879a6a9	2150	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
mbed_official	85:e1a8e879a6a9	2151	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2152	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2153
mbed_official	85:e1a8e879a6a9	2154	/* Bit 17 : Pin 17. */
mbed_official	85:e1a8e879a6a9	2155	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
mbed_official	85:e1a8e879a6a9	2156	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
mbed_official	85:e1a8e879a6a9	2157	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2158	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2159
mbed_official	85:e1a8e879a6a9	2160	/* Bit 16 : Pin 16. */
mbed_official	85:e1a8e879a6a9	2161	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
mbed_official	85:e1a8e879a6a9	2162	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
mbed_official	85:e1a8e879a6a9	2163	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2164	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2165
mbed_official	85:e1a8e879a6a9	2166	/* Bit 15 : Pin 15. */
mbed_official	85:e1a8e879a6a9	2167	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
mbed_official	85:e1a8e879a6a9	2168	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
mbed_official	85:e1a8e879a6a9	2169	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2170	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2171
mbed_official	85:e1a8e879a6a9	2172	/* Bit 14 : Pin 14. */
mbed_official	85:e1a8e879a6a9	2173	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
mbed_official	85:e1a8e879a6a9	2174	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
mbed_official	85:e1a8e879a6a9	2175	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2176	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2177
mbed_official	85:e1a8e879a6a9	2178	/* Bit 13 : Pin 13. */
mbed_official	85:e1a8e879a6a9	2179	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
mbed_official	85:e1a8e879a6a9	2180	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
mbed_official	85:e1a8e879a6a9	2181	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2182	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2183
mbed_official	85:e1a8e879a6a9	2184	/* Bit 12 : Pin 12. */
mbed_official	85:e1a8e879a6a9	2185	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
mbed_official	85:e1a8e879a6a9	2186	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
mbed_official	85:e1a8e879a6a9	2187	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2188	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2189
mbed_official	85:e1a8e879a6a9	2190	/* Bit 11 : Pin 11. */
mbed_official	85:e1a8e879a6a9	2191	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
mbed_official	85:e1a8e879a6a9	2192	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
mbed_official	85:e1a8e879a6a9	2193	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2194	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2195
mbed_official	85:e1a8e879a6a9	2196	/* Bit 10 : Pin 10. */
mbed_official	85:e1a8e879a6a9	2197	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
mbed_official	85:e1a8e879a6a9	2198	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
mbed_official	85:e1a8e879a6a9	2199	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2200	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2201
mbed_official	85:e1a8e879a6a9	2202	/* Bit 9 : Pin 9. */
mbed_official	85:e1a8e879a6a9	2203	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
mbed_official	85:e1a8e879a6a9	2204	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
mbed_official	85:e1a8e879a6a9	2205	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2206	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2207
mbed_official	85:e1a8e879a6a9	2208	/* Bit 8 : Pin 8. */
mbed_official	85:e1a8e879a6a9	2209	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
mbed_official	85:e1a8e879a6a9	2210	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
mbed_official	85:e1a8e879a6a9	2211	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2212	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2213
mbed_official	85:e1a8e879a6a9	2214	/* Bit 7 : Pin 7. */
mbed_official	85:e1a8e879a6a9	2215	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
mbed_official	85:e1a8e879a6a9	2216	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
mbed_official	85:e1a8e879a6a9	2217	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2218	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2219
mbed_official	85:e1a8e879a6a9	2220	/* Bit 6 : Pin 6. */
mbed_official	85:e1a8e879a6a9	2221	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
mbed_official	85:e1a8e879a6a9	2222	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
mbed_official	85:e1a8e879a6a9	2223	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2224	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2225
mbed_official	85:e1a8e879a6a9	2226	/* Bit 5 : Pin 5. */
mbed_official	85:e1a8e879a6a9	2227	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
mbed_official	85:e1a8e879a6a9	2228	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
mbed_official	85:e1a8e879a6a9	2229	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2230	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2231
mbed_official	85:e1a8e879a6a9	2232	/* Bit 4 : Pin 4. */
mbed_official	85:e1a8e879a6a9	2233	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
mbed_official	85:e1a8e879a6a9	2234	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
mbed_official	85:e1a8e879a6a9	2235	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2236	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2237
mbed_official	85:e1a8e879a6a9	2238	/* Bit 3 : Pin 3. */
mbed_official	85:e1a8e879a6a9	2239	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
mbed_official	85:e1a8e879a6a9	2240	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
mbed_official	85:e1a8e879a6a9	2241	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2242	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2243
mbed_official	85:e1a8e879a6a9	2244	/* Bit 2 : Pin 2. */
mbed_official	85:e1a8e879a6a9	2245	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
mbed_official	85:e1a8e879a6a9	2246	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
mbed_official	85:e1a8e879a6a9	2247	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2248	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2249
mbed_official	85:e1a8e879a6a9	2250	/* Bit 1 : Pin 1. */
mbed_official	85:e1a8e879a6a9	2251	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
mbed_official	85:e1a8e879a6a9	2252	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
mbed_official	85:e1a8e879a6a9	2253	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2254	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2255
mbed_official	85:e1a8e879a6a9	2256	/* Bit 0 : Pin 0. */
mbed_official	85:e1a8e879a6a9	2257	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
mbed_official	85:e1a8e879a6a9	2258	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
mbed_official	85:e1a8e879a6a9	2259	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2260	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2261
mbed_official	85:e1a8e879a6a9	2262	/* Register: GPIO_DIRSET */
mbed_official	85:e1a8e879a6a9	2263	/* Description: DIR set register. */
mbed_official	85:e1a8e879a6a9	2264
mbed_official	85:e1a8e879a6a9	2265	/* Bit 31 : Set as output pin 31. */
mbed_official	85:e1a8e879a6a9	2266	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
mbed_official	85:e1a8e879a6a9	2267	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
mbed_official	85:e1a8e879a6a9	2268	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2269	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2270	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2271
mbed_official	85:e1a8e879a6a9	2272	/* Bit 30 : Set as output pin 30. */
mbed_official	85:e1a8e879a6a9	2273	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
mbed_official	85:e1a8e879a6a9	2274	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
mbed_official	85:e1a8e879a6a9	2275	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2276	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2277	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2278
mbed_official	85:e1a8e879a6a9	2279	/* Bit 29 : Set as output pin 29. */
mbed_official	85:e1a8e879a6a9	2280	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
mbed_official	85:e1a8e879a6a9	2281	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
mbed_official	85:e1a8e879a6a9	2282	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2283	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2284	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2285
mbed_official	85:e1a8e879a6a9	2286	/* Bit 28 : Set as output pin 28. */
mbed_official	85:e1a8e879a6a9	2287	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
mbed_official	85:e1a8e879a6a9	2288	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
mbed_official	85:e1a8e879a6a9	2289	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2290	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2291	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2292
mbed_official	85:e1a8e879a6a9	2293	/* Bit 27 : Set as output pin 27. */
mbed_official	85:e1a8e879a6a9	2294	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
mbed_official	85:e1a8e879a6a9	2295	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
mbed_official	85:e1a8e879a6a9	2296	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2297	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2298	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2299
mbed_official	85:e1a8e879a6a9	2300	/* Bit 26 : Set as output pin 26. */
mbed_official	85:e1a8e879a6a9	2301	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
mbed_official	85:e1a8e879a6a9	2302	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
mbed_official	85:e1a8e879a6a9	2303	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2304	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2305	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2306
mbed_official	85:e1a8e879a6a9	2307	/* Bit 25 : Set as output pin 25. */
mbed_official	85:e1a8e879a6a9	2308	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
mbed_official	85:e1a8e879a6a9	2309	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
mbed_official	85:e1a8e879a6a9	2310	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2311	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2312	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2313
mbed_official	85:e1a8e879a6a9	2314	/* Bit 24 : Set as output pin 24. */
mbed_official	85:e1a8e879a6a9	2315	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
mbed_official	85:e1a8e879a6a9	2316	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
mbed_official	85:e1a8e879a6a9	2317	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2318	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2319	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2320
mbed_official	85:e1a8e879a6a9	2321	/* Bit 23 : Set as output pin 23. */
mbed_official	85:e1a8e879a6a9	2322	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
mbed_official	85:e1a8e879a6a9	2323	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
mbed_official	85:e1a8e879a6a9	2324	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2325	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2326	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2327
mbed_official	85:e1a8e879a6a9	2328	/* Bit 22 : Set as output pin 22. */
mbed_official	85:e1a8e879a6a9	2329	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
mbed_official	85:e1a8e879a6a9	2330	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
mbed_official	85:e1a8e879a6a9	2331	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2332	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2333	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2334
mbed_official	85:e1a8e879a6a9	2335	/* Bit 21 : Set as output pin 21. */
mbed_official	85:e1a8e879a6a9	2336	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
mbed_official	85:e1a8e879a6a9	2337	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
mbed_official	85:e1a8e879a6a9	2338	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2339	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2340	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2341
mbed_official	85:e1a8e879a6a9	2342	/* Bit 20 : Set as output pin 20. */
mbed_official	85:e1a8e879a6a9	2343	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
mbed_official	85:e1a8e879a6a9	2344	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
mbed_official	85:e1a8e879a6a9	2345	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2346	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2347	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2348
mbed_official	85:e1a8e879a6a9	2349	/* Bit 19 : Set as output pin 19. */
mbed_official	85:e1a8e879a6a9	2350	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
mbed_official	85:e1a8e879a6a9	2351	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
mbed_official	85:e1a8e879a6a9	2352	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2353	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2354	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2355
mbed_official	85:e1a8e879a6a9	2356	/* Bit 18 : Set as output pin 18. */
mbed_official	85:e1a8e879a6a9	2357	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
mbed_official	85:e1a8e879a6a9	2358	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
mbed_official	85:e1a8e879a6a9	2359	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2360	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2361	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2362
mbed_official	85:e1a8e879a6a9	2363	/* Bit 17 : Set as output pin 17. */
mbed_official	85:e1a8e879a6a9	2364	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
mbed_official	85:e1a8e879a6a9	2365	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
mbed_official	85:e1a8e879a6a9	2366	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2367	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2368	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2369
mbed_official	85:e1a8e879a6a9	2370	/* Bit 16 : Set as output pin 16. */
mbed_official	85:e1a8e879a6a9	2371	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
mbed_official	85:e1a8e879a6a9	2372	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
mbed_official	85:e1a8e879a6a9	2373	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2374	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2375	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2376
mbed_official	85:e1a8e879a6a9	2377	/* Bit 15 : Set as output pin 15. */
mbed_official	85:e1a8e879a6a9	2378	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
mbed_official	85:e1a8e879a6a9	2379	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
mbed_official	85:e1a8e879a6a9	2380	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2381	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2382	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2383
mbed_official	85:e1a8e879a6a9	2384	/* Bit 14 : Set as output pin 14. */
mbed_official	85:e1a8e879a6a9	2385	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
mbed_official	85:e1a8e879a6a9	2386	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
mbed_official	85:e1a8e879a6a9	2387	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2388	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2389	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2390
mbed_official	85:e1a8e879a6a9	2391	/* Bit 13 : Set as output pin 13. */
mbed_official	85:e1a8e879a6a9	2392	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
mbed_official	85:e1a8e879a6a9	2393	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
mbed_official	85:e1a8e879a6a9	2394	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2395	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2396	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2397
mbed_official	85:e1a8e879a6a9	2398	/* Bit 12 : Set as output pin 12. */
mbed_official	85:e1a8e879a6a9	2399	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
mbed_official	85:e1a8e879a6a9	2400	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
mbed_official	85:e1a8e879a6a9	2401	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2402	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2403	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2404
mbed_official	85:e1a8e879a6a9	2405	/* Bit 11 : Set as output pin 11. */
mbed_official	85:e1a8e879a6a9	2406	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
mbed_official	85:e1a8e879a6a9	2407	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
mbed_official	85:e1a8e879a6a9	2408	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2409	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2410	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2411
mbed_official	85:e1a8e879a6a9	2412	/* Bit 10 : Set as output pin 10. */
mbed_official	85:e1a8e879a6a9	2413	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
mbed_official	85:e1a8e879a6a9	2414	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
mbed_official	85:e1a8e879a6a9	2415	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2416	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2417	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2418
mbed_official	85:e1a8e879a6a9	2419	/* Bit 9 : Set as output pin 9. */
mbed_official	85:e1a8e879a6a9	2420	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
mbed_official	85:e1a8e879a6a9	2421	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
mbed_official	85:e1a8e879a6a9	2422	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2423	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2424	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2425
mbed_official	85:e1a8e879a6a9	2426	/* Bit 8 : Set as output pin 8. */
mbed_official	85:e1a8e879a6a9	2427	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
mbed_official	85:e1a8e879a6a9	2428	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
mbed_official	85:e1a8e879a6a9	2429	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2430	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2431	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2432
mbed_official	85:e1a8e879a6a9	2433	/* Bit 7 : Set as output pin 7. */
mbed_official	85:e1a8e879a6a9	2434	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
mbed_official	85:e1a8e879a6a9	2435	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
mbed_official	85:e1a8e879a6a9	2436	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2437	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2438	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2439
mbed_official	85:e1a8e879a6a9	2440	/* Bit 6 : Set as output pin 6. */
mbed_official	85:e1a8e879a6a9	2441	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
mbed_official	85:e1a8e879a6a9	2442	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
mbed_official	85:e1a8e879a6a9	2443	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2444	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2445	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2446
mbed_official	85:e1a8e879a6a9	2447	/* Bit 5 : Set as output pin 5. */
mbed_official	85:e1a8e879a6a9	2448	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
mbed_official	85:e1a8e879a6a9	2449	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
mbed_official	85:e1a8e879a6a9	2450	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2451	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2452	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2453
mbed_official	85:e1a8e879a6a9	2454	/* Bit 4 : Set as output pin 4. */
mbed_official	85:e1a8e879a6a9	2455	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
mbed_official	85:e1a8e879a6a9	2456	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
mbed_official	85:e1a8e879a6a9	2457	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2458	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2459	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2460
mbed_official	85:e1a8e879a6a9	2461	/* Bit 3 : Set as output pin 3. */
mbed_official	85:e1a8e879a6a9	2462	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
mbed_official	85:e1a8e879a6a9	2463	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
mbed_official	85:e1a8e879a6a9	2464	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2465	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2466	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2467
mbed_official	85:e1a8e879a6a9	2468	/* Bit 2 : Set as output pin 2. */
mbed_official	85:e1a8e879a6a9	2469	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
mbed_official	85:e1a8e879a6a9	2470	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
mbed_official	85:e1a8e879a6a9	2471	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2472	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2473	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2474
mbed_official	85:e1a8e879a6a9	2475	/* Bit 1 : Set as output pin 1. */
mbed_official	85:e1a8e879a6a9	2476	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
mbed_official	85:e1a8e879a6a9	2477	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
mbed_official	85:e1a8e879a6a9	2478	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2479	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2480	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2481
mbed_official	85:e1a8e879a6a9	2482	/* Bit 0 : Set as output pin 0. */
mbed_official	85:e1a8e879a6a9	2483	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
mbed_official	85:e1a8e879a6a9	2484	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
mbed_official	85:e1a8e879a6a9	2485	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2486	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2487	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
mbed_official	85:e1a8e879a6a9	2488
mbed_official	85:e1a8e879a6a9	2489	/* Register: GPIO_DIRCLR */
mbed_official	85:e1a8e879a6a9	2490	/* Description: DIR clear register. */
mbed_official	85:e1a8e879a6a9	2491
mbed_official	85:e1a8e879a6a9	2492	/* Bit 31 : Set as input pin 31. */
mbed_official	85:e1a8e879a6a9	2493	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
mbed_official	85:e1a8e879a6a9	2494	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
mbed_official	85:e1a8e879a6a9	2495	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2496	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2497	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2498
mbed_official	85:e1a8e879a6a9	2499	/* Bit 30 : Set as input pin 30. */
mbed_official	85:e1a8e879a6a9	2500	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
mbed_official	85:e1a8e879a6a9	2501	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
mbed_official	85:e1a8e879a6a9	2502	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2503	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2504	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2505
mbed_official	85:e1a8e879a6a9	2506	/* Bit 29 : Set as input pin 29. */
mbed_official	85:e1a8e879a6a9	2507	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
mbed_official	85:e1a8e879a6a9	2508	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
mbed_official	85:e1a8e879a6a9	2509	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2510	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2511	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2512
mbed_official	85:e1a8e879a6a9	2513	/* Bit 28 : Set as input pin 28. */
mbed_official	85:e1a8e879a6a9	2514	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
mbed_official	85:e1a8e879a6a9	2515	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
mbed_official	85:e1a8e879a6a9	2516	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2517	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2518	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2519
mbed_official	85:e1a8e879a6a9	2520	/* Bit 27 : Set as input pin 27. */
mbed_official	85:e1a8e879a6a9	2521	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
mbed_official	85:e1a8e879a6a9	2522	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
mbed_official	85:e1a8e879a6a9	2523	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2524	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2525	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2526
mbed_official	85:e1a8e879a6a9	2527	/* Bit 26 : Set as input pin 26. */
mbed_official	85:e1a8e879a6a9	2528	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
mbed_official	85:e1a8e879a6a9	2529	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
mbed_official	85:e1a8e879a6a9	2530	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2531	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2532	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2533
mbed_official	85:e1a8e879a6a9	2534	/* Bit 25 : Set as input pin 25. */
mbed_official	85:e1a8e879a6a9	2535	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
mbed_official	85:e1a8e879a6a9	2536	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
mbed_official	85:e1a8e879a6a9	2537	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2538	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2539	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2540
mbed_official	85:e1a8e879a6a9	2541	/* Bit 24 : Set as input pin 24. */
mbed_official	85:e1a8e879a6a9	2542	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
mbed_official	85:e1a8e879a6a9	2543	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
mbed_official	85:e1a8e879a6a9	2544	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2545	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2546	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2547
mbed_official	85:e1a8e879a6a9	2548	/* Bit 23 : Set as input pin 23. */
mbed_official	85:e1a8e879a6a9	2549	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
mbed_official	85:e1a8e879a6a9	2550	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
mbed_official	85:e1a8e879a6a9	2551	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2552	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2553	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2554
mbed_official	85:e1a8e879a6a9	2555	/* Bit 22 : Set as input pin 22. */
mbed_official	85:e1a8e879a6a9	2556	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
mbed_official	85:e1a8e879a6a9	2557	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
mbed_official	85:e1a8e879a6a9	2558	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2559	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2560	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2561
mbed_official	85:e1a8e879a6a9	2562	/* Bit 21 : Set as input pin 21. */
mbed_official	85:e1a8e879a6a9	2563	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
mbed_official	85:e1a8e879a6a9	2564	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
mbed_official	85:e1a8e879a6a9	2565	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2566	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2567	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2568
mbed_official	85:e1a8e879a6a9	2569	/* Bit 20 : Set as input pin 20. */
mbed_official	85:e1a8e879a6a9	2570	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
mbed_official	85:e1a8e879a6a9	2571	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
mbed_official	85:e1a8e879a6a9	2572	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2573	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2574	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2575
mbed_official	85:e1a8e879a6a9	2576	/* Bit 19 : Set as input pin 19. */
mbed_official	85:e1a8e879a6a9	2577	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
mbed_official	85:e1a8e879a6a9	2578	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
mbed_official	85:e1a8e879a6a9	2579	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2580	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2581	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2582
mbed_official	85:e1a8e879a6a9	2583	/* Bit 18 : Set as input pin 18. */
mbed_official	85:e1a8e879a6a9	2584	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
mbed_official	85:e1a8e879a6a9	2585	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
mbed_official	85:e1a8e879a6a9	2586	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2587	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2588	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2589
mbed_official	85:e1a8e879a6a9	2590	/* Bit 17 : Set as input pin 17. */
mbed_official	85:e1a8e879a6a9	2591	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
mbed_official	85:e1a8e879a6a9	2592	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
mbed_official	85:e1a8e879a6a9	2593	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2594	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2595	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2596
mbed_official	85:e1a8e879a6a9	2597	/* Bit 16 : Set as input pin 16. */
mbed_official	85:e1a8e879a6a9	2598	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
mbed_official	85:e1a8e879a6a9	2599	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
mbed_official	85:e1a8e879a6a9	2600	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2601	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2602	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2603
mbed_official	85:e1a8e879a6a9	2604	/* Bit 15 : Set as input pin 15. */
mbed_official	85:e1a8e879a6a9	2605	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
mbed_official	85:e1a8e879a6a9	2606	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
mbed_official	85:e1a8e879a6a9	2607	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2608	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2609	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2610
mbed_official	85:e1a8e879a6a9	2611	/* Bit 14 : Set as input pin 14. */
mbed_official	85:e1a8e879a6a9	2612	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
mbed_official	85:e1a8e879a6a9	2613	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
mbed_official	85:e1a8e879a6a9	2614	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2615	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2616	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2617
mbed_official	85:e1a8e879a6a9	2618	/* Bit 13 : Set as input pin 13. */
mbed_official	85:e1a8e879a6a9	2619	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
mbed_official	85:e1a8e879a6a9	2620	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
mbed_official	85:e1a8e879a6a9	2621	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2622	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2623	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2624
mbed_official	85:e1a8e879a6a9	2625	/* Bit 12 : Set as input pin 12. */
mbed_official	85:e1a8e879a6a9	2626	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
mbed_official	85:e1a8e879a6a9	2627	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
mbed_official	85:e1a8e879a6a9	2628	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2629	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2630	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2631
mbed_official	85:e1a8e879a6a9	2632	/* Bit 11 : Set as input pin 11. */
mbed_official	85:e1a8e879a6a9	2633	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
mbed_official	85:e1a8e879a6a9	2634	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
mbed_official	85:e1a8e879a6a9	2635	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2636	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2637	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2638
mbed_official	85:e1a8e879a6a9	2639	/* Bit 10 : Set as input pin 10. */
mbed_official	85:e1a8e879a6a9	2640	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
mbed_official	85:e1a8e879a6a9	2641	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
mbed_official	85:e1a8e879a6a9	2642	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2643	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2644	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2645
mbed_official	85:e1a8e879a6a9	2646	/* Bit 9 : Set as input pin 9. */
mbed_official	85:e1a8e879a6a9	2647	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
mbed_official	85:e1a8e879a6a9	2648	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
mbed_official	85:e1a8e879a6a9	2649	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2650	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2651	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2652
mbed_official	85:e1a8e879a6a9	2653	/* Bit 8 : Set as input pin 8. */
mbed_official	85:e1a8e879a6a9	2654	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
mbed_official	85:e1a8e879a6a9	2655	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
mbed_official	85:e1a8e879a6a9	2656	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2657	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2658	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2659
mbed_official	85:e1a8e879a6a9	2660	/* Bit 7 : Set as input pin 7. */
mbed_official	85:e1a8e879a6a9	2661	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
mbed_official	85:e1a8e879a6a9	2662	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
mbed_official	85:e1a8e879a6a9	2663	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2664	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2665	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2666
mbed_official	85:e1a8e879a6a9	2667	/* Bit 6 : Set as input pin 6. */
mbed_official	85:e1a8e879a6a9	2668	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
mbed_official	85:e1a8e879a6a9	2669	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
mbed_official	85:e1a8e879a6a9	2670	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2671	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2672	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2673
mbed_official	85:e1a8e879a6a9	2674	/* Bit 5 : Set as input pin 5. */
mbed_official	85:e1a8e879a6a9	2675	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
mbed_official	85:e1a8e879a6a9	2676	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
mbed_official	85:e1a8e879a6a9	2677	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2678	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2679	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2680
mbed_official	85:e1a8e879a6a9	2681	/* Bit 4 : Set as input pin 4. */
mbed_official	85:e1a8e879a6a9	2682	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
mbed_official	85:e1a8e879a6a9	2683	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
mbed_official	85:e1a8e879a6a9	2684	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2685	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2686	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2687
mbed_official	85:e1a8e879a6a9	2688	/* Bit 3 : Set as input pin 3. */
mbed_official	85:e1a8e879a6a9	2689	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
mbed_official	85:e1a8e879a6a9	2690	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
mbed_official	85:e1a8e879a6a9	2691	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2692	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2693	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2694
mbed_official	85:e1a8e879a6a9	2695	/* Bit 2 : Set as input pin 2. */
mbed_official	85:e1a8e879a6a9	2696	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
mbed_official	85:e1a8e879a6a9	2697	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
mbed_official	85:e1a8e879a6a9	2698	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2699	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2700	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2701
mbed_official	85:e1a8e879a6a9	2702	/* Bit 1 : Set as input pin 1. */
mbed_official	85:e1a8e879a6a9	2703	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
mbed_official	85:e1a8e879a6a9	2704	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
mbed_official	85:e1a8e879a6a9	2705	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2706	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2707	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2708
mbed_official	85:e1a8e879a6a9	2709	/* Bit 0 : Set as input pin 0. */
mbed_official	85:e1a8e879a6a9	2710	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
mbed_official	85:e1a8e879a6a9	2711	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
mbed_official	85:e1a8e879a6a9	2712	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
mbed_official	85:e1a8e879a6a9	2713	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
mbed_official	85:e1a8e879a6a9	2714	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
mbed_official	85:e1a8e879a6a9	2715
mbed_official	85:e1a8e879a6a9	2716	/* Register: GPIO_PIN_CNF */
mbed_official	85:e1a8e879a6a9	2717	/* Description: Configuration of GPIO pins. */
mbed_official	85:e1a8e879a6a9	2718
mbed_official	85:e1a8e879a6a9	2719	/* Bits 17..16 : Pin sensing mechanism. */
mbed_official	85:e1a8e879a6a9	2720	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
mbed_official	85:e1a8e879a6a9	2721	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
mbed_official	85:e1a8e879a6a9	2722	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	2723	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
mbed_official	85:e1a8e879a6a9	2724	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
mbed_official	85:e1a8e879a6a9	2725
mbed_official	85:e1a8e879a6a9	2726	/* Bits 10..8 : Drive configuration. */
mbed_official	85:e1a8e879a6a9	2727	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
mbed_official	85:e1a8e879a6a9	2728	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
mbed_official	85:e1a8e879a6a9	2729	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
mbed_official	85:e1a8e879a6a9	2730	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
mbed_official	85:e1a8e879a6a9	2731	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
mbed_official	85:e1a8e879a6a9	2732	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
mbed_official	85:e1a8e879a6a9	2733	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
mbed_official	85:e1a8e879a6a9	2734	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
mbed_official	85:e1a8e879a6a9	2735	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
mbed_official	85:e1a8e879a6a9	2736	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
mbed_official	85:e1a8e879a6a9	2737
mbed_official	85:e1a8e879a6a9	2738	/* Bits 3..2 : Pull-up or -down configuration. */
mbed_official	85:e1a8e879a6a9	2739	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
mbed_official	85:e1a8e879a6a9	2740	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
mbed_official	85:e1a8e879a6a9	2741	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
mbed_official	85:e1a8e879a6a9	2742	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
mbed_official	85:e1a8e879a6a9	2743	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
mbed_official	85:e1a8e879a6a9	2744
mbed_official	85:e1a8e879a6a9	2745	/* Bit 1 : Connect or disconnect input path. */
mbed_official	85:e1a8e879a6a9	2746	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
mbed_official	85:e1a8e879a6a9	2747	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
mbed_official	85:e1a8e879a6a9	2748	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
mbed_official	85:e1a8e879a6a9	2749	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
mbed_official	85:e1a8e879a6a9	2750
mbed_official	85:e1a8e879a6a9	2751	/* Bit 0 : Pin direction. */
mbed_official	85:e1a8e879a6a9	2752	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
mbed_official	85:e1a8e879a6a9	2753	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
mbed_official	85:e1a8e879a6a9	2754	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
mbed_official	85:e1a8e879a6a9	2755	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
mbed_official	85:e1a8e879a6a9	2756
mbed_official	85:e1a8e879a6a9	2757
mbed_official	85:e1a8e879a6a9	2758	/* Peripheral: GPIOTE */
mbed_official	85:e1a8e879a6a9	2759	/* Description: GPIO tasks and events. */
mbed_official	85:e1a8e879a6a9	2760
mbed_official	85:e1a8e879a6a9	2761	/* Register: GPIOTE_INTENSET */
mbed_official	85:e1a8e879a6a9	2762	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	2763
mbed_official	85:e1a8e879a6a9	2764	/* Bit 31 : Enable interrupt on PORT event. */
mbed_official	85:e1a8e879a6a9	2765	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
mbed_official	85:e1a8e879a6a9	2766	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
mbed_official	85:e1a8e879a6a9	2767	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2768	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2769	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2770
mbed_official	85:e1a8e879a6a9	2771	/* Bit 3 : Enable interrupt on IN[3] event. */
mbed_official	85:e1a8e879a6a9	2772	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
mbed_official	85:e1a8e879a6a9	2773	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
mbed_official	85:e1a8e879a6a9	2774	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2775	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2776	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2777
mbed_official	85:e1a8e879a6a9	2778	/* Bit 2 : Enable interrupt on IN[2] event. */
mbed_official	85:e1a8e879a6a9	2779	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
mbed_official	85:e1a8e879a6a9	2780	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
mbed_official	85:e1a8e879a6a9	2781	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2782	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2783	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2784
mbed_official	85:e1a8e879a6a9	2785	/* Bit 1 : Enable interrupt on IN[1] event. */
mbed_official	85:e1a8e879a6a9	2786	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
mbed_official	85:e1a8e879a6a9	2787	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
mbed_official	85:e1a8e879a6a9	2788	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2789	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2790	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2791
mbed_official	85:e1a8e879a6a9	2792	/* Bit 0 : Enable interrupt on IN[0] event. */
mbed_official	85:e1a8e879a6a9	2793	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
mbed_official	85:e1a8e879a6a9	2794	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
mbed_official	85:e1a8e879a6a9	2795	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2796	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2797	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2798
mbed_official	85:e1a8e879a6a9	2799	/* Register: GPIOTE_INTENCLR */
mbed_official	85:e1a8e879a6a9	2800	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	2801
mbed_official	85:e1a8e879a6a9	2802	/* Bit 31 : Disable interrupt on PORT event. */
mbed_official	85:e1a8e879a6a9	2803	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
mbed_official	85:e1a8e879a6a9	2804	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
mbed_official	85:e1a8e879a6a9	2805	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2806	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2807	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2808
mbed_official	85:e1a8e879a6a9	2809	/* Bit 3 : Disable interrupt on IN[3] event. */
mbed_official	85:e1a8e879a6a9	2810	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
mbed_official	85:e1a8e879a6a9	2811	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
mbed_official	85:e1a8e879a6a9	2812	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2813	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2814	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2815
mbed_official	85:e1a8e879a6a9	2816	/* Bit 2 : Disable interrupt on IN[2] event. */
mbed_official	85:e1a8e879a6a9	2817	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
mbed_official	85:e1a8e879a6a9	2818	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
mbed_official	85:e1a8e879a6a9	2819	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2820	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2821	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2822
mbed_official	85:e1a8e879a6a9	2823	/* Bit 1 : Disable interrupt on IN[1] event. */
mbed_official	85:e1a8e879a6a9	2824	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
mbed_official	85:e1a8e879a6a9	2825	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
mbed_official	85:e1a8e879a6a9	2826	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2827	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2828	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2829
mbed_official	85:e1a8e879a6a9	2830	/* Bit 0 : Disable interrupt on IN[0] event. */
mbed_official	85:e1a8e879a6a9	2831	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
mbed_official	85:e1a8e879a6a9	2832	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
mbed_official	85:e1a8e879a6a9	2833	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2834	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2835	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2836
mbed_official	85:e1a8e879a6a9	2837	/* Register: GPIOTE_CONFIG */
mbed_official	85:e1a8e879a6a9	2838	/* Description: Channel configuration registers. */
mbed_official	85:e1a8e879a6a9	2839
mbed_official	85:e1a8e879a6a9	2840	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
mbed_official	85:e1a8e879a6a9	2841	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
mbed_official	85:e1a8e879a6a9	2842	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
mbed_official	85:e1a8e879a6a9	2843	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
mbed_official	85:e1a8e879a6a9	2844	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
mbed_official	85:e1a8e879a6a9	2845
mbed_official	85:e1a8e879a6a9	2846	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
mbed_official	85:e1a8e879a6a9	2847	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
mbed_official	85:e1a8e879a6a9	2848	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
mbed_official	85:e1a8e879a6a9	2849	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
mbed_official	85:e1a8e879a6a9	2850	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
mbed_official	85:e1a8e879a6a9	2851	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
mbed_official	85:e1a8e879a6a9	2852
mbed_official	85:e1a8e879a6a9	2853	/* Bits 12..8 : Pin select. */
mbed_official	85:e1a8e879a6a9	2854	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
mbed_official	85:e1a8e879a6a9	2855	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
mbed_official	85:e1a8e879a6a9	2856
mbed_official	85:e1a8e879a6a9	2857	/* Bits 1..0 : Mode */
mbed_official	85:e1a8e879a6a9	2858	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
mbed_official	85:e1a8e879a6a9	2859	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
mbed_official	85:e1a8e879a6a9	2860	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	2861	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
mbed_official	85:e1a8e879a6a9	2862	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
mbed_official	85:e1a8e879a6a9	2863
mbed_official	85:e1a8e879a6a9	2864	/* Register: GPIOTE_POWER */
mbed_official	85:e1a8e879a6a9	2865	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	2866
mbed_official	85:e1a8e879a6a9	2867	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	2868	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	2869	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	2870	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	2871	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	2872
mbed_official	85:e1a8e879a6a9	2873
mbed_official	85:e1a8e879a6a9	2874	/* Peripheral: LPCOMP */
mbed_official	501:36015dec7d16	2875	/* Description: Low power comparator. */
mbed_official	85:e1a8e879a6a9	2876
mbed_official	85:e1a8e879a6a9	2877	/* Register: LPCOMP_SHORTS */
mbed_official	501:36015dec7d16	2878	/* Description: Shortcuts for the LPCOMP. */
mbed_official	501:36015dec7d16	2879
mbed_official	501:36015dec7d16	2880	/* Bit 4 : Shortcut between CROSS event and STOP task. */
mbed_official	85:e1a8e879a6a9	2881	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
mbed_official	85:e1a8e879a6a9	2882	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
mbed_official	85:e1a8e879a6a9	2883	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	2884	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	2885
mbed_official	501:36015dec7d16	2886	/* Bit 3 : Shortcut between UP event and STOP task. */
mbed_official	85:e1a8e879a6a9	2887	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
mbed_official	85:e1a8e879a6a9	2888	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
mbed_official	85:e1a8e879a6a9	2889	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	2890	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	2891
mbed_official	501:36015dec7d16	2892	/* Bit 2 : Shortcut between DOWN event and STOP task. */
mbed_official	85:e1a8e879a6a9	2893	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
mbed_official	85:e1a8e879a6a9	2894	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
mbed_official	85:e1a8e879a6a9	2895	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	2896	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	2897
mbed_official	501:36015dec7d16	2898	/* Bit 1 : Shortcut between RADY event and STOP task. */
mbed_official	85:e1a8e879a6a9	2899	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
mbed_official	85:e1a8e879a6a9	2900	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
mbed_official	85:e1a8e879a6a9	2901	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	2902	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	2903
mbed_official	501:36015dec7d16	2904	/* Bit 0 : Shortcut between READY event and SAMPLE task. */
mbed_official	85:e1a8e879a6a9	2905	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
mbed_official	85:e1a8e879a6a9	2906	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
mbed_official	85:e1a8e879a6a9	2907	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	2908	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	2909
mbed_official	85:e1a8e879a6a9	2910	/* Register: LPCOMP_INTENSET */
mbed_official	85:e1a8e879a6a9	2911	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	2912
mbed_official	85:e1a8e879a6a9	2913	/* Bit 3 : Enable interrupt on CROSS event. */
mbed_official	85:e1a8e879a6a9	2914	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
mbed_official	85:e1a8e879a6a9	2915	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
mbed_official	85:e1a8e879a6a9	2916	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2917	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2918	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2919
mbed_official	85:e1a8e879a6a9	2920	/* Bit 2 : Enable interrupt on UP event. */
mbed_official	85:e1a8e879a6a9	2921	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
mbed_official	85:e1a8e879a6a9	2922	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
mbed_official	85:e1a8e879a6a9	2923	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2924	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2925	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2926
mbed_official	85:e1a8e879a6a9	2927	/* Bit 1 : Enable interrupt on DOWN event. */
mbed_official	85:e1a8e879a6a9	2928	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
mbed_official	85:e1a8e879a6a9	2929	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
mbed_official	85:e1a8e879a6a9	2930	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2931	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2932	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2933
mbed_official	85:e1a8e879a6a9	2934	/* Bit 0 : Enable interrupt on READY event. */
mbed_official	85:e1a8e879a6a9	2935	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
mbed_official	85:e1a8e879a6a9	2936	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
mbed_official	85:e1a8e879a6a9	2937	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2938	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2939	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2940
mbed_official	85:e1a8e879a6a9	2941	/* Register: LPCOMP_INTENCLR */
mbed_official	85:e1a8e879a6a9	2942	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	2943
mbed_official	85:e1a8e879a6a9	2944	/* Bit 3 : Disable interrupt on CROSS event. */
mbed_official	85:e1a8e879a6a9	2945	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
mbed_official	85:e1a8e879a6a9	2946	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
mbed_official	85:e1a8e879a6a9	2947	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2948	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2949	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2950
mbed_official	85:e1a8e879a6a9	2951	/* Bit 2 : Disable interrupt on UP event. */
mbed_official	85:e1a8e879a6a9	2952	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
mbed_official	85:e1a8e879a6a9	2953	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
mbed_official	85:e1a8e879a6a9	2954	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2955	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2956	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2957
mbed_official	85:e1a8e879a6a9	2958	/* Bit 1 : Disable interrupt on DOWN event. */
mbed_official	85:e1a8e879a6a9	2959	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
mbed_official	85:e1a8e879a6a9	2960	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
mbed_official	85:e1a8e879a6a9	2961	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2962	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2963	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2964
mbed_official	85:e1a8e879a6a9	2965	/* Bit 0 : Disable interrupt on READY event. */
mbed_official	85:e1a8e879a6a9	2966	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
mbed_official	85:e1a8e879a6a9	2967	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
mbed_official	85:e1a8e879a6a9	2968	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	2969	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	2970	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	2971
mbed_official	85:e1a8e879a6a9	2972	/* Register: LPCOMP_RESULT */
mbed_official	85:e1a8e879a6a9	2973	/* Description: Result of last compare. */
mbed_official	85:e1a8e879a6a9	2974
mbed_official	85:e1a8e879a6a9	2975	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
mbed_official	85:e1a8e879a6a9	2976	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
mbed_official	85:e1a8e879a6a9	2977	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
mbed_official	85:e1a8e879a6a9	2978	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
mbed_official	85:e1a8e879a6a9	2979	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
mbed_official	85:e1a8e879a6a9	2980
mbed_official	85:e1a8e879a6a9	2981	/* Register: LPCOMP_ENABLE */
mbed_official	85:e1a8e879a6a9	2982	/* Description: Enable the LPCOMP. */
mbed_official	85:e1a8e879a6a9	2983
mbed_official	85:e1a8e879a6a9	2984	/* Bits 1..0 : Enable or disable LPCOMP. */
mbed_official	85:e1a8e879a6a9	2985	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
mbed_official	85:e1a8e879a6a9	2986	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
mbed_official	85:e1a8e879a6a9	2987	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
mbed_official	85:e1a8e879a6a9	2988	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
mbed_official	85:e1a8e879a6a9	2989
mbed_official	85:e1a8e879a6a9	2990	/* Register: LPCOMP_PSEL */
mbed_official	85:e1a8e879a6a9	2991	/* Description: Input pin select. */
mbed_official	85:e1a8e879a6a9	2992
mbed_official	85:e1a8e879a6a9	2993	/* Bits 2..0 : Analog input pin select. */
mbed_official	85:e1a8e879a6a9	2994	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
mbed_official	85:e1a8e879a6a9	2995	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
mbed_official	85:e1a8e879a6a9	2996	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
mbed_official	85:e1a8e879a6a9	2997	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
mbed_official	85:e1a8e879a6a9	2998	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
mbed_official	85:e1a8e879a6a9	2999	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
mbed_official	85:e1a8e879a6a9	3000	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
mbed_official	85:e1a8e879a6a9	3001	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
mbed_official	85:e1a8e879a6a9	3002	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
mbed_official	85:e1a8e879a6a9	3003	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
mbed_official	85:e1a8e879a6a9	3004
mbed_official	85:e1a8e879a6a9	3005	/* Register: LPCOMP_REFSEL */
mbed_official	85:e1a8e879a6a9	3006	/* Description: Reference select. */
mbed_official	85:e1a8e879a6a9	3007
mbed_official	85:e1a8e879a6a9	3008	/* Bits 2..0 : Reference select. */
mbed_official	85:e1a8e879a6a9	3009	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
mbed_official	85:e1a8e879a6a9	3010	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
mbed_official	501:36015dec7d16	3011	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use supply with a 1/8 prescaler as reference. /
mbed_official	501:36015dec7d16	3012	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use supply with a 2/8 prescaler as reference. /
mbed_official	501:36015dec7d16	3013	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use supply with a 3/8 prescaler as reference. /
mbed_official	501:36015dec7d16	3014	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use supply with a 4/8 prescaler as reference. /
mbed_official	501:36015dec7d16	3015	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use supply with a 5/8 prescaler as reference. /
mbed_official	501:36015dec7d16	3016	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use supply with a 6/8 prescaler as reference. /
mbed_official	501:36015dec7d16	3017	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use supply with a 7/8 prescaler as reference. /
mbed_official	85:e1a8e879a6a9	3018	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
mbed_official	85:e1a8e879a6a9	3019
mbed_official	85:e1a8e879a6a9	3020	/* Register: LPCOMP_EXTREFSEL */
mbed_official	85:e1a8e879a6a9	3021	/* Description: External reference select. */
mbed_official	85:e1a8e879a6a9	3022
mbed_official	85:e1a8e879a6a9	3023	/* Bit 0 : External analog reference pin selection. */
mbed_official	85:e1a8e879a6a9	3024	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
mbed_official	85:e1a8e879a6a9	3025	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
mbed_official	85:e1a8e879a6a9	3026	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
mbed_official	85:e1a8e879a6a9	3027	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
mbed_official	85:e1a8e879a6a9	3028
mbed_official	85:e1a8e879a6a9	3029	/* Register: LPCOMP_ANADETECT */
mbed_official	85:e1a8e879a6a9	3030	/* Description: Analog detect configuration. */
mbed_official	85:e1a8e879a6a9	3031
mbed_official	85:e1a8e879a6a9	3032	/* Bits 1..0 : Analog detect configuration. */
mbed_official	85:e1a8e879a6a9	3033	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
mbed_official	85:e1a8e879a6a9	3034	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
mbed_official	85:e1a8e879a6a9	3035	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
mbed_official	85:e1a8e879a6a9	3036	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
mbed_official	85:e1a8e879a6a9	3037	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
mbed_official	85:e1a8e879a6a9	3038
mbed_official	85:e1a8e879a6a9	3039	/* Register: LPCOMP_POWER */
mbed_official	85:e1a8e879a6a9	3040	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	3041
mbed_official	85:e1a8e879a6a9	3042	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	3043	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	3044	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	3045	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	3046	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	3047
mbed_official	85:e1a8e879a6a9	3048
mbed_official	85:e1a8e879a6a9	3049	/* Peripheral: MPU */
mbed_official	85:e1a8e879a6a9	3050	/* Description: Memory Protection Unit. */
mbed_official	85:e1a8e879a6a9	3051
mbed_official	85:e1a8e879a6a9	3052	/* Register: MPU_PERR0 */
mbed_official	85:e1a8e879a6a9	3053	/* Description: Configuration of peripherals in mpu regions. */
mbed_official	85:e1a8e879a6a9	3054
mbed_official	85:e1a8e879a6a9	3055	/* Bit 31 : PPI region configuration. */
mbed_official	85:e1a8e879a6a9	3056	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
mbed_official	85:e1a8e879a6a9	3057	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
mbed_official	85:e1a8e879a6a9	3058	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3059	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3060
mbed_official	85:e1a8e879a6a9	3061	/* Bit 30 : NVMC region configuration. */
mbed_official	85:e1a8e879a6a9	3062	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
mbed_official	85:e1a8e879a6a9	3063	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
mbed_official	85:e1a8e879a6a9	3064	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3065	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3066
mbed_official	501:36015dec7d16	3067	/* Bit 19 : LPCOMP region configuration. */
mbed_official	501:36015dec7d16	3068	#define MPU_PERR0_LPCOMP_Pos (19UL) /!< Position of LPCOMP field. /
mbed_official	501:36015dec7d16	3069	#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
mbed_official	501:36015dec7d16	3070	#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	501:36015dec7d16	3071	#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3072
mbed_official	85:e1a8e879a6a9	3073	/* Bit 18 : QDEC region configuration. */
mbed_official	85:e1a8e879a6a9	3074	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
mbed_official	85:e1a8e879a6a9	3075	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
mbed_official	85:e1a8e879a6a9	3076	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3077	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3078
mbed_official	85:e1a8e879a6a9	3079	/* Bit 17 : RTC1 region configuration. */
mbed_official	85:e1a8e879a6a9	3080	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
mbed_official	85:e1a8e879a6a9	3081	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
mbed_official	85:e1a8e879a6a9	3082	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3083	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3084
mbed_official	85:e1a8e879a6a9	3085	/* Bit 16 : WDT region configuration. */
mbed_official	85:e1a8e879a6a9	3086	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
mbed_official	85:e1a8e879a6a9	3087	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
mbed_official	85:e1a8e879a6a9	3088	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3089	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3090
mbed_official	85:e1a8e879a6a9	3091	/* Bit 15 : CCM and AAR region configuration. */
mbed_official	85:e1a8e879a6a9	3092	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
mbed_official	85:e1a8e879a6a9	3093	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
mbed_official	85:e1a8e879a6a9	3094	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3095	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3096
mbed_official	85:e1a8e879a6a9	3097	/* Bit 14 : ECB region configuration. */
mbed_official	85:e1a8e879a6a9	3098	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
mbed_official	85:e1a8e879a6a9	3099	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
mbed_official	85:e1a8e879a6a9	3100	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3101	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3102
mbed_official	85:e1a8e879a6a9	3103	/* Bit 13 : RNG region configuration. */
mbed_official	85:e1a8e879a6a9	3104	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
mbed_official	85:e1a8e879a6a9	3105	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
mbed_official	85:e1a8e879a6a9	3106	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3107	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3108
mbed_official	85:e1a8e879a6a9	3109	/* Bit 12 : TEMP region configuration. */
mbed_official	85:e1a8e879a6a9	3110	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
mbed_official	85:e1a8e879a6a9	3111	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
mbed_official	85:e1a8e879a6a9	3112	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3113	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3114
mbed_official	85:e1a8e879a6a9	3115	/* Bit 11 : RTC0 region configuration. */
mbed_official	85:e1a8e879a6a9	3116	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
mbed_official	85:e1a8e879a6a9	3117	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
mbed_official	85:e1a8e879a6a9	3118	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3119	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3120
mbed_official	85:e1a8e879a6a9	3121	/* Bit 10 : TIMER2 region configuration. */
mbed_official	85:e1a8e879a6a9	3122	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
mbed_official	85:e1a8e879a6a9	3123	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
mbed_official	85:e1a8e879a6a9	3124	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3125	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3126
mbed_official	85:e1a8e879a6a9	3127	/* Bit 9 : TIMER1 region configuration. */
mbed_official	85:e1a8e879a6a9	3128	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
mbed_official	85:e1a8e879a6a9	3129	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
mbed_official	85:e1a8e879a6a9	3130	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3131	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3132
mbed_official	85:e1a8e879a6a9	3133	/* Bit 8 : TIMER0 region configuration. */
mbed_official	85:e1a8e879a6a9	3134	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
mbed_official	85:e1a8e879a6a9	3135	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
mbed_official	85:e1a8e879a6a9	3136	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3137	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3138
mbed_official	85:e1a8e879a6a9	3139	/* Bit 7 : ADC region configuration. */
mbed_official	85:e1a8e879a6a9	3140	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
mbed_official	85:e1a8e879a6a9	3141	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
mbed_official	85:e1a8e879a6a9	3142	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3143	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3144
mbed_official	85:e1a8e879a6a9	3145	/* Bit 6 : GPIOTE region configuration. */
mbed_official	85:e1a8e879a6a9	3146	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
mbed_official	85:e1a8e879a6a9	3147	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
mbed_official	85:e1a8e879a6a9	3148	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3149	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3150
mbed_official	85:e1a8e879a6a9	3151	/* Bit 4 : SPI1 and TWI1 region configuration. */
mbed_official	85:e1a8e879a6a9	3152	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
mbed_official	85:e1a8e879a6a9	3153	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
mbed_official	85:e1a8e879a6a9	3154	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3155	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3156
mbed_official	85:e1a8e879a6a9	3157	/* Bit 3 : SPI0 and TWI0 region configuration. */
mbed_official	85:e1a8e879a6a9	3158	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
mbed_official	85:e1a8e879a6a9	3159	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
mbed_official	85:e1a8e879a6a9	3160	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3161	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3162
mbed_official	85:e1a8e879a6a9	3163	/* Bit 2 : UART0 region configuration. */
mbed_official	85:e1a8e879a6a9	3164	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
mbed_official	85:e1a8e879a6a9	3165	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
mbed_official	85:e1a8e879a6a9	3166	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3167	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3168
mbed_official	85:e1a8e879a6a9	3169	/* Bit 1 : RADIO region configuration. */
mbed_official	85:e1a8e879a6a9	3170	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
mbed_official	85:e1a8e879a6a9	3171	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
mbed_official	85:e1a8e879a6a9	3172	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3173	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3174
mbed_official	85:e1a8e879a6a9	3175	/* Bit 0 : POWER_CLOCK region configuration. */
mbed_official	85:e1a8e879a6a9	3176	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
mbed_official	85:e1a8e879a6a9	3177	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
mbed_official	85:e1a8e879a6a9	3178	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
mbed_official	85:e1a8e879a6a9	3179	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
mbed_official	85:e1a8e879a6a9	3180
mbed_official	85:e1a8e879a6a9	3181	/* Register: MPU_PROTENSET0 */
mbed_official	501:36015dec7d16	3182	/* Description: Erase and write protection bit enable set register. */
mbed_official	85:e1a8e879a6a9	3183
mbed_official	85:e1a8e879a6a9	3184	/* Bit 31 : Protection enable for region 31. */
mbed_official	85:e1a8e879a6a9	3185	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
mbed_official	85:e1a8e879a6a9	3186	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
mbed_official	85:e1a8e879a6a9	3187	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3188	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3189	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3190
mbed_official	85:e1a8e879a6a9	3191	/* Bit 30 : Protection enable for region 30. */
mbed_official	85:e1a8e879a6a9	3192	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
mbed_official	85:e1a8e879a6a9	3193	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
mbed_official	85:e1a8e879a6a9	3194	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3195	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3196	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3197
mbed_official	85:e1a8e879a6a9	3198	/* Bit 29 : Protection enable for region 29. */
mbed_official	85:e1a8e879a6a9	3199	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
mbed_official	85:e1a8e879a6a9	3200	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
mbed_official	85:e1a8e879a6a9	3201	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3202	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3203	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3204
mbed_official	85:e1a8e879a6a9	3205	/* Bit 28 : Protection enable for region 28. */
mbed_official	85:e1a8e879a6a9	3206	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
mbed_official	85:e1a8e879a6a9	3207	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
mbed_official	85:e1a8e879a6a9	3208	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3209	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3210	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3211
mbed_official	85:e1a8e879a6a9	3212	/* Bit 27 : Protection enable for region 27. */
mbed_official	85:e1a8e879a6a9	3213	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
mbed_official	85:e1a8e879a6a9	3214	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
mbed_official	85:e1a8e879a6a9	3215	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3216	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3217	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3218
mbed_official	85:e1a8e879a6a9	3219	/* Bit 26 : Protection enable for region 26. */
mbed_official	85:e1a8e879a6a9	3220	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
mbed_official	85:e1a8e879a6a9	3221	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
mbed_official	85:e1a8e879a6a9	3222	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3223	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3224	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3225
mbed_official	85:e1a8e879a6a9	3226	/* Bit 25 : Protection enable for region 25. */
mbed_official	85:e1a8e879a6a9	3227	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
mbed_official	85:e1a8e879a6a9	3228	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
mbed_official	85:e1a8e879a6a9	3229	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3230	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3231	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3232
mbed_official	85:e1a8e879a6a9	3233	/* Bit 24 : Protection enable for region 24. */
mbed_official	85:e1a8e879a6a9	3234	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
mbed_official	85:e1a8e879a6a9	3235	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
mbed_official	85:e1a8e879a6a9	3236	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3237	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3238	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3239
mbed_official	85:e1a8e879a6a9	3240	/* Bit 23 : Protection enable for region 23. */
mbed_official	85:e1a8e879a6a9	3241	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
mbed_official	85:e1a8e879a6a9	3242	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
mbed_official	85:e1a8e879a6a9	3243	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3244	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3245	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3246
mbed_official	85:e1a8e879a6a9	3247	/* Bit 22 : Protection enable for region 22. */
mbed_official	85:e1a8e879a6a9	3248	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
mbed_official	85:e1a8e879a6a9	3249	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
mbed_official	85:e1a8e879a6a9	3250	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3251	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3252	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3253
mbed_official	85:e1a8e879a6a9	3254	/* Bit 21 : Protection enable for region 21. */
mbed_official	85:e1a8e879a6a9	3255	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
mbed_official	85:e1a8e879a6a9	3256	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
mbed_official	85:e1a8e879a6a9	3257	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3258	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3259	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3260
mbed_official	85:e1a8e879a6a9	3261	/* Bit 20 : Protection enable for region 20. */
mbed_official	85:e1a8e879a6a9	3262	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
mbed_official	85:e1a8e879a6a9	3263	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
mbed_official	85:e1a8e879a6a9	3264	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3265	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3266	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3267
mbed_official	85:e1a8e879a6a9	3268	/* Bit 19 : Protection enable for region 19. */
mbed_official	85:e1a8e879a6a9	3269	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
mbed_official	85:e1a8e879a6a9	3270	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
mbed_official	85:e1a8e879a6a9	3271	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3272	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3273	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3274
mbed_official	85:e1a8e879a6a9	3275	/* Bit 18 : Protection enable for region 18. */
mbed_official	85:e1a8e879a6a9	3276	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
mbed_official	85:e1a8e879a6a9	3277	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
mbed_official	85:e1a8e879a6a9	3278	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3279	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3280	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3281
mbed_official	85:e1a8e879a6a9	3282	/* Bit 17 : Protection enable for region 17. */
mbed_official	85:e1a8e879a6a9	3283	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
mbed_official	85:e1a8e879a6a9	3284	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
mbed_official	85:e1a8e879a6a9	3285	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3286	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3287	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3288
mbed_official	85:e1a8e879a6a9	3289	/* Bit 16 : Protection enable for region 16. */
mbed_official	85:e1a8e879a6a9	3290	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
mbed_official	85:e1a8e879a6a9	3291	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
mbed_official	85:e1a8e879a6a9	3292	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3293	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3294	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3295
mbed_official	85:e1a8e879a6a9	3296	/* Bit 15 : Protection enable for region 15. */
mbed_official	85:e1a8e879a6a9	3297	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
mbed_official	85:e1a8e879a6a9	3298	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
mbed_official	85:e1a8e879a6a9	3299	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3300	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3301	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3302
mbed_official	85:e1a8e879a6a9	3303	/* Bit 14 : Protection enable for region 14. */
mbed_official	85:e1a8e879a6a9	3304	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
mbed_official	85:e1a8e879a6a9	3305	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
mbed_official	85:e1a8e879a6a9	3306	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3307	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3308	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3309
mbed_official	85:e1a8e879a6a9	3310	/* Bit 13 : Protection enable for region 13. */
mbed_official	85:e1a8e879a6a9	3311	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
mbed_official	85:e1a8e879a6a9	3312	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
mbed_official	85:e1a8e879a6a9	3313	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3314	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3315	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3316
mbed_official	85:e1a8e879a6a9	3317	/* Bit 12 : Protection enable for region 12. */
mbed_official	85:e1a8e879a6a9	3318	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
mbed_official	85:e1a8e879a6a9	3319	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
mbed_official	85:e1a8e879a6a9	3320	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3321	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3322	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3323
mbed_official	85:e1a8e879a6a9	3324	/* Bit 11 : Protection enable for region 11. */
mbed_official	85:e1a8e879a6a9	3325	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
mbed_official	85:e1a8e879a6a9	3326	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
mbed_official	85:e1a8e879a6a9	3327	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3328	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3329	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3330
mbed_official	85:e1a8e879a6a9	3331	/* Bit 10 : Protection enable for region 10. */
mbed_official	85:e1a8e879a6a9	3332	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
mbed_official	85:e1a8e879a6a9	3333	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
mbed_official	85:e1a8e879a6a9	3334	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3335	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3336	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3337
mbed_official	85:e1a8e879a6a9	3338	/* Bit 9 : Protection enable for region 9. */
mbed_official	85:e1a8e879a6a9	3339	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
mbed_official	85:e1a8e879a6a9	3340	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
mbed_official	85:e1a8e879a6a9	3341	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3342	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3343	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3344
mbed_official	85:e1a8e879a6a9	3345	/* Bit 8 : Protection enable for region 8. */
mbed_official	85:e1a8e879a6a9	3346	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
mbed_official	85:e1a8e879a6a9	3347	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
mbed_official	85:e1a8e879a6a9	3348	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3349	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3350	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3351
mbed_official	85:e1a8e879a6a9	3352	/* Bit 7 : Protection enable for region 7. */
mbed_official	85:e1a8e879a6a9	3353	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
mbed_official	85:e1a8e879a6a9	3354	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
mbed_official	85:e1a8e879a6a9	3355	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3356	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3357	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3358
mbed_official	85:e1a8e879a6a9	3359	/* Bit 6 : Protection enable for region 6. */
mbed_official	85:e1a8e879a6a9	3360	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
mbed_official	85:e1a8e879a6a9	3361	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
mbed_official	85:e1a8e879a6a9	3362	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3363	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3364	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3365
mbed_official	85:e1a8e879a6a9	3366	/* Bit 5 : Protection enable for region 5. */
mbed_official	85:e1a8e879a6a9	3367	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
mbed_official	85:e1a8e879a6a9	3368	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
mbed_official	85:e1a8e879a6a9	3369	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3370	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3371	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3372
mbed_official	85:e1a8e879a6a9	3373	/* Bit 4 : Protection enable for region 4. */
mbed_official	85:e1a8e879a6a9	3374	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
mbed_official	85:e1a8e879a6a9	3375	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
mbed_official	85:e1a8e879a6a9	3376	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3377	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3378	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3379
mbed_official	85:e1a8e879a6a9	3380	/* Bit 3 : Protection enable for region 3. */
mbed_official	85:e1a8e879a6a9	3381	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
mbed_official	85:e1a8e879a6a9	3382	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
mbed_official	85:e1a8e879a6a9	3383	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3384	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3385	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3386
mbed_official	85:e1a8e879a6a9	3387	/* Bit 2 : Protection enable for region 2. */
mbed_official	85:e1a8e879a6a9	3388	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
mbed_official	85:e1a8e879a6a9	3389	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
mbed_official	85:e1a8e879a6a9	3390	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3391	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3392	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3393
mbed_official	85:e1a8e879a6a9	3394	/* Bit 1 : Protection enable for region 1. */
mbed_official	85:e1a8e879a6a9	3395	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
mbed_official	85:e1a8e879a6a9	3396	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
mbed_official	85:e1a8e879a6a9	3397	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3398	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3399	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3400
mbed_official	85:e1a8e879a6a9	3401	/* Bit 0 : Protection enable for region 0. */
mbed_official	85:e1a8e879a6a9	3402	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
mbed_official	85:e1a8e879a6a9	3403	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
mbed_official	85:e1a8e879a6a9	3404	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3405	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3406	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3407
mbed_official	85:e1a8e879a6a9	3408	/* Register: MPU_PROTENSET1 */
mbed_official	501:36015dec7d16	3409	/* Description: Erase and write protection bit enable set register. */
mbed_official	85:e1a8e879a6a9	3410
mbed_official	85:e1a8e879a6a9	3411	/* Bit 31 : Protection enable for region 63. */
mbed_official	85:e1a8e879a6a9	3412	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
mbed_official	85:e1a8e879a6a9	3413	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
mbed_official	85:e1a8e879a6a9	3414	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3415	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3416	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3417
mbed_official	85:e1a8e879a6a9	3418	/* Bit 30 : Protection enable for region 62. */
mbed_official	85:e1a8e879a6a9	3419	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
mbed_official	85:e1a8e879a6a9	3420	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
mbed_official	85:e1a8e879a6a9	3421	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3422	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3423	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3424
mbed_official	85:e1a8e879a6a9	3425	/* Bit 29 : Protection enable for region 61. */
mbed_official	85:e1a8e879a6a9	3426	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
mbed_official	85:e1a8e879a6a9	3427	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
mbed_official	85:e1a8e879a6a9	3428	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3429	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3430	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3431
mbed_official	85:e1a8e879a6a9	3432	/* Bit 28 : Protection enable for region 60. */
mbed_official	85:e1a8e879a6a9	3433	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
mbed_official	85:e1a8e879a6a9	3434	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
mbed_official	85:e1a8e879a6a9	3435	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3436	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3437	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3438
mbed_official	85:e1a8e879a6a9	3439	/* Bit 27 : Protection enable for region 59. */
mbed_official	85:e1a8e879a6a9	3440	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
mbed_official	85:e1a8e879a6a9	3441	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
mbed_official	85:e1a8e879a6a9	3442	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3443	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3444	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3445
mbed_official	85:e1a8e879a6a9	3446	/* Bit 26 : Protection enable for region 58. */
mbed_official	85:e1a8e879a6a9	3447	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
mbed_official	85:e1a8e879a6a9	3448	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
mbed_official	85:e1a8e879a6a9	3449	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3450	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3451	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3452
mbed_official	85:e1a8e879a6a9	3453	/* Bit 25 : Protection enable for region 57. */
mbed_official	85:e1a8e879a6a9	3454	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
mbed_official	85:e1a8e879a6a9	3455	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
mbed_official	85:e1a8e879a6a9	3456	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3457	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3458	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3459
mbed_official	85:e1a8e879a6a9	3460	/* Bit 24 : Protection enable for region 56. */
mbed_official	85:e1a8e879a6a9	3461	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
mbed_official	85:e1a8e879a6a9	3462	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
mbed_official	85:e1a8e879a6a9	3463	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3464	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3465	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3466
mbed_official	85:e1a8e879a6a9	3467	/* Bit 23 : Protection enable for region 55. */
mbed_official	85:e1a8e879a6a9	3468	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
mbed_official	85:e1a8e879a6a9	3469	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
mbed_official	85:e1a8e879a6a9	3470	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3471	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3472	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3473
mbed_official	85:e1a8e879a6a9	3474	/* Bit 22 : Protection enable for region 54. */
mbed_official	85:e1a8e879a6a9	3475	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
mbed_official	85:e1a8e879a6a9	3476	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
mbed_official	85:e1a8e879a6a9	3477	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3478	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3479	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3480
mbed_official	85:e1a8e879a6a9	3481	/* Bit 21 : Protection enable for region 53. */
mbed_official	85:e1a8e879a6a9	3482	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
mbed_official	85:e1a8e879a6a9	3483	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
mbed_official	85:e1a8e879a6a9	3484	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3485	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3486	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3487
mbed_official	85:e1a8e879a6a9	3488	/* Bit 20 : Protection enable for region 52. */
mbed_official	85:e1a8e879a6a9	3489	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
mbed_official	85:e1a8e879a6a9	3490	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
mbed_official	85:e1a8e879a6a9	3491	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3492	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3493	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3494
mbed_official	85:e1a8e879a6a9	3495	/* Bit 19 : Protection enable for region 51. */
mbed_official	85:e1a8e879a6a9	3496	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
mbed_official	85:e1a8e879a6a9	3497	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
mbed_official	85:e1a8e879a6a9	3498	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3499	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3500	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3501
mbed_official	85:e1a8e879a6a9	3502	/* Bit 18 : Protection enable for region 50. */
mbed_official	85:e1a8e879a6a9	3503	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
mbed_official	85:e1a8e879a6a9	3504	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
mbed_official	85:e1a8e879a6a9	3505	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3506	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3507	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3508
mbed_official	85:e1a8e879a6a9	3509	/* Bit 17 : Protection enable for region 49. */
mbed_official	85:e1a8e879a6a9	3510	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
mbed_official	85:e1a8e879a6a9	3511	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
mbed_official	85:e1a8e879a6a9	3512	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3513	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3514	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3515
mbed_official	85:e1a8e879a6a9	3516	/* Bit 16 : Protection enable for region 48. */
mbed_official	85:e1a8e879a6a9	3517	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
mbed_official	85:e1a8e879a6a9	3518	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
mbed_official	85:e1a8e879a6a9	3519	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3520	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3521	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3522
mbed_official	85:e1a8e879a6a9	3523	/* Bit 15 : Protection enable for region 47. */
mbed_official	85:e1a8e879a6a9	3524	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
mbed_official	85:e1a8e879a6a9	3525	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
mbed_official	85:e1a8e879a6a9	3526	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3527	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3528	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3529
mbed_official	85:e1a8e879a6a9	3530	/* Bit 14 : Protection enable for region 46. */
mbed_official	85:e1a8e879a6a9	3531	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
mbed_official	85:e1a8e879a6a9	3532	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
mbed_official	85:e1a8e879a6a9	3533	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3534	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3535	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3536
mbed_official	85:e1a8e879a6a9	3537	/* Bit 13 : Protection enable for region 45. */
mbed_official	85:e1a8e879a6a9	3538	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
mbed_official	85:e1a8e879a6a9	3539	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
mbed_official	85:e1a8e879a6a9	3540	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3541	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3542	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3543
mbed_official	85:e1a8e879a6a9	3544	/* Bit 12 : Protection enable for region 44. */
mbed_official	85:e1a8e879a6a9	3545	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
mbed_official	85:e1a8e879a6a9	3546	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
mbed_official	85:e1a8e879a6a9	3547	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3548	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3549	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3550
mbed_official	85:e1a8e879a6a9	3551	/* Bit 11 : Protection enable for region 43. */
mbed_official	85:e1a8e879a6a9	3552	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
mbed_official	85:e1a8e879a6a9	3553	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
mbed_official	85:e1a8e879a6a9	3554	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3555	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3556	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3557
mbed_official	85:e1a8e879a6a9	3558	/* Bit 10 : Protection enable for region 42. */
mbed_official	85:e1a8e879a6a9	3559	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
mbed_official	85:e1a8e879a6a9	3560	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
mbed_official	85:e1a8e879a6a9	3561	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3562	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3563	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3564
mbed_official	85:e1a8e879a6a9	3565	/* Bit 9 : Protection enable for region 41. */
mbed_official	85:e1a8e879a6a9	3566	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
mbed_official	85:e1a8e879a6a9	3567	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
mbed_official	85:e1a8e879a6a9	3568	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3569	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3570	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3571
mbed_official	85:e1a8e879a6a9	3572	/* Bit 8 : Protection enable for region 40. */
mbed_official	85:e1a8e879a6a9	3573	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
mbed_official	85:e1a8e879a6a9	3574	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
mbed_official	85:e1a8e879a6a9	3575	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3576	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3577	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3578
mbed_official	85:e1a8e879a6a9	3579	/* Bit 7 : Protection enable for region 39. */
mbed_official	85:e1a8e879a6a9	3580	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
mbed_official	85:e1a8e879a6a9	3581	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
mbed_official	85:e1a8e879a6a9	3582	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3583	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3584	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3585
mbed_official	85:e1a8e879a6a9	3586	/* Bit 6 : Protection enable for region 38. */
mbed_official	85:e1a8e879a6a9	3587	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
mbed_official	85:e1a8e879a6a9	3588	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
mbed_official	85:e1a8e879a6a9	3589	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3590	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3591	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3592
mbed_official	85:e1a8e879a6a9	3593	/* Bit 5 : Protection enable for region 37. */
mbed_official	85:e1a8e879a6a9	3594	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
mbed_official	85:e1a8e879a6a9	3595	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
mbed_official	85:e1a8e879a6a9	3596	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3597	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3598	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3599
mbed_official	85:e1a8e879a6a9	3600	/* Bit 4 : Protection enable for region 36. */
mbed_official	85:e1a8e879a6a9	3601	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
mbed_official	85:e1a8e879a6a9	3602	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
mbed_official	85:e1a8e879a6a9	3603	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3604	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3605	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3606
mbed_official	85:e1a8e879a6a9	3607	/* Bit 3 : Protection enable for region 35. */
mbed_official	85:e1a8e879a6a9	3608	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
mbed_official	85:e1a8e879a6a9	3609	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
mbed_official	85:e1a8e879a6a9	3610	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3611	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3612	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3613
mbed_official	85:e1a8e879a6a9	3614	/* Bit 2 : Protection enable for region 34. */
mbed_official	85:e1a8e879a6a9	3615	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
mbed_official	85:e1a8e879a6a9	3616	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
mbed_official	85:e1a8e879a6a9	3617	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3618	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3619	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3620
mbed_official	85:e1a8e879a6a9	3621	/* Bit 1 : Protection enable for region 33. */
mbed_official	85:e1a8e879a6a9	3622	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
mbed_official	85:e1a8e879a6a9	3623	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
mbed_official	85:e1a8e879a6a9	3624	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3625	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3626	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3627
mbed_official	85:e1a8e879a6a9	3628	/* Bit 0 : Protection enable for region 32. */
mbed_official	85:e1a8e879a6a9	3629	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
mbed_official	85:e1a8e879a6a9	3630	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
mbed_official	85:e1a8e879a6a9	3631	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3632	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3633	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
mbed_official	85:e1a8e879a6a9	3634
mbed_official	85:e1a8e879a6a9	3635	/* Register: MPU_DISABLEINDEBUG */
mbed_official	501:36015dec7d16	3636	/* Description: Disable erase and write protection mechanism in debug mode. */
mbed_official	85:e1a8e879a6a9	3637
mbed_official	85:e1a8e879a6a9	3638	/* Bit 0 : Disable protection mechanism in debug mode. */
mbed_official	85:e1a8e879a6a9	3639	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
mbed_official	85:e1a8e879a6a9	3640	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
mbed_official	85:e1a8e879a6a9	3641	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
mbed_official	85:e1a8e879a6a9	3642	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
mbed_official	85:e1a8e879a6a9	3643
mbed_official	501:36015dec7d16	3644	/* Register: MPU_PROTBLOCKSIZE */
mbed_official	501:36015dec7d16	3645	/* Description: Erase and write protection block size. */
mbed_official	501:36015dec7d16	3646
mbed_official	501:36015dec7d16	3647	/* Bits 1..0 : Erase and write protection block size. */
mbed_official	501:36015dec7d16	3648	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /!< Position of PROTBLOCKSIZE field. /
mbed_official	501:36015dec7d16	3649	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /!< Bit mask of PROTBLOCKSIZE field. /
mbed_official	501:36015dec7d16	3650	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /!< Erase and write protection block size is 4k. /
mbed_official	501:36015dec7d16	3651
mbed_official	85:e1a8e879a6a9	3652
mbed_official	85:e1a8e879a6a9	3653	/* Peripheral: NVMC */
mbed_official	85:e1a8e879a6a9	3654	/* Description: Non Volatile Memory Controller. */
mbed_official	85:e1a8e879a6a9	3655
mbed_official	85:e1a8e879a6a9	3656	/* Register: NVMC_READY */
mbed_official	85:e1a8e879a6a9	3657	/* Description: Ready flag. */
mbed_official	85:e1a8e879a6a9	3658
mbed_official	85:e1a8e879a6a9	3659	/* Bit 0 : NVMC ready. */
mbed_official	85:e1a8e879a6a9	3660	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
mbed_official	85:e1a8e879a6a9	3661	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
mbed_official	85:e1a8e879a6a9	3662	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
mbed_official	85:e1a8e879a6a9	3663	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
mbed_official	85:e1a8e879a6a9	3664
mbed_official	85:e1a8e879a6a9	3665	/* Register: NVMC_CONFIG */
mbed_official	85:e1a8e879a6a9	3666	/* Description: Configuration register. */
mbed_official	85:e1a8e879a6a9	3667
mbed_official	85:e1a8e879a6a9	3668	/* Bits 1..0 : Program write enable. */
mbed_official	85:e1a8e879a6a9	3669	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
mbed_official	85:e1a8e879a6a9	3670	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
mbed_official	85:e1a8e879a6a9	3671	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
mbed_official	85:e1a8e879a6a9	3672	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
mbed_official	85:e1a8e879a6a9	3673	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
mbed_official	85:e1a8e879a6a9	3674
mbed_official	85:e1a8e879a6a9	3675	/* Register: NVMC_ERASEALL */
mbed_official	85:e1a8e879a6a9	3676	/* Description: Register for erasing all non-volatile user memory. */
mbed_official	85:e1a8e879a6a9	3677
mbed_official	85:e1a8e879a6a9	3678	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
mbed_official	85:e1a8e879a6a9	3679	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
mbed_official	85:e1a8e879a6a9	3680	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
mbed_official	85:e1a8e879a6a9	3681	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
mbed_official	85:e1a8e879a6a9	3682	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
mbed_official	85:e1a8e879a6a9	3683
mbed_official	85:e1a8e879a6a9	3684	/* Register: NVMC_ERASEUICR */
mbed_official	85:e1a8e879a6a9	3685	/* Description: Register for start erasing User Information Congfiguration Registers. */
mbed_official	85:e1a8e879a6a9	3686
mbed_official	85:e1a8e879a6a9	3687	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
mbed_official	85:e1a8e879a6a9	3688	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
mbed_official	85:e1a8e879a6a9	3689	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
mbed_official	85:e1a8e879a6a9	3690	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
mbed_official	85:e1a8e879a6a9	3691	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
mbed_official	85:e1a8e879a6a9	3692
mbed_official	85:e1a8e879a6a9	3693
mbed_official	85:e1a8e879a6a9	3694	/* Peripheral: POWER */
mbed_official	85:e1a8e879a6a9	3695	/* Description: Power Control. */
mbed_official	85:e1a8e879a6a9	3696
mbed_official	85:e1a8e879a6a9	3697	/* Register: POWER_INTENSET */
mbed_official	85:e1a8e879a6a9	3698	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	3699
mbed_official	85:e1a8e879a6a9	3700	/* Bit 2 : Enable interrupt on POFWARN event. */
mbed_official	85:e1a8e879a6a9	3701	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
mbed_official	85:e1a8e879a6a9	3702	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
mbed_official	85:e1a8e879a6a9	3703	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	3704	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	3705	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	3706
mbed_official	85:e1a8e879a6a9	3707	/* Register: POWER_INTENCLR */
mbed_official	85:e1a8e879a6a9	3708	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	3709
mbed_official	85:e1a8e879a6a9	3710	/* Bit 2 : Disable interrupt on POFWARN event. */
mbed_official	85:e1a8e879a6a9	3711	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
mbed_official	85:e1a8e879a6a9	3712	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
mbed_official	85:e1a8e879a6a9	3713	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	3714	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	3715	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	3716
mbed_official	85:e1a8e879a6a9	3717	/* Register: POWER_RESETREAS */
mbed_official	85:e1a8e879a6a9	3718	/* Description: Reset reason. */
mbed_official	85:e1a8e879a6a9	3719
mbed_official	85:e1a8e879a6a9	3720	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
mbed_official	85:e1a8e879a6a9	3721	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
mbed_official	85:e1a8e879a6a9	3722	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
mbed_official	85:e1a8e879a6a9	3723
mbed_official	85:e1a8e879a6a9	3724	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
mbed_official	85:e1a8e879a6a9	3725	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
mbed_official	85:e1a8e879a6a9	3726	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
mbed_official	85:e1a8e879a6a9	3727
mbed_official	85:e1a8e879a6a9	3728	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
mbed_official	85:e1a8e879a6a9	3729	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
mbed_official	85:e1a8e879a6a9	3730	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
mbed_official	85:e1a8e879a6a9	3731
mbed_official	85:e1a8e879a6a9	3732	/* Bit 3 : Reset from CPU lock-up detected. */
mbed_official	85:e1a8e879a6a9	3733	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
mbed_official	85:e1a8e879a6a9	3734	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
mbed_official	85:e1a8e879a6a9	3735
mbed_official	85:e1a8e879a6a9	3736	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
mbed_official	85:e1a8e879a6a9	3737	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
mbed_official	85:e1a8e879a6a9	3738	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
mbed_official	85:e1a8e879a6a9	3739
mbed_official	85:e1a8e879a6a9	3740	/* Bit 1 : Reset from watchdog detected. */
mbed_official	85:e1a8e879a6a9	3741	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
mbed_official	85:e1a8e879a6a9	3742	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
mbed_official	85:e1a8e879a6a9	3743
mbed_official	85:e1a8e879a6a9	3744	/* Bit 0 : Reset from pin-reset detected. */
mbed_official	85:e1a8e879a6a9	3745	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
mbed_official	85:e1a8e879a6a9	3746	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
mbed_official	85:e1a8e879a6a9	3747
mbed_official	501:36015dec7d16	3748	/* Register: POWER_RAMSTATUS */
mbed_official	501:36015dec7d16	3749	/* Description: Ram status register. */
mbed_official	501:36015dec7d16	3750
mbed_official	501:36015dec7d16	3751	/* Bit 3 : RAM block 3 status. */
mbed_official	501:36015dec7d16	3752	#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /!< Position of RAMBLOCK3 field. /
mbed_official	501:36015dec7d16	3753	#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /!< Bit mask of RAMBLOCK3 field. /
mbed_official	501:36015dec7d16	3754	#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /!< RAM block 3 is off or powering up. /
mbed_official	501:36015dec7d16	3755	#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /!< RAM block 3 is on. /
mbed_official	501:36015dec7d16	3756
mbed_official	501:36015dec7d16	3757	/* Bit 2 : RAM block 2 status. */
mbed_official	501:36015dec7d16	3758	#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /!< Position of RAMBLOCK2 field. /
mbed_official	501:36015dec7d16	3759	#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /!< Bit mask of RAMBLOCK2 field. /
mbed_official	501:36015dec7d16	3760	#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /!< RAM block 2 is off or powering up. /
mbed_official	501:36015dec7d16	3761	#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /!< RAM block 2 is on. /
mbed_official	501:36015dec7d16	3762
mbed_official	501:36015dec7d16	3763	/* Bit 1 : RAM block 1 status. */
mbed_official	501:36015dec7d16	3764	#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /!< Position of RAMBLOCK1 field. /
mbed_official	501:36015dec7d16	3765	#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /!< Bit mask of RAMBLOCK1 field. /
mbed_official	501:36015dec7d16	3766	#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /!< RAM block 1 is off or powering up. /
mbed_official	501:36015dec7d16	3767	#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /!< RAM block 1 is on. /
mbed_official	501:36015dec7d16	3768
mbed_official	501:36015dec7d16	3769	/* Bit 0 : RAM block 0 status. */
mbed_official	501:36015dec7d16	3770	#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /!< Position of RAMBLOCK0 field. /
mbed_official	501:36015dec7d16	3771	#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /!< Bit mask of RAMBLOCK0 field. /
mbed_official	501:36015dec7d16	3772	#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /!< RAM block 0 is off or powering up. /
mbed_official	501:36015dec7d16	3773	#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /!< RAM block 0 is on. /
mbed_official	501:36015dec7d16	3774
mbed_official	85:e1a8e879a6a9	3775	/* Register: POWER_SYSTEMOFF */
mbed_official	85:e1a8e879a6a9	3776	/* Description: System off register. */
mbed_official	85:e1a8e879a6a9	3777
mbed_official	85:e1a8e879a6a9	3778	/* Bit 0 : Enter system off mode. */
mbed_official	85:e1a8e879a6a9	3779	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
mbed_official	85:e1a8e879a6a9	3780	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
mbed_official	85:e1a8e879a6a9	3781	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
mbed_official	85:e1a8e879a6a9	3782
mbed_official	85:e1a8e879a6a9	3783	/* Register: POWER_POFCON */
mbed_official	85:e1a8e879a6a9	3784	/* Description: Power failure configuration. */
mbed_official	85:e1a8e879a6a9	3785
mbed_official	85:e1a8e879a6a9	3786	/* Bits 2..1 : Set threshold level. */
mbed_official	85:e1a8e879a6a9	3787	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
mbed_official	85:e1a8e879a6a9	3788	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
mbed_official	85:e1a8e879a6a9	3789	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
mbed_official	85:e1a8e879a6a9	3790	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
mbed_official	85:e1a8e879a6a9	3791	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
mbed_official	85:e1a8e879a6a9	3792	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
mbed_official	85:e1a8e879a6a9	3793
mbed_official	85:e1a8e879a6a9	3794	/* Bit 0 : Power failure comparator enable. */
mbed_official	85:e1a8e879a6a9	3795	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
mbed_official	85:e1a8e879a6a9	3796	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
mbed_official	85:e1a8e879a6a9	3797	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	3798	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
mbed_official	85:e1a8e879a6a9	3799
mbed_official	85:e1a8e879a6a9	3800	/* Register: POWER_GPREGRET */
mbed_official	85:e1a8e879a6a9	3801	/* Description: General purpose retention register. This register is a retained register. */
mbed_official	85:e1a8e879a6a9	3802
mbed_official	85:e1a8e879a6a9	3803	/* Bits 7..0 : General purpose retention register. */
mbed_official	85:e1a8e879a6a9	3804	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
mbed_official	85:e1a8e879a6a9	3805	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
mbed_official	85:e1a8e879a6a9	3806
mbed_official	85:e1a8e879a6a9	3807	/* Register: POWER_RAMON */
mbed_official	85:e1a8e879a6a9	3808	/* Description: Ram on/off. */
mbed_official	85:e1a8e879a6a9	3809
mbed_official	85:e1a8e879a6a9	3810	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
mbed_official	85:e1a8e879a6a9	3811	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
mbed_official	85:e1a8e879a6a9	3812	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
mbed_official	85:e1a8e879a6a9	3813	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
mbed_official	85:e1a8e879a6a9	3814	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
mbed_official	85:e1a8e879a6a9	3815
mbed_official	85:e1a8e879a6a9	3816	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
mbed_official	85:e1a8e879a6a9	3817	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
mbed_official	85:e1a8e879a6a9	3818	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
mbed_official	85:e1a8e879a6a9	3819	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
mbed_official	85:e1a8e879a6a9	3820	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
mbed_official	85:e1a8e879a6a9	3821
mbed_official	85:e1a8e879a6a9	3822	/* Bit 1 : RAM block 1 behaviour in ON mode. */
mbed_official	85:e1a8e879a6a9	3823	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
mbed_official	85:e1a8e879a6a9	3824	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
mbed_official	85:e1a8e879a6a9	3825	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
mbed_official	85:e1a8e879a6a9	3826	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
mbed_official	85:e1a8e879a6a9	3827
mbed_official	85:e1a8e879a6a9	3828	/* Bit 0 : RAM block 0 behaviour in ON mode. */
mbed_official	85:e1a8e879a6a9	3829	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
mbed_official	85:e1a8e879a6a9	3830	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
mbed_official	85:e1a8e879a6a9	3831	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
mbed_official	85:e1a8e879a6a9	3832	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
mbed_official	85:e1a8e879a6a9	3833
mbed_official	85:e1a8e879a6a9	3834	/* Register: POWER_RESET */
mbed_official	85:e1a8e879a6a9	3835	/* Description: Pin reset functionality configuration register. This register is a retained register. */
mbed_official	85:e1a8e879a6a9	3836
mbed_official	501:36015dec7d16	3837	/* Bit 0 : Enable or disable pin reset in debug interface mode. */
mbed_official	85:e1a8e879a6a9	3838	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
mbed_official	85:e1a8e879a6a9	3839	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
mbed_official	85:e1a8e879a6a9	3840	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
mbed_official	85:e1a8e879a6a9	3841	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
mbed_official	85:e1a8e879a6a9	3842
mbed_official	501:36015dec7d16	3843	/* Register: POWER_RAMONB */
mbed_official	501:36015dec7d16	3844	/* Description: Ram on/off. */
mbed_official	501:36015dec7d16	3845
mbed_official	501:36015dec7d16	3846	/* Bit 17 : RAM block 3 behaviour in OFF mode. */
mbed_official	501:36015dec7d16	3847	#define POWER_RAMONB_OFFRAM3_Pos (17UL) /!< Position of OFFRAM3 field. /
mbed_official	501:36015dec7d16	3848	#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
mbed_official	501:36015dec7d16	3849	#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
mbed_official	501:36015dec7d16	3850	#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
mbed_official	501:36015dec7d16	3851
mbed_official	501:36015dec7d16	3852	/* Bit 16 : RAM block 2 behaviour in OFF mode. */
mbed_official	501:36015dec7d16	3853	#define POWER_RAMONB_OFFRAM2_Pos (16UL) /!< Position of OFFRAM2 field. /
mbed_official	501:36015dec7d16	3854	#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
mbed_official	501:36015dec7d16	3855	#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
mbed_official	501:36015dec7d16	3856	#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
mbed_official	501:36015dec7d16	3857
mbed_official	501:36015dec7d16	3858	/* Bit 1 : RAM block 3 behaviour in ON mode. */
mbed_official	501:36015dec7d16	3859	#define POWER_RAMONB_ONRAM3_Pos (1UL) /!< Position of ONRAM3 field. /
mbed_official	501:36015dec7d16	3860	#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
mbed_official	501:36015dec7d16	3861	#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /!< RAM block 33 OFF in ON mode. /
mbed_official	501:36015dec7d16	3862	#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
mbed_official	501:36015dec7d16	3863
mbed_official	501:36015dec7d16	3864	/* Bit 0 : RAM block 2 behaviour in ON mode. */
mbed_official	501:36015dec7d16	3865	#define POWER_RAMONB_ONRAM2_Pos (0UL) /!< Position of ONRAM2 field. /
mbed_official	501:36015dec7d16	3866	#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
mbed_official	501:36015dec7d16	3867	#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
mbed_official	501:36015dec7d16	3868	#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
mbed_official	501:36015dec7d16	3869
mbed_official	85:e1a8e879a6a9	3870	/* Register: POWER_DCDCEN */
mbed_official	85:e1a8e879a6a9	3871	/* Description: DCDC converter enable configuration register. */
mbed_official	85:e1a8e879a6a9	3872
mbed_official	85:e1a8e879a6a9	3873	/* Bit 0 : Enable DCDC converter. */
mbed_official	85:e1a8e879a6a9	3874	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
mbed_official	85:e1a8e879a6a9	3875	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
mbed_official	85:e1a8e879a6a9	3876	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
mbed_official	85:e1a8e879a6a9	3877	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
mbed_official	85:e1a8e879a6a9	3878
mbed_official	501:36015dec7d16	3879	/* Register: POWER_DCDCFORCE */
mbed_official	501:36015dec7d16	3880	/* Description: DCDC power-up force register. */
mbed_official	501:36015dec7d16	3881
mbed_official	501:36015dec7d16	3882	/* Bit 1 : DCDC power-up force on. */
mbed_official	501:36015dec7d16	3883	#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /!< Position of FORCEON field. /
mbed_official	501:36015dec7d16	3884	#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /!< Bit mask of FORCEON field. /
mbed_official	501:36015dec7d16	3885	#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /!< No force. /
mbed_official	501:36015dec7d16	3886	#define POWER_DCDCFORCE_FORCEON_Force (1UL) /!< Force. /
mbed_official	501:36015dec7d16	3887
mbed_official	501:36015dec7d16	3888	/* Bit 0 : DCDC power-up force off. */
mbed_official	501:36015dec7d16	3889	#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /!< Position of FORCEOFF field. /
mbed_official	501:36015dec7d16	3890	#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /!< Bit mask of FORCEOFF field. /
mbed_official	501:36015dec7d16	3891	#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /!< No force. /
mbed_official	501:36015dec7d16	3892	#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /!< Force. /
mbed_official	501:36015dec7d16	3893
mbed_official	85:e1a8e879a6a9	3894
mbed_official	85:e1a8e879a6a9	3895	/* Peripheral: PPI */
mbed_official	85:e1a8e879a6a9	3896	/* Description: PPI controller. */
mbed_official	85:e1a8e879a6a9	3897
mbed_official	85:e1a8e879a6a9	3898	/* Register: PPI_CHEN */
mbed_official	85:e1a8e879a6a9	3899	/* Description: Channel enable. */
mbed_official	85:e1a8e879a6a9	3900
mbed_official	85:e1a8e879a6a9	3901	/* Bit 31 : Enable PPI channel 31. */
mbed_official	85:e1a8e879a6a9	3902	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
mbed_official	85:e1a8e879a6a9	3903	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
mbed_official	85:e1a8e879a6a9	3904	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3905	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3906
mbed_official	85:e1a8e879a6a9	3907	/* Bit 30 : Enable PPI channel 30. */
mbed_official	85:e1a8e879a6a9	3908	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
mbed_official	85:e1a8e879a6a9	3909	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
mbed_official	85:e1a8e879a6a9	3910	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3911	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3912
mbed_official	85:e1a8e879a6a9	3913	/* Bit 29 : Enable PPI channel 29. */
mbed_official	85:e1a8e879a6a9	3914	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
mbed_official	85:e1a8e879a6a9	3915	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
mbed_official	85:e1a8e879a6a9	3916	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3917	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3918
mbed_official	85:e1a8e879a6a9	3919	/* Bit 28 : Enable PPI channel 28. */
mbed_official	85:e1a8e879a6a9	3920	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
mbed_official	85:e1a8e879a6a9	3921	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
mbed_official	85:e1a8e879a6a9	3922	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3923	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3924
mbed_official	85:e1a8e879a6a9	3925	/* Bit 27 : Enable PPI channel 27. */
mbed_official	85:e1a8e879a6a9	3926	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
mbed_official	85:e1a8e879a6a9	3927	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
mbed_official	85:e1a8e879a6a9	3928	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3929	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3930
mbed_official	85:e1a8e879a6a9	3931	/* Bit 26 : Enable PPI channel 26. */
mbed_official	85:e1a8e879a6a9	3932	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
mbed_official	85:e1a8e879a6a9	3933	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
mbed_official	85:e1a8e879a6a9	3934	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3935	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3936
mbed_official	85:e1a8e879a6a9	3937	/* Bit 25 : Enable PPI channel 25. */
mbed_official	85:e1a8e879a6a9	3938	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
mbed_official	85:e1a8e879a6a9	3939	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
mbed_official	85:e1a8e879a6a9	3940	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3941	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3942
mbed_official	85:e1a8e879a6a9	3943	/* Bit 24 : Enable PPI channel 24. */
mbed_official	85:e1a8e879a6a9	3944	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
mbed_official	85:e1a8e879a6a9	3945	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
mbed_official	85:e1a8e879a6a9	3946	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3947	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3948
mbed_official	85:e1a8e879a6a9	3949	/* Bit 23 : Enable PPI channel 23. */
mbed_official	85:e1a8e879a6a9	3950	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
mbed_official	85:e1a8e879a6a9	3951	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
mbed_official	85:e1a8e879a6a9	3952	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3953	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3954
mbed_official	85:e1a8e879a6a9	3955	/* Bit 22 : Enable PPI channel 22. */
mbed_official	85:e1a8e879a6a9	3956	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
mbed_official	85:e1a8e879a6a9	3957	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
mbed_official	85:e1a8e879a6a9	3958	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3959	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3960
mbed_official	85:e1a8e879a6a9	3961	/* Bit 21 : Enable PPI channel 21. */
mbed_official	85:e1a8e879a6a9	3962	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
mbed_official	85:e1a8e879a6a9	3963	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
mbed_official	85:e1a8e879a6a9	3964	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3965	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3966
mbed_official	85:e1a8e879a6a9	3967	/* Bit 20 : Enable PPI channel 20. */
mbed_official	85:e1a8e879a6a9	3968	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
mbed_official	85:e1a8e879a6a9	3969	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
mbed_official	85:e1a8e879a6a9	3970	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3971	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3972
mbed_official	85:e1a8e879a6a9	3973	/* Bit 15 : Enable PPI channel 15. */
mbed_official	85:e1a8e879a6a9	3974	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
mbed_official	85:e1a8e879a6a9	3975	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
mbed_official	85:e1a8e879a6a9	3976	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3977	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3978
mbed_official	85:e1a8e879a6a9	3979	/* Bit 14 : Enable PPI channel 14. */
mbed_official	85:e1a8e879a6a9	3980	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
mbed_official	85:e1a8e879a6a9	3981	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
mbed_official	85:e1a8e879a6a9	3982	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3983	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3984
mbed_official	85:e1a8e879a6a9	3985	/* Bit 13 : Enable PPI channel 13. */
mbed_official	85:e1a8e879a6a9	3986	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
mbed_official	85:e1a8e879a6a9	3987	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
mbed_official	85:e1a8e879a6a9	3988	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3989	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3990
mbed_official	85:e1a8e879a6a9	3991	/* Bit 12 : Enable PPI channel 12. */
mbed_official	85:e1a8e879a6a9	3992	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
mbed_official	85:e1a8e879a6a9	3993	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
mbed_official	85:e1a8e879a6a9	3994	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	3995	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	3996
mbed_official	85:e1a8e879a6a9	3997	/* Bit 11 : Enable PPI channel 11. */
mbed_official	85:e1a8e879a6a9	3998	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
mbed_official	85:e1a8e879a6a9	3999	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
mbed_official	85:e1a8e879a6a9	4000	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4001	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4002
mbed_official	85:e1a8e879a6a9	4003	/* Bit 10 : Enable PPI channel 10. */
mbed_official	85:e1a8e879a6a9	4004	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
mbed_official	85:e1a8e879a6a9	4005	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
mbed_official	85:e1a8e879a6a9	4006	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4007	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4008
mbed_official	85:e1a8e879a6a9	4009	/* Bit 9 : Enable PPI channel 9. */
mbed_official	85:e1a8e879a6a9	4010	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
mbed_official	85:e1a8e879a6a9	4011	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
mbed_official	85:e1a8e879a6a9	4012	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4013	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4014
mbed_official	85:e1a8e879a6a9	4015	/* Bit 8 : Enable PPI channel 8. */
mbed_official	85:e1a8e879a6a9	4016	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
mbed_official	85:e1a8e879a6a9	4017	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
mbed_official	85:e1a8e879a6a9	4018	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4019	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4020
mbed_official	85:e1a8e879a6a9	4021	/* Bit 7 : Enable PPI channel 7. */
mbed_official	85:e1a8e879a6a9	4022	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
mbed_official	85:e1a8e879a6a9	4023	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
mbed_official	85:e1a8e879a6a9	4024	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4025	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4026
mbed_official	85:e1a8e879a6a9	4027	/* Bit 6 : Enable PPI channel 6. */
mbed_official	85:e1a8e879a6a9	4028	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
mbed_official	85:e1a8e879a6a9	4029	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
mbed_official	85:e1a8e879a6a9	4030	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4031	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4032
mbed_official	85:e1a8e879a6a9	4033	/* Bit 5 : Enable PPI channel 5. */
mbed_official	85:e1a8e879a6a9	4034	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
mbed_official	85:e1a8e879a6a9	4035	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
mbed_official	85:e1a8e879a6a9	4036	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4037	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4038
mbed_official	85:e1a8e879a6a9	4039	/* Bit 4 : Enable PPI channel 4. */
mbed_official	85:e1a8e879a6a9	4040	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
mbed_official	85:e1a8e879a6a9	4041	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
mbed_official	85:e1a8e879a6a9	4042	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4043	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4044
mbed_official	85:e1a8e879a6a9	4045	/* Bit 3 : Enable PPI channel 3. */
mbed_official	85:e1a8e879a6a9	4046	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
mbed_official	85:e1a8e879a6a9	4047	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
mbed_official	85:e1a8e879a6a9	4048	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
mbed_official	85:e1a8e879a6a9	4049	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
mbed_official	85:e1a8e879a6a9	4050
mbed_official	85:e1a8e879a6a9	4051	/* Bit 2 : Enable PPI channel 2. */
mbed_official	85:e1a8e879a6a9	4052	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
mbed_official	85:e1a8e879a6a9	4053	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
mbed_official	85:e1a8e879a6a9	4054	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4055	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4056
mbed_official	85:e1a8e879a6a9	4057	/* Bit 1 : Enable PPI channel 1. */
mbed_official	85:e1a8e879a6a9	4058	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
mbed_official	85:e1a8e879a6a9	4059	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
mbed_official	85:e1a8e879a6a9	4060	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4061	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4062
mbed_official	85:e1a8e879a6a9	4063	/* Bit 0 : Enable PPI channel 0. */
mbed_official	85:e1a8e879a6a9	4064	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
mbed_official	85:e1a8e879a6a9	4065	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
mbed_official	85:e1a8e879a6a9	4066	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4067	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4068
mbed_official	85:e1a8e879a6a9	4069	/* Register: PPI_CHENSET */
mbed_official	85:e1a8e879a6a9	4070	/* Description: Channel enable set. */
mbed_official	85:e1a8e879a6a9	4071
mbed_official	85:e1a8e879a6a9	4072	/* Bit 31 : Enable PPI channel 31. */
mbed_official	85:e1a8e879a6a9	4073	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
mbed_official	85:e1a8e879a6a9	4074	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
mbed_official	85:e1a8e879a6a9	4075	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4076	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4077	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4078
mbed_official	85:e1a8e879a6a9	4079	/* Bit 30 : Enable PPI channel 30. */
mbed_official	85:e1a8e879a6a9	4080	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
mbed_official	85:e1a8e879a6a9	4081	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
mbed_official	85:e1a8e879a6a9	4082	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4083	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4084	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4085
mbed_official	85:e1a8e879a6a9	4086	/* Bit 29 : Enable PPI channel 29. */
mbed_official	85:e1a8e879a6a9	4087	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
mbed_official	85:e1a8e879a6a9	4088	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
mbed_official	85:e1a8e879a6a9	4089	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4090	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4091	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4092
mbed_official	85:e1a8e879a6a9	4093	/* Bit 28 : Enable PPI channel 28. */
mbed_official	85:e1a8e879a6a9	4094	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
mbed_official	85:e1a8e879a6a9	4095	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
mbed_official	85:e1a8e879a6a9	4096	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4097	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4098	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4099
mbed_official	85:e1a8e879a6a9	4100	/* Bit 27 : Enable PPI channel 27. */
mbed_official	85:e1a8e879a6a9	4101	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
mbed_official	85:e1a8e879a6a9	4102	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
mbed_official	85:e1a8e879a6a9	4103	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4104	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4105	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4106
mbed_official	85:e1a8e879a6a9	4107	/* Bit 26 : Enable PPI channel 26. */
mbed_official	85:e1a8e879a6a9	4108	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
mbed_official	85:e1a8e879a6a9	4109	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
mbed_official	85:e1a8e879a6a9	4110	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4111	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4112	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4113
mbed_official	85:e1a8e879a6a9	4114	/* Bit 25 : Enable PPI channel 25. */
mbed_official	85:e1a8e879a6a9	4115	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
mbed_official	85:e1a8e879a6a9	4116	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
mbed_official	85:e1a8e879a6a9	4117	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4118	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4119	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4120
mbed_official	85:e1a8e879a6a9	4121	/* Bit 24 : Enable PPI channel 24. */
mbed_official	85:e1a8e879a6a9	4122	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
mbed_official	85:e1a8e879a6a9	4123	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
mbed_official	85:e1a8e879a6a9	4124	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4125	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4126	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4127
mbed_official	85:e1a8e879a6a9	4128	/* Bit 23 : Enable PPI channel 23. */
mbed_official	85:e1a8e879a6a9	4129	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
mbed_official	85:e1a8e879a6a9	4130	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
mbed_official	85:e1a8e879a6a9	4131	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4132	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4133	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4134
mbed_official	85:e1a8e879a6a9	4135	/* Bit 22 : Enable PPI channel 22. */
mbed_official	85:e1a8e879a6a9	4136	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
mbed_official	85:e1a8e879a6a9	4137	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
mbed_official	85:e1a8e879a6a9	4138	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4139	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4140	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4141
mbed_official	85:e1a8e879a6a9	4142	/* Bit 21 : Enable PPI channel 21. */
mbed_official	85:e1a8e879a6a9	4143	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
mbed_official	85:e1a8e879a6a9	4144	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
mbed_official	85:e1a8e879a6a9	4145	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4146	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4147	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4148
mbed_official	85:e1a8e879a6a9	4149	/* Bit 20 : Enable PPI channel 20. */
mbed_official	85:e1a8e879a6a9	4150	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
mbed_official	85:e1a8e879a6a9	4151	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
mbed_official	85:e1a8e879a6a9	4152	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4153	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4154	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4155
mbed_official	85:e1a8e879a6a9	4156	/* Bit 15 : Enable PPI channel 15. */
mbed_official	85:e1a8e879a6a9	4157	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
mbed_official	85:e1a8e879a6a9	4158	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
mbed_official	85:e1a8e879a6a9	4159	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4160	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4161	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4162
mbed_official	85:e1a8e879a6a9	4163	/* Bit 14 : Enable PPI channel 14. */
mbed_official	85:e1a8e879a6a9	4164	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
mbed_official	85:e1a8e879a6a9	4165	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
mbed_official	85:e1a8e879a6a9	4166	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4167	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4168	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4169
mbed_official	85:e1a8e879a6a9	4170	/* Bit 13 : Enable PPI channel 13. */
mbed_official	85:e1a8e879a6a9	4171	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
mbed_official	85:e1a8e879a6a9	4172	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
mbed_official	85:e1a8e879a6a9	4173	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4174	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4175	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4176
mbed_official	85:e1a8e879a6a9	4177	/* Bit 12 : Enable PPI channel 12. */
mbed_official	85:e1a8e879a6a9	4178	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
mbed_official	85:e1a8e879a6a9	4179	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
mbed_official	85:e1a8e879a6a9	4180	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4181	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4182	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4183
mbed_official	85:e1a8e879a6a9	4184	/* Bit 11 : Enable PPI channel 11. */
mbed_official	85:e1a8e879a6a9	4185	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
mbed_official	85:e1a8e879a6a9	4186	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
mbed_official	85:e1a8e879a6a9	4187	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4188	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4189	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4190
mbed_official	85:e1a8e879a6a9	4191	/* Bit 10 : Enable PPI channel 10. */
mbed_official	85:e1a8e879a6a9	4192	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
mbed_official	85:e1a8e879a6a9	4193	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
mbed_official	85:e1a8e879a6a9	4194	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4195	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4196	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4197
mbed_official	85:e1a8e879a6a9	4198	/* Bit 9 : Enable PPI channel 9. */
mbed_official	85:e1a8e879a6a9	4199	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
mbed_official	85:e1a8e879a6a9	4200	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
mbed_official	85:e1a8e879a6a9	4201	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4202	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4203	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4204
mbed_official	85:e1a8e879a6a9	4205	/* Bit 8 : Enable PPI channel 8. */
mbed_official	85:e1a8e879a6a9	4206	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
mbed_official	85:e1a8e879a6a9	4207	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
mbed_official	85:e1a8e879a6a9	4208	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4209	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4210	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4211
mbed_official	85:e1a8e879a6a9	4212	/* Bit 7 : Enable PPI channel 7. */
mbed_official	85:e1a8e879a6a9	4213	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
mbed_official	85:e1a8e879a6a9	4214	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
mbed_official	85:e1a8e879a6a9	4215	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4216	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4217	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4218
mbed_official	85:e1a8e879a6a9	4219	/* Bit 6 : Enable PPI channel 6. */
mbed_official	85:e1a8e879a6a9	4220	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
mbed_official	85:e1a8e879a6a9	4221	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
mbed_official	85:e1a8e879a6a9	4222	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4223	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4224	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4225
mbed_official	85:e1a8e879a6a9	4226	/* Bit 5 : Enable PPI channel 5. */
mbed_official	85:e1a8e879a6a9	4227	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
mbed_official	85:e1a8e879a6a9	4228	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
mbed_official	85:e1a8e879a6a9	4229	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4230	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4231	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4232
mbed_official	85:e1a8e879a6a9	4233	/* Bit 4 : Enable PPI channel 4. */
mbed_official	85:e1a8e879a6a9	4234	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
mbed_official	85:e1a8e879a6a9	4235	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
mbed_official	85:e1a8e879a6a9	4236	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4237	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4238	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4239
mbed_official	85:e1a8e879a6a9	4240	/* Bit 3 : Enable PPI channel 3. */
mbed_official	85:e1a8e879a6a9	4241	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
mbed_official	85:e1a8e879a6a9	4242	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
mbed_official	85:e1a8e879a6a9	4243	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4244	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4245	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4246
mbed_official	85:e1a8e879a6a9	4247	/* Bit 2 : Enable PPI channel 2. */
mbed_official	85:e1a8e879a6a9	4248	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
mbed_official	85:e1a8e879a6a9	4249	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
mbed_official	85:e1a8e879a6a9	4250	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4251	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4252	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4253
mbed_official	85:e1a8e879a6a9	4254	/* Bit 1 : Enable PPI channel 1. */
mbed_official	85:e1a8e879a6a9	4255	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
mbed_official	85:e1a8e879a6a9	4256	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
mbed_official	85:e1a8e879a6a9	4257	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4258	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4259	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4260
mbed_official	85:e1a8e879a6a9	4261	/* Bit 0 : Enable PPI channel 0. */
mbed_official	85:e1a8e879a6a9	4262	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
mbed_official	85:e1a8e879a6a9	4263	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
mbed_official	85:e1a8e879a6a9	4264	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4265	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4266	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
mbed_official	85:e1a8e879a6a9	4267
mbed_official	85:e1a8e879a6a9	4268	/* Register: PPI_CHENCLR */
mbed_official	85:e1a8e879a6a9	4269	/* Description: Channel enable clear. */
mbed_official	85:e1a8e879a6a9	4270
mbed_official	85:e1a8e879a6a9	4271	/* Bit 31 : Disable PPI channel 31. */
mbed_official	85:e1a8e879a6a9	4272	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
mbed_official	85:e1a8e879a6a9	4273	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
mbed_official	85:e1a8e879a6a9	4274	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4275	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4276	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4277
mbed_official	85:e1a8e879a6a9	4278	/* Bit 30 : Disable PPI channel 30. */
mbed_official	85:e1a8e879a6a9	4279	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
mbed_official	85:e1a8e879a6a9	4280	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
mbed_official	85:e1a8e879a6a9	4281	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4282	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4283	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4284
mbed_official	85:e1a8e879a6a9	4285	/* Bit 29 : Disable PPI channel 29. */
mbed_official	85:e1a8e879a6a9	4286	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
mbed_official	85:e1a8e879a6a9	4287	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
mbed_official	85:e1a8e879a6a9	4288	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4289	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4290	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4291
mbed_official	85:e1a8e879a6a9	4292	/* Bit 28 : Disable PPI channel 28. */
mbed_official	85:e1a8e879a6a9	4293	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
mbed_official	85:e1a8e879a6a9	4294	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
mbed_official	85:e1a8e879a6a9	4295	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4296	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4297	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4298
mbed_official	85:e1a8e879a6a9	4299	/* Bit 27 : Disable PPI channel 27. */
mbed_official	85:e1a8e879a6a9	4300	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
mbed_official	85:e1a8e879a6a9	4301	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
mbed_official	85:e1a8e879a6a9	4302	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4303	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4304	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4305
mbed_official	85:e1a8e879a6a9	4306	/* Bit 26 : Disable PPI channel 26. */
mbed_official	85:e1a8e879a6a9	4307	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
mbed_official	85:e1a8e879a6a9	4308	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
mbed_official	85:e1a8e879a6a9	4309	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4310	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4311	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4312
mbed_official	85:e1a8e879a6a9	4313	/* Bit 25 : Disable PPI channel 25. */
mbed_official	85:e1a8e879a6a9	4314	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
mbed_official	85:e1a8e879a6a9	4315	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
mbed_official	85:e1a8e879a6a9	4316	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4317	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4318	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4319
mbed_official	85:e1a8e879a6a9	4320	/* Bit 24 : Disable PPI channel 24. */
mbed_official	85:e1a8e879a6a9	4321	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
mbed_official	85:e1a8e879a6a9	4322	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
mbed_official	85:e1a8e879a6a9	4323	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4324	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4325	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4326
mbed_official	85:e1a8e879a6a9	4327	/* Bit 23 : Disable PPI channel 23. */
mbed_official	85:e1a8e879a6a9	4328	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
mbed_official	85:e1a8e879a6a9	4329	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
mbed_official	85:e1a8e879a6a9	4330	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4331	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4332	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4333
mbed_official	85:e1a8e879a6a9	4334	/* Bit 22 : Disable PPI channel 22. */
mbed_official	85:e1a8e879a6a9	4335	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
mbed_official	85:e1a8e879a6a9	4336	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
mbed_official	85:e1a8e879a6a9	4337	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4338	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4339	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4340
mbed_official	85:e1a8e879a6a9	4341	/* Bit 21 : Disable PPI channel 21. */
mbed_official	85:e1a8e879a6a9	4342	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
mbed_official	85:e1a8e879a6a9	4343	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
mbed_official	85:e1a8e879a6a9	4344	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4345	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4346	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4347
mbed_official	85:e1a8e879a6a9	4348	/* Bit 20 : Disable PPI channel 20. */
mbed_official	85:e1a8e879a6a9	4349	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
mbed_official	85:e1a8e879a6a9	4350	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
mbed_official	85:e1a8e879a6a9	4351	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4352	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4353	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4354
mbed_official	85:e1a8e879a6a9	4355	/* Bit 15 : Disable PPI channel 15. */
mbed_official	85:e1a8e879a6a9	4356	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
mbed_official	85:e1a8e879a6a9	4357	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
mbed_official	85:e1a8e879a6a9	4358	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4359	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4360	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4361
mbed_official	85:e1a8e879a6a9	4362	/* Bit 14 : Disable PPI channel 14. */
mbed_official	85:e1a8e879a6a9	4363	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
mbed_official	85:e1a8e879a6a9	4364	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
mbed_official	85:e1a8e879a6a9	4365	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4366	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4367	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4368
mbed_official	85:e1a8e879a6a9	4369	/* Bit 13 : Disable PPI channel 13. */
mbed_official	85:e1a8e879a6a9	4370	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
mbed_official	85:e1a8e879a6a9	4371	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
mbed_official	85:e1a8e879a6a9	4372	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4373	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4374	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4375
mbed_official	85:e1a8e879a6a9	4376	/* Bit 12 : Disable PPI channel 12. */
mbed_official	85:e1a8e879a6a9	4377	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
mbed_official	85:e1a8e879a6a9	4378	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
mbed_official	85:e1a8e879a6a9	4379	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4380	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4381	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4382
mbed_official	85:e1a8e879a6a9	4383	/* Bit 11 : Disable PPI channel 11. */
mbed_official	85:e1a8e879a6a9	4384	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
mbed_official	85:e1a8e879a6a9	4385	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
mbed_official	85:e1a8e879a6a9	4386	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4387	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4388	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4389
mbed_official	85:e1a8e879a6a9	4390	/* Bit 10 : Disable PPI channel 10. */
mbed_official	85:e1a8e879a6a9	4391	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
mbed_official	85:e1a8e879a6a9	4392	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
mbed_official	85:e1a8e879a6a9	4393	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4394	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4395	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4396
mbed_official	85:e1a8e879a6a9	4397	/* Bit 9 : Disable PPI channel 9. */
mbed_official	85:e1a8e879a6a9	4398	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
mbed_official	85:e1a8e879a6a9	4399	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
mbed_official	85:e1a8e879a6a9	4400	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4401	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4402	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4403
mbed_official	85:e1a8e879a6a9	4404	/* Bit 8 : Disable PPI channel 8. */
mbed_official	85:e1a8e879a6a9	4405	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
mbed_official	85:e1a8e879a6a9	4406	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
mbed_official	85:e1a8e879a6a9	4407	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4408	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4409	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4410
mbed_official	85:e1a8e879a6a9	4411	/* Bit 7 : Disable PPI channel 7. */
mbed_official	85:e1a8e879a6a9	4412	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
mbed_official	85:e1a8e879a6a9	4413	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
mbed_official	85:e1a8e879a6a9	4414	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4415	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4416	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4417
mbed_official	85:e1a8e879a6a9	4418	/* Bit 6 : Disable PPI channel 6. */
mbed_official	85:e1a8e879a6a9	4419	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
mbed_official	85:e1a8e879a6a9	4420	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
mbed_official	85:e1a8e879a6a9	4421	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4422	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4423	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4424
mbed_official	85:e1a8e879a6a9	4425	/* Bit 5 : Disable PPI channel 5. */
mbed_official	85:e1a8e879a6a9	4426	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
mbed_official	85:e1a8e879a6a9	4427	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
mbed_official	85:e1a8e879a6a9	4428	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4429	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4430	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4431
mbed_official	85:e1a8e879a6a9	4432	/* Bit 4 : Disable PPI channel 4. */
mbed_official	85:e1a8e879a6a9	4433	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
mbed_official	85:e1a8e879a6a9	4434	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
mbed_official	85:e1a8e879a6a9	4435	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4436	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4437	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4438
mbed_official	85:e1a8e879a6a9	4439	/* Bit 3 : Disable PPI channel 3. */
mbed_official	85:e1a8e879a6a9	4440	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
mbed_official	85:e1a8e879a6a9	4441	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
mbed_official	85:e1a8e879a6a9	4442	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4443	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4444	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4445
mbed_official	85:e1a8e879a6a9	4446	/* Bit 2 : Disable PPI channel 2. */
mbed_official	85:e1a8e879a6a9	4447	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
mbed_official	85:e1a8e879a6a9	4448	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
mbed_official	85:e1a8e879a6a9	4449	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4450	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4451	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4452
mbed_official	85:e1a8e879a6a9	4453	/* Bit 1 : Disable PPI channel 1. */
mbed_official	85:e1a8e879a6a9	4454	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
mbed_official	85:e1a8e879a6a9	4455	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
mbed_official	85:e1a8e879a6a9	4456	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4457	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4458	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4459
mbed_official	85:e1a8e879a6a9	4460	/* Bit 0 : Disable PPI channel 0. */
mbed_official	85:e1a8e879a6a9	4461	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
mbed_official	85:e1a8e879a6a9	4462	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
mbed_official	85:e1a8e879a6a9	4463	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
mbed_official	85:e1a8e879a6a9	4464	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
mbed_official	85:e1a8e879a6a9	4465	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
mbed_official	85:e1a8e879a6a9	4466
mbed_official	85:e1a8e879a6a9	4467	/* Register: PPI_CHG */
mbed_official	85:e1a8e879a6a9	4468	/* Description: Channel group configuration. */
mbed_official	85:e1a8e879a6a9	4469
mbed_official	85:e1a8e879a6a9	4470	/* Bit 31 : Include CH31 in channel group. */
mbed_official	85:e1a8e879a6a9	4471	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
mbed_official	85:e1a8e879a6a9	4472	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
mbed_official	85:e1a8e879a6a9	4473	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4474	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4475
mbed_official	85:e1a8e879a6a9	4476	/* Bit 30 : Include CH30 in channel group. */
mbed_official	85:e1a8e879a6a9	4477	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
mbed_official	85:e1a8e879a6a9	4478	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
mbed_official	85:e1a8e879a6a9	4479	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4480	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4481
mbed_official	85:e1a8e879a6a9	4482	/* Bit 29 : Include CH29 in channel group. */
mbed_official	85:e1a8e879a6a9	4483	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
mbed_official	85:e1a8e879a6a9	4484	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
mbed_official	85:e1a8e879a6a9	4485	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4486	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4487
mbed_official	85:e1a8e879a6a9	4488	/* Bit 28 : Include CH28 in channel group. */
mbed_official	85:e1a8e879a6a9	4489	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
mbed_official	85:e1a8e879a6a9	4490	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
mbed_official	85:e1a8e879a6a9	4491	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4492	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4493
mbed_official	85:e1a8e879a6a9	4494	/* Bit 27 : Include CH27 in channel group. */
mbed_official	85:e1a8e879a6a9	4495	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
mbed_official	85:e1a8e879a6a9	4496	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
mbed_official	85:e1a8e879a6a9	4497	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4498	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4499
mbed_official	85:e1a8e879a6a9	4500	/* Bit 26 : Include CH26 in channel group. */
mbed_official	85:e1a8e879a6a9	4501	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
mbed_official	85:e1a8e879a6a9	4502	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
mbed_official	85:e1a8e879a6a9	4503	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4504	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4505
mbed_official	85:e1a8e879a6a9	4506	/* Bit 25 : Include CH25 in channel group. */
mbed_official	85:e1a8e879a6a9	4507	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
mbed_official	85:e1a8e879a6a9	4508	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
mbed_official	85:e1a8e879a6a9	4509	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4510	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4511
mbed_official	85:e1a8e879a6a9	4512	/* Bit 24 : Include CH24 in channel group. */
mbed_official	85:e1a8e879a6a9	4513	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
mbed_official	85:e1a8e879a6a9	4514	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
mbed_official	85:e1a8e879a6a9	4515	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4516	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4517
mbed_official	85:e1a8e879a6a9	4518	/* Bit 23 : Include CH23 in channel group. */
mbed_official	85:e1a8e879a6a9	4519	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
mbed_official	85:e1a8e879a6a9	4520	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
mbed_official	85:e1a8e879a6a9	4521	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4522	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4523
mbed_official	85:e1a8e879a6a9	4524	/* Bit 22 : Include CH22 in channel group. */
mbed_official	85:e1a8e879a6a9	4525	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
mbed_official	85:e1a8e879a6a9	4526	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
mbed_official	85:e1a8e879a6a9	4527	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4528	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4529
mbed_official	85:e1a8e879a6a9	4530	/* Bit 21 : Include CH21 in channel group. */
mbed_official	85:e1a8e879a6a9	4531	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
mbed_official	85:e1a8e879a6a9	4532	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
mbed_official	85:e1a8e879a6a9	4533	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4534	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4535
mbed_official	85:e1a8e879a6a9	4536	/* Bit 20 : Include CH20 in channel group. */
mbed_official	85:e1a8e879a6a9	4537	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
mbed_official	85:e1a8e879a6a9	4538	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
mbed_official	85:e1a8e879a6a9	4539	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4540	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4541
mbed_official	85:e1a8e879a6a9	4542	/* Bit 15 : Include CH15 in channel group. */
mbed_official	85:e1a8e879a6a9	4543	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
mbed_official	85:e1a8e879a6a9	4544	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
mbed_official	85:e1a8e879a6a9	4545	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4546	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4547
mbed_official	85:e1a8e879a6a9	4548	/* Bit 14 : Include CH14 in channel group. */
mbed_official	85:e1a8e879a6a9	4549	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
mbed_official	85:e1a8e879a6a9	4550	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
mbed_official	85:e1a8e879a6a9	4551	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4552	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4553
mbed_official	85:e1a8e879a6a9	4554	/* Bit 13 : Include CH13 in channel group. */
mbed_official	85:e1a8e879a6a9	4555	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
mbed_official	85:e1a8e879a6a9	4556	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
mbed_official	85:e1a8e879a6a9	4557	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4558	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4559
mbed_official	85:e1a8e879a6a9	4560	/* Bit 12 : Include CH12 in channel group. */
mbed_official	85:e1a8e879a6a9	4561	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
mbed_official	85:e1a8e879a6a9	4562	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
mbed_official	85:e1a8e879a6a9	4563	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4564	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4565
mbed_official	85:e1a8e879a6a9	4566	/* Bit 11 : Include CH11 in channel group. */
mbed_official	85:e1a8e879a6a9	4567	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
mbed_official	85:e1a8e879a6a9	4568	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
mbed_official	85:e1a8e879a6a9	4569	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4570	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4571
mbed_official	85:e1a8e879a6a9	4572	/* Bit 10 : Include CH10 in channel group. */
mbed_official	85:e1a8e879a6a9	4573	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
mbed_official	85:e1a8e879a6a9	4574	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
mbed_official	85:e1a8e879a6a9	4575	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4576	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4577
mbed_official	85:e1a8e879a6a9	4578	/* Bit 9 : Include CH9 in channel group. */
mbed_official	85:e1a8e879a6a9	4579	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
mbed_official	85:e1a8e879a6a9	4580	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
mbed_official	85:e1a8e879a6a9	4581	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4582	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4583
mbed_official	85:e1a8e879a6a9	4584	/* Bit 8 : Include CH8 in channel group. */
mbed_official	85:e1a8e879a6a9	4585	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
mbed_official	85:e1a8e879a6a9	4586	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
mbed_official	85:e1a8e879a6a9	4587	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4588	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4589
mbed_official	85:e1a8e879a6a9	4590	/* Bit 7 : Include CH7 in channel group. */
mbed_official	85:e1a8e879a6a9	4591	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
mbed_official	85:e1a8e879a6a9	4592	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
mbed_official	85:e1a8e879a6a9	4593	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4594	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4595
mbed_official	85:e1a8e879a6a9	4596	/* Bit 6 : Include CH6 in channel group. */
mbed_official	85:e1a8e879a6a9	4597	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
mbed_official	85:e1a8e879a6a9	4598	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
mbed_official	85:e1a8e879a6a9	4599	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4600	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4601
mbed_official	85:e1a8e879a6a9	4602	/* Bit 5 : Include CH5 in channel group. */
mbed_official	85:e1a8e879a6a9	4603	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
mbed_official	85:e1a8e879a6a9	4604	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
mbed_official	85:e1a8e879a6a9	4605	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4606	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4607
mbed_official	85:e1a8e879a6a9	4608	/* Bit 4 : Include CH4 in channel group. */
mbed_official	85:e1a8e879a6a9	4609	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
mbed_official	85:e1a8e879a6a9	4610	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
mbed_official	85:e1a8e879a6a9	4611	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4612	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4613
mbed_official	85:e1a8e879a6a9	4614	/* Bit 3 : Include CH3 in channel group. */
mbed_official	85:e1a8e879a6a9	4615	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
mbed_official	85:e1a8e879a6a9	4616	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
mbed_official	85:e1a8e879a6a9	4617	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4618	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4619
mbed_official	85:e1a8e879a6a9	4620	/* Bit 2 : Include CH2 in channel group. */
mbed_official	85:e1a8e879a6a9	4621	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
mbed_official	85:e1a8e879a6a9	4622	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
mbed_official	85:e1a8e879a6a9	4623	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4624	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4625
mbed_official	85:e1a8e879a6a9	4626	/* Bit 1 : Include CH1 in channel group. */
mbed_official	85:e1a8e879a6a9	4627	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
mbed_official	85:e1a8e879a6a9	4628	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
mbed_official	85:e1a8e879a6a9	4629	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4630	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4631
mbed_official	85:e1a8e879a6a9	4632	/* Bit 0 : Include CH0 in channel group. */
mbed_official	85:e1a8e879a6a9	4633	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
mbed_official	85:e1a8e879a6a9	4634	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
mbed_official	85:e1a8e879a6a9	4635	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
mbed_official	85:e1a8e879a6a9	4636	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
mbed_official	85:e1a8e879a6a9	4637
mbed_official	85:e1a8e879a6a9	4638
mbed_official	85:e1a8e879a6a9	4639	/* Peripheral: PU */
mbed_official	85:e1a8e879a6a9	4640	/* Description: Patch unit. */
mbed_official	85:e1a8e879a6a9	4641
mbed_official	85:e1a8e879a6a9	4642	/* Register: PU_PATCHADDR */
mbed_official	85:e1a8e879a6a9	4643	/* Description: Relative address of patch instructions. */
mbed_official	85:e1a8e879a6a9	4644
mbed_official	85:e1a8e879a6a9	4645	/* Bits 24..0 : Relative address of patch instructions. */
mbed_official	85:e1a8e879a6a9	4646	#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /!< Position of PATCHADDR field. /
mbed_official	85:e1a8e879a6a9	4647	#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /!< Bit mask of PATCHADDR field. /
mbed_official	85:e1a8e879a6a9	4648
mbed_official	85:e1a8e879a6a9	4649	/* Register: PU_PATCHEN */
mbed_official	85:e1a8e879a6a9	4650	/* Description: Patch enable register. */
mbed_official	85:e1a8e879a6a9	4651
mbed_official	85:e1a8e879a6a9	4652	/* Bit 7 : Patch 7 enabled. */
mbed_official	85:e1a8e879a6a9	4653	#define PU_PATCHEN_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
mbed_official	85:e1a8e879a6a9	4654	#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
mbed_official	85:e1a8e879a6a9	4655	#define PU_PATCHEN_PATCH7_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4656	#define PU_PATCHEN_PATCH7_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4657
mbed_official	85:e1a8e879a6a9	4658	/* Bit 6 : Patch 6 enabled. */
mbed_official	85:e1a8e879a6a9	4659	#define PU_PATCHEN_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
mbed_official	85:e1a8e879a6a9	4660	#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
mbed_official	85:e1a8e879a6a9	4661	#define PU_PATCHEN_PATCH6_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4662	#define PU_PATCHEN_PATCH6_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4663
mbed_official	85:e1a8e879a6a9	4664	/* Bit 5 : Patch 5 enabled. */
mbed_official	85:e1a8e879a6a9	4665	#define PU_PATCHEN_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
mbed_official	85:e1a8e879a6a9	4666	#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
mbed_official	85:e1a8e879a6a9	4667	#define PU_PATCHEN_PATCH5_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4668	#define PU_PATCHEN_PATCH5_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4669
mbed_official	85:e1a8e879a6a9	4670	/* Bit 4 : Patch 4 enabled. */
mbed_official	85:e1a8e879a6a9	4671	#define PU_PATCHEN_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
mbed_official	85:e1a8e879a6a9	4672	#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
mbed_official	85:e1a8e879a6a9	4673	#define PU_PATCHEN_PATCH4_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4674	#define PU_PATCHEN_PATCH4_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4675
mbed_official	85:e1a8e879a6a9	4676	/* Bit 3 : Patch 3 enabled. */
mbed_official	85:e1a8e879a6a9	4677	#define PU_PATCHEN_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
mbed_official	85:e1a8e879a6a9	4678	#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
mbed_official	85:e1a8e879a6a9	4679	#define PU_PATCHEN_PATCH3_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4680	#define PU_PATCHEN_PATCH3_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4681
mbed_official	85:e1a8e879a6a9	4682	/* Bit 2 : Patch 2 enabled. */
mbed_official	85:e1a8e879a6a9	4683	#define PU_PATCHEN_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
mbed_official	85:e1a8e879a6a9	4684	#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
mbed_official	85:e1a8e879a6a9	4685	#define PU_PATCHEN_PATCH2_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4686	#define PU_PATCHEN_PATCH2_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4687
mbed_official	85:e1a8e879a6a9	4688	/* Bit 1 : Patch 1 enabled. */
mbed_official	85:e1a8e879a6a9	4689	#define PU_PATCHEN_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
mbed_official	85:e1a8e879a6a9	4690	#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
mbed_official	85:e1a8e879a6a9	4691	#define PU_PATCHEN_PATCH1_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4692	#define PU_PATCHEN_PATCH1_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4693
mbed_official	85:e1a8e879a6a9	4694	/* Bit 0 : Patch 0 enabled. */
mbed_official	85:e1a8e879a6a9	4695	#define PU_PATCHEN_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
mbed_official	85:e1a8e879a6a9	4696	#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
mbed_official	85:e1a8e879a6a9	4697	#define PU_PATCHEN_PATCH0_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4698	#define PU_PATCHEN_PATCH0_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4699
mbed_official	85:e1a8e879a6a9	4700	/* Register: PU_PATCHENSET */
mbed_official	85:e1a8e879a6a9	4701	/* Description: Patch enable register. */
mbed_official	85:e1a8e879a6a9	4702
mbed_official	85:e1a8e879a6a9	4703	/* Bit 7 : Patch 7 enabled. */
mbed_official	85:e1a8e879a6a9	4704	#define PU_PATCHENSET_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
mbed_official	85:e1a8e879a6a9	4705	#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
mbed_official	85:e1a8e879a6a9	4706	#define PU_PATCHENSET_PATCH7_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4707	#define PU_PATCHENSET_PATCH7_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4708	#define PU_PATCHENSET_PATCH7_Set (1UL) /!< Enable patch on write. /
mbed_official	85:e1a8e879a6a9	4709
mbed_official	85:e1a8e879a6a9	4710	/* Bit 6 : Patch 6 enabled. */
mbed_official	85:e1a8e879a6a9	4711	#define PU_PATCHENSET_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
mbed_official	85:e1a8e879a6a9	4712	#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
mbed_official	85:e1a8e879a6a9	4713	#define PU_PATCHENSET_PATCH6_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4714	#define PU_PATCHENSET_PATCH6_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4715	#define PU_PATCHENSET_PATCH6_Set (1UL) /!< Enable patch on write. /
mbed_official	85:e1a8e879a6a9	4716
mbed_official	85:e1a8e879a6a9	4717	/* Bit 5 : Patch 5 enabled. */
mbed_official	85:e1a8e879a6a9	4718	#define PU_PATCHENSET_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
mbed_official	85:e1a8e879a6a9	4719	#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
mbed_official	85:e1a8e879a6a9	4720	#define PU_PATCHENSET_PATCH5_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4721	#define PU_PATCHENSET_PATCH5_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4722	#define PU_PATCHENSET_PATCH5_Set (1UL) /!< Enable patch on write. /
mbed_official	85:e1a8e879a6a9	4723
mbed_official	85:e1a8e879a6a9	4724	/* Bit 4 : Patch 4 enabled. */
mbed_official	85:e1a8e879a6a9	4725	#define PU_PATCHENSET_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
mbed_official	85:e1a8e879a6a9	4726	#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
mbed_official	85:e1a8e879a6a9	4727	#define PU_PATCHENSET_PATCH4_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4728	#define PU_PATCHENSET_PATCH4_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4729	#define PU_PATCHENSET_PATCH4_Set (1UL) /!< Enable patch on write. /
mbed_official	85:e1a8e879a6a9	4730
mbed_official	85:e1a8e879a6a9	4731	/* Bit 3 : Patch 3 enabled. */
mbed_official	85:e1a8e879a6a9	4732	#define PU_PATCHENSET_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
mbed_official	85:e1a8e879a6a9	4733	#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
mbed_official	85:e1a8e879a6a9	4734	#define PU_PATCHENSET_PATCH3_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4735	#define PU_PATCHENSET_PATCH3_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4736	#define PU_PATCHENSET_PATCH3_Set (1UL) /!< Enable patch on write. /
mbed_official	85:e1a8e879a6a9	4737
mbed_official	85:e1a8e879a6a9	4738	/* Bit 2 : Patch 2 enabled. */
mbed_official	85:e1a8e879a6a9	4739	#define PU_PATCHENSET_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
mbed_official	85:e1a8e879a6a9	4740	#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
mbed_official	85:e1a8e879a6a9	4741	#define PU_PATCHENSET_PATCH2_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4742	#define PU_PATCHENSET_PATCH2_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4743	#define PU_PATCHENSET_PATCH2_Set (1UL) /!< Enable patch on write. /
mbed_official	85:e1a8e879a6a9	4744
mbed_official	85:e1a8e879a6a9	4745	/* Bit 1 : Patch 1 enabled. */
mbed_official	85:e1a8e879a6a9	4746	#define PU_PATCHENSET_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
mbed_official	85:e1a8e879a6a9	4747	#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
mbed_official	85:e1a8e879a6a9	4748	#define PU_PATCHENSET_PATCH1_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4749	#define PU_PATCHENSET_PATCH1_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4750	#define PU_PATCHENSET_PATCH1_Set (1UL) /!< Enable patch on write. /
mbed_official	85:e1a8e879a6a9	4751
mbed_official	85:e1a8e879a6a9	4752	/* Bit 0 : Patch 0 enabled. */
mbed_official	85:e1a8e879a6a9	4753	#define PU_PATCHENSET_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
mbed_official	85:e1a8e879a6a9	4754	#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
mbed_official	85:e1a8e879a6a9	4755	#define PU_PATCHENSET_PATCH0_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4756	#define PU_PATCHENSET_PATCH0_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4757	#define PU_PATCHENSET_PATCH0_Set (1UL) /!< Enable patch on write. /
mbed_official	85:e1a8e879a6a9	4758
mbed_official	85:e1a8e879a6a9	4759	/* Register: PU_PATCHENCLR */
mbed_official	85:e1a8e879a6a9	4760	/* Description: Patch disable register. */
mbed_official	85:e1a8e879a6a9	4761
mbed_official	85:e1a8e879a6a9	4762	/* Bit 7 : Patch 7 enabled. */
mbed_official	85:e1a8e879a6a9	4763	#define PU_PATCHENCLR_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
mbed_official	85:e1a8e879a6a9	4764	#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
mbed_official	85:e1a8e879a6a9	4765	#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4766	#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4767	#define PU_PATCHENCLR_PATCH7_Clear (1UL) /!< Disable patch on write. /
mbed_official	85:e1a8e879a6a9	4768
mbed_official	85:e1a8e879a6a9	4769	/* Bit 6 : Patch 6 enabled. */
mbed_official	85:e1a8e879a6a9	4770	#define PU_PATCHENCLR_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
mbed_official	85:e1a8e879a6a9	4771	#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
mbed_official	85:e1a8e879a6a9	4772	#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4773	#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4774	#define PU_PATCHENCLR_PATCH6_Clear (1UL) /!< Disable patch on write. /
mbed_official	85:e1a8e879a6a9	4775
mbed_official	85:e1a8e879a6a9	4776	/* Bit 5 : Patch 5 enabled. */
mbed_official	85:e1a8e879a6a9	4777	#define PU_PATCHENCLR_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
mbed_official	85:e1a8e879a6a9	4778	#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
mbed_official	85:e1a8e879a6a9	4779	#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4780	#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4781	#define PU_PATCHENCLR_PATCH5_Clear (1UL) /!< Disable patch on write. /
mbed_official	85:e1a8e879a6a9	4782
mbed_official	85:e1a8e879a6a9	4783	/* Bit 4 : Patch 4 enabled. */
mbed_official	85:e1a8e879a6a9	4784	#define PU_PATCHENCLR_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
mbed_official	85:e1a8e879a6a9	4785	#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
mbed_official	85:e1a8e879a6a9	4786	#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4787	#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4788	#define PU_PATCHENCLR_PATCH4_Clear (1UL) /!< Disable patch on write. /
mbed_official	85:e1a8e879a6a9	4789
mbed_official	85:e1a8e879a6a9	4790	/* Bit 3 : Patch 3 enabled. */
mbed_official	85:e1a8e879a6a9	4791	#define PU_PATCHENCLR_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
mbed_official	85:e1a8e879a6a9	4792	#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
mbed_official	85:e1a8e879a6a9	4793	#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4794	#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4795	#define PU_PATCHENCLR_PATCH3_Clear (1UL) /!< Disable patch on write. /
mbed_official	85:e1a8e879a6a9	4796
mbed_official	85:e1a8e879a6a9	4797	/* Bit 2 : Patch 2 enabled. */
mbed_official	85:e1a8e879a6a9	4798	#define PU_PATCHENCLR_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
mbed_official	85:e1a8e879a6a9	4799	#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
mbed_official	85:e1a8e879a6a9	4800	#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4801	#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4802	#define PU_PATCHENCLR_PATCH2_Clear (1UL) /!< Disable patch on write. /
mbed_official	85:e1a8e879a6a9	4803
mbed_official	85:e1a8e879a6a9	4804	/* Bit 1 : Patch 1 enabled. */
mbed_official	85:e1a8e879a6a9	4805	#define PU_PATCHENCLR_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
mbed_official	85:e1a8e879a6a9	4806	#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
mbed_official	85:e1a8e879a6a9	4807	#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4808	#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4809	#define PU_PATCHENCLR_PATCH1_Clear (1UL) /!< Disable patch on write. /
mbed_official	85:e1a8e879a6a9	4810
mbed_official	85:e1a8e879a6a9	4811	/* Bit 0 : Patch 0 enabled. */
mbed_official	85:e1a8e879a6a9	4812	#define PU_PATCHENCLR_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
mbed_official	85:e1a8e879a6a9	4813	#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
mbed_official	85:e1a8e879a6a9	4814	#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /!< Patch disabled. /
mbed_official	85:e1a8e879a6a9	4815	#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /!< Patch enabled. /
mbed_official	85:e1a8e879a6a9	4816	#define PU_PATCHENCLR_PATCH0_Clear (1UL) /!< Disable patch on write. /
mbed_official	85:e1a8e879a6a9	4817
mbed_official	85:e1a8e879a6a9	4818
mbed_official	85:e1a8e879a6a9	4819	/* Peripheral: QDEC */
mbed_official	85:e1a8e879a6a9	4820	/* Description: Rotary decoder. */
mbed_official	85:e1a8e879a6a9	4821
mbed_official	85:e1a8e879a6a9	4822	/* Register: QDEC_SHORTS */
mbed_official	501:36015dec7d16	4823	/* Description: Shortcuts for the QDEC. */
mbed_official	501:36015dec7d16	4824
mbed_official	501:36015dec7d16	4825	/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
mbed_official	85:e1a8e879a6a9	4826	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
mbed_official	85:e1a8e879a6a9	4827	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
mbed_official	85:e1a8e879a6a9	4828	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	4829	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	4830
mbed_official	501:36015dec7d16	4831	/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
mbed_official	85:e1a8e879a6a9	4832	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
mbed_official	85:e1a8e879a6a9	4833	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
mbed_official	85:e1a8e879a6a9	4834	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	4835	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	4836
mbed_official	85:e1a8e879a6a9	4837	/* Register: QDEC_INTENSET */
mbed_official	85:e1a8e879a6a9	4838	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	4839
mbed_official	85:e1a8e879a6a9	4840	/* Bit 2 : Enable interrupt on ACCOF event. */
mbed_official	85:e1a8e879a6a9	4841	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
mbed_official	85:e1a8e879a6a9	4842	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
mbed_official	85:e1a8e879a6a9	4843	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	4844	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	4845	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	4846
mbed_official	85:e1a8e879a6a9	4847	/* Bit 1 : Enable interrupt on REPORTRDY event. */
mbed_official	85:e1a8e879a6a9	4848	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
mbed_official	85:e1a8e879a6a9	4849	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
mbed_official	85:e1a8e879a6a9	4850	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	4851	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	4852	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	4853
mbed_official	85:e1a8e879a6a9	4854	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
mbed_official	85:e1a8e879a6a9	4855	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
mbed_official	85:e1a8e879a6a9	4856	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
mbed_official	85:e1a8e879a6a9	4857	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	4858	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	4859	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	4860
mbed_official	85:e1a8e879a6a9	4861	/* Register: QDEC_INTENCLR */
mbed_official	85:e1a8e879a6a9	4862	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	4863
mbed_official	85:e1a8e879a6a9	4864	/* Bit 2 : Disable interrupt on ACCOF event. */
mbed_official	85:e1a8e879a6a9	4865	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
mbed_official	85:e1a8e879a6a9	4866	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
mbed_official	85:e1a8e879a6a9	4867	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	4868	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	4869	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	4870
mbed_official	85:e1a8e879a6a9	4871	/* Bit 1 : Disable interrupt on REPORTRDY event. */
mbed_official	85:e1a8e879a6a9	4872	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
mbed_official	85:e1a8e879a6a9	4873	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
mbed_official	85:e1a8e879a6a9	4874	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	4875	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	4876	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	4877
mbed_official	85:e1a8e879a6a9	4878	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
mbed_official	85:e1a8e879a6a9	4879	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
mbed_official	85:e1a8e879a6a9	4880	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
mbed_official	85:e1a8e879a6a9	4881	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	4882	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	4883	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	4884
mbed_official	85:e1a8e879a6a9	4885	/* Register: QDEC_ENABLE */
mbed_official	85:e1a8e879a6a9	4886	/* Description: Enable the QDEC. */
mbed_official	85:e1a8e879a6a9	4887
mbed_official	85:e1a8e879a6a9	4888	/* Bit 0 : Enable or disable QDEC. */
mbed_official	85:e1a8e879a6a9	4889	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
mbed_official	85:e1a8e879a6a9	4890	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
mbed_official	85:e1a8e879a6a9	4891	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
mbed_official	85:e1a8e879a6a9	4892	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
mbed_official	85:e1a8e879a6a9	4893
mbed_official	85:e1a8e879a6a9	4894	/* Register: QDEC_LEDPOL */
mbed_official	85:e1a8e879a6a9	4895	/* Description: LED output pin polarity. */
mbed_official	85:e1a8e879a6a9	4896
mbed_official	85:e1a8e879a6a9	4897	/* Bit 0 : LED output pin polarity. */
mbed_official	85:e1a8e879a6a9	4898	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
mbed_official	85:e1a8e879a6a9	4899	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
mbed_official	85:e1a8e879a6a9	4900	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
mbed_official	85:e1a8e879a6a9	4901	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
mbed_official	85:e1a8e879a6a9	4902
mbed_official	85:e1a8e879a6a9	4903	/* Register: QDEC_SAMPLEPER */
mbed_official	85:e1a8e879a6a9	4904	/* Description: Sample period. */
mbed_official	85:e1a8e879a6a9	4905
mbed_official	85:e1a8e879a6a9	4906	/* Bits 2..0 : Sample period. */
mbed_official	85:e1a8e879a6a9	4907	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
mbed_official	85:e1a8e879a6a9	4908	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
mbed_official	85:e1a8e879a6a9	4909	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
mbed_official	85:e1a8e879a6a9	4910	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
mbed_official	85:e1a8e879a6a9	4911	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
mbed_official	85:e1a8e879a6a9	4912	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
mbed_official	85:e1a8e879a6a9	4913	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
mbed_official	85:e1a8e879a6a9	4914	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
mbed_official	85:e1a8e879a6a9	4915	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
mbed_official	85:e1a8e879a6a9	4916	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
mbed_official	85:e1a8e879a6a9	4917
mbed_official	85:e1a8e879a6a9	4918	/* Register: QDEC_SAMPLE */
mbed_official	85:e1a8e879a6a9	4919	/* Description: Motion sample value. */
mbed_official	85:e1a8e879a6a9	4920
mbed_official	85:e1a8e879a6a9	4921	/* Bits 31..0 : Last sample taken in compliment to 2. */
mbed_official	85:e1a8e879a6a9	4922	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
mbed_official	85:e1a8e879a6a9	4923	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
mbed_official	85:e1a8e879a6a9	4924
mbed_official	85:e1a8e879a6a9	4925	/* Register: QDEC_REPORTPER */
mbed_official	85:e1a8e879a6a9	4926	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
mbed_official	85:e1a8e879a6a9	4927
mbed_official	85:e1a8e879a6a9	4928	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
mbed_official	85:e1a8e879a6a9	4929	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
mbed_official	85:e1a8e879a6a9	4930	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
mbed_official	85:e1a8e879a6a9	4931	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
mbed_official	85:e1a8e879a6a9	4932	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
mbed_official	85:e1a8e879a6a9	4933	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
mbed_official	85:e1a8e879a6a9	4934	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
mbed_official	85:e1a8e879a6a9	4935	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
mbed_official	85:e1a8e879a6a9	4936	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
mbed_official	85:e1a8e879a6a9	4937	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
mbed_official	85:e1a8e879a6a9	4938	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
mbed_official	85:e1a8e879a6a9	4939
mbed_official	85:e1a8e879a6a9	4940	/* Register: QDEC_DBFEN */
mbed_official	85:e1a8e879a6a9	4941	/* Description: Enable debouncer input filters. */
mbed_official	85:e1a8e879a6a9	4942
mbed_official	85:e1a8e879a6a9	4943	/* Bit 0 : Enable debounce input filters. */
mbed_official	85:e1a8e879a6a9	4944	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
mbed_official	85:e1a8e879a6a9	4945	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
mbed_official	85:e1a8e879a6a9	4946	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
mbed_official	85:e1a8e879a6a9	4947	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
mbed_official	85:e1a8e879a6a9	4948
mbed_official	85:e1a8e879a6a9	4949	/* Register: QDEC_LEDPRE */
mbed_official	85:e1a8e879a6a9	4950	/* Description: Time LED is switched ON before the sample. */
mbed_official	85:e1a8e879a6a9	4951
mbed_official	501:36015dec7d16	4952	/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
mbed_official	85:e1a8e879a6a9	4953	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
mbed_official	501:36015dec7d16	4954	#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
mbed_official	85:e1a8e879a6a9	4955
mbed_official	85:e1a8e879a6a9	4956	/* Register: QDEC_ACCDBL */
mbed_official	85:e1a8e879a6a9	4957	/* Description: Accumulated double (error) transitions register. */
mbed_official	85:e1a8e879a6a9	4958
mbed_official	85:e1a8e879a6a9	4959	/* Bits 3..0 : Accumulated double (error) transitions. */
mbed_official	85:e1a8e879a6a9	4960	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
mbed_official	85:e1a8e879a6a9	4961	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
mbed_official	85:e1a8e879a6a9	4962
mbed_official	85:e1a8e879a6a9	4963	/* Register: QDEC_ACCDBLREAD */
mbed_official	85:e1a8e879a6a9	4964	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
mbed_official	85:e1a8e879a6a9	4965
mbed_official	85:e1a8e879a6a9	4966	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
mbed_official	85:e1a8e879a6a9	4967	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
mbed_official	85:e1a8e879a6a9	4968	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
mbed_official	85:e1a8e879a6a9	4969
mbed_official	85:e1a8e879a6a9	4970	/* Register: QDEC_POWER */
mbed_official	85:e1a8e879a6a9	4971	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	4972
mbed_official	85:e1a8e879a6a9	4973	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	4974	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	4975	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	4976	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	4977	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	4978
mbed_official	85:e1a8e879a6a9	4979
mbed_official	85:e1a8e879a6a9	4980	/* Peripheral: RADIO */
mbed_official	85:e1a8e879a6a9	4981	/* Description: The radio. */
mbed_official	85:e1a8e879a6a9	4982
mbed_official	85:e1a8e879a6a9	4983	/* Register: RADIO_SHORTS */
mbed_official	501:36015dec7d16	4984	/* Description: Shortcuts for the radio. */
mbed_official	85:e1a8e879a6a9	4985
mbed_official	85:e1a8e879a6a9	4986	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
mbed_official	85:e1a8e879a6a9	4987	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
mbed_official	85:e1a8e879a6a9	4988	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
mbed_official	85:e1a8e879a6a9	4989	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	4990	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	4991
mbed_official	85:e1a8e879a6a9	4992	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
mbed_official	85:e1a8e879a6a9	4993	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
mbed_official	85:e1a8e879a6a9	4994	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
mbed_official	85:e1a8e879a6a9	4995	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	4996	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	4997
mbed_official	85:e1a8e879a6a9	4998	/* Bit 5 : Shortcut between END event and START task. */
mbed_official	85:e1a8e879a6a9	4999	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
mbed_official	85:e1a8e879a6a9	5000	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
mbed_official	85:e1a8e879a6a9	5001	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	5002	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	5003
mbed_official	85:e1a8e879a6a9	5004	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
mbed_official	85:e1a8e879a6a9	5005	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
mbed_official	85:e1a8e879a6a9	5006	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
mbed_official	85:e1a8e879a6a9	5007	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	5008	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	5009
mbed_official	85:e1a8e879a6a9	5010	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
mbed_official	85:e1a8e879a6a9	5011	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
mbed_official	85:e1a8e879a6a9	5012	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
mbed_official	85:e1a8e879a6a9	5013	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	5014	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	5015
mbed_official	85:e1a8e879a6a9	5016	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
mbed_official	85:e1a8e879a6a9	5017	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
mbed_official	85:e1a8e879a6a9	5018	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
mbed_official	85:e1a8e879a6a9	5019	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	5020	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	5021
mbed_official	85:e1a8e879a6a9	5022	/* Bit 1 : Shortcut between END event and DISABLE task. */
mbed_official	85:e1a8e879a6a9	5023	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
mbed_official	85:e1a8e879a6a9	5024	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
mbed_official	85:e1a8e879a6a9	5025	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	5026	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	5027
mbed_official	85:e1a8e879a6a9	5028	/* Bit 0 : Shortcut between READY event and START task. */
mbed_official	85:e1a8e879a6a9	5029	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
mbed_official	85:e1a8e879a6a9	5030	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
mbed_official	85:e1a8e879a6a9	5031	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	5032	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	5033
mbed_official	85:e1a8e879a6a9	5034	/* Register: RADIO_INTENSET */
mbed_official	85:e1a8e879a6a9	5035	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	5036
mbed_official	85:e1a8e879a6a9	5037	/* Bit 10 : Enable interrupt on BCMATCH event. */
mbed_official	85:e1a8e879a6a9	5038	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
mbed_official	85:e1a8e879a6a9	5039	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
mbed_official	85:e1a8e879a6a9	5040	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5041	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5042	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5043
mbed_official	85:e1a8e879a6a9	5044	/* Bit 7 : Enable interrupt on RSSIEND event. */
mbed_official	85:e1a8e879a6a9	5045	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
mbed_official	85:e1a8e879a6a9	5046	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
mbed_official	85:e1a8e879a6a9	5047	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5048	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5049	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5050
mbed_official	85:e1a8e879a6a9	5051	/* Bit 6 : Enable interrupt on DEVMISS event. */
mbed_official	85:e1a8e879a6a9	5052	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
mbed_official	85:e1a8e879a6a9	5053	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
mbed_official	85:e1a8e879a6a9	5054	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5055	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5056	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5057
mbed_official	85:e1a8e879a6a9	5058	/* Bit 5 : Enable interrupt on DEVMATCH event. */
mbed_official	85:e1a8e879a6a9	5059	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
mbed_official	85:e1a8e879a6a9	5060	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
mbed_official	85:e1a8e879a6a9	5061	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5062	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5063	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5064
mbed_official	85:e1a8e879a6a9	5065	/* Bit 4 : Enable interrupt on DISABLED event. */
mbed_official	85:e1a8e879a6a9	5066	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
mbed_official	85:e1a8e879a6a9	5067	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
mbed_official	85:e1a8e879a6a9	5068	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5069	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5070	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5071
mbed_official	85:e1a8e879a6a9	5072	/* Bit 3 : Enable interrupt on END event. */
mbed_official	85:e1a8e879a6a9	5073	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
mbed_official	85:e1a8e879a6a9	5074	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
mbed_official	85:e1a8e879a6a9	5075	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5076	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5077	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5078
mbed_official	85:e1a8e879a6a9	5079	/* Bit 2 : Enable interrupt on PAYLOAD event. */
mbed_official	85:e1a8e879a6a9	5080	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
mbed_official	85:e1a8e879a6a9	5081	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
mbed_official	85:e1a8e879a6a9	5082	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5083	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5084	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5085
mbed_official	85:e1a8e879a6a9	5086	/* Bit 1 : Enable interrupt on ADDRESS event. */
mbed_official	85:e1a8e879a6a9	5087	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
mbed_official	85:e1a8e879a6a9	5088	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
mbed_official	85:e1a8e879a6a9	5089	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5090	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5091	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5092
mbed_official	85:e1a8e879a6a9	5093	/* Bit 0 : Enable interrupt on READY event. */
mbed_official	85:e1a8e879a6a9	5094	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
mbed_official	85:e1a8e879a6a9	5095	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
mbed_official	85:e1a8e879a6a9	5096	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5097	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5098	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5099
mbed_official	85:e1a8e879a6a9	5100	/* Register: RADIO_INTENCLR */
mbed_official	85:e1a8e879a6a9	5101	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	5102
mbed_official	85:e1a8e879a6a9	5103	/* Bit 10 : Disable interrupt on BCMATCH event. */
mbed_official	85:e1a8e879a6a9	5104	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
mbed_official	85:e1a8e879a6a9	5105	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
mbed_official	85:e1a8e879a6a9	5106	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5107	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5108	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5109
mbed_official	85:e1a8e879a6a9	5110	/* Bit 7 : Disable interrupt on RSSIEND event. */
mbed_official	85:e1a8e879a6a9	5111	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
mbed_official	85:e1a8e879a6a9	5112	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
mbed_official	85:e1a8e879a6a9	5113	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5114	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5115	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5116
mbed_official	85:e1a8e879a6a9	5117	/* Bit 6 : Disable interrupt on DEVMISS event. */
mbed_official	85:e1a8e879a6a9	5118	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
mbed_official	85:e1a8e879a6a9	5119	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
mbed_official	85:e1a8e879a6a9	5120	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5121	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5122	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5123
mbed_official	85:e1a8e879a6a9	5124	/* Bit 5 : Disable interrupt on DEVMATCH event. */
mbed_official	85:e1a8e879a6a9	5125	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
mbed_official	85:e1a8e879a6a9	5126	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
mbed_official	85:e1a8e879a6a9	5127	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5128	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5129	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5130
mbed_official	85:e1a8e879a6a9	5131	/* Bit 4 : Disable interrupt on DISABLED event. */
mbed_official	85:e1a8e879a6a9	5132	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
mbed_official	85:e1a8e879a6a9	5133	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
mbed_official	85:e1a8e879a6a9	5134	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5135	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5136	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5137
mbed_official	85:e1a8e879a6a9	5138	/* Bit 3 : Disable interrupt on END event. */
mbed_official	85:e1a8e879a6a9	5139	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
mbed_official	85:e1a8e879a6a9	5140	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
mbed_official	85:e1a8e879a6a9	5141	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5142	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5143	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5144
mbed_official	85:e1a8e879a6a9	5145	/* Bit 2 : Disable interrupt on PAYLOAD event. */
mbed_official	85:e1a8e879a6a9	5146	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
mbed_official	85:e1a8e879a6a9	5147	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
mbed_official	85:e1a8e879a6a9	5148	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5149	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5150	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5151
mbed_official	85:e1a8e879a6a9	5152	/* Bit 1 : Disable interrupt on ADDRESS event. */
mbed_official	85:e1a8e879a6a9	5153	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
mbed_official	85:e1a8e879a6a9	5154	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
mbed_official	85:e1a8e879a6a9	5155	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5156	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5157	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5158
mbed_official	85:e1a8e879a6a9	5159	/* Bit 0 : Disable interrupt on READY event. */
mbed_official	85:e1a8e879a6a9	5160	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
mbed_official	85:e1a8e879a6a9	5161	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
mbed_official	85:e1a8e879a6a9	5162	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5163	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5164	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5165
mbed_official	85:e1a8e879a6a9	5166	/* Register: RADIO_CRCSTATUS */
mbed_official	85:e1a8e879a6a9	5167	/* Description: CRC status of received packet. */
mbed_official	85:e1a8e879a6a9	5168
mbed_official	85:e1a8e879a6a9	5169	/* Bit 0 : CRC status of received packet. */
mbed_official	85:e1a8e879a6a9	5170	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
mbed_official	85:e1a8e879a6a9	5171	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
mbed_official	85:e1a8e879a6a9	5172	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
mbed_official	85:e1a8e879a6a9	5173	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
mbed_official	85:e1a8e879a6a9	5174
mbed_official	501:36015dec7d16	5175	/* Register: RADIO_CD */
mbed_official	501:36015dec7d16	5176	/* Description: Carrier detect. */
mbed_official	501:36015dec7d16	5177
mbed_official	501:36015dec7d16	5178	/* Bit 0 : Carrier detect. */
mbed_official	501:36015dec7d16	5179	#define RADIO_CD_CD_Pos (0UL) /!< Position of CD field. /
mbed_official	501:36015dec7d16	5180	#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /!< Bit mask of CD field. /
mbed_official	501:36015dec7d16	5181
mbed_official	85:e1a8e879a6a9	5182	/* Register: RADIO_RXMATCH */
mbed_official	85:e1a8e879a6a9	5183	/* Description: Received address. */
mbed_official	85:e1a8e879a6a9	5184
mbed_official	85:e1a8e879a6a9	5185	/* Bits 2..0 : Logical address in which previous packet was received. */
mbed_official	85:e1a8e879a6a9	5186	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
mbed_official	85:e1a8e879a6a9	5187	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
mbed_official	85:e1a8e879a6a9	5188
mbed_official	85:e1a8e879a6a9	5189	/* Register: RADIO_RXCRC */
mbed_official	85:e1a8e879a6a9	5190	/* Description: Received CRC. */
mbed_official	85:e1a8e879a6a9	5191
mbed_official	85:e1a8e879a6a9	5192	/* Bits 23..0 : CRC field of previously received packet. */
mbed_official	85:e1a8e879a6a9	5193	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
mbed_official	85:e1a8e879a6a9	5194	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
mbed_official	85:e1a8e879a6a9	5195
mbed_official	85:e1a8e879a6a9	5196	/* Register: RADIO_DAI */
mbed_official	85:e1a8e879a6a9	5197	/* Description: Device address match index. */
mbed_official	85:e1a8e879a6a9	5198
mbed_official	501:36015dec7d16	5199	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
mbed_official	85:e1a8e879a6a9	5200	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
mbed_official	85:e1a8e879a6a9	5201	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
mbed_official	85:e1a8e879a6a9	5202
mbed_official	85:e1a8e879a6a9	5203	/* Register: RADIO_FREQUENCY */
mbed_official	85:e1a8e879a6a9	5204	/* Description: Frequency. */
mbed_official	85:e1a8e879a6a9	5205
mbed_official	85:e1a8e879a6a9	5206	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
mbed_official	85:e1a8e879a6a9	5207	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
mbed_official	85:e1a8e879a6a9	5208	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
mbed_official	85:e1a8e879a6a9	5209
mbed_official	85:e1a8e879a6a9	5210	/* Register: RADIO_TXPOWER */
mbed_official	85:e1a8e879a6a9	5211	/* Description: Output power. */
mbed_official	85:e1a8e879a6a9	5212
mbed_official	85:e1a8e879a6a9	5213	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
mbed_official	85:e1a8e879a6a9	5214	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
mbed_official	85:e1a8e879a6a9	5215	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
mbed_official	85:e1a8e879a6a9	5216	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
mbed_official	85:e1a8e879a6a9	5217	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
mbed_official	85:e1a8e879a6a9	5218	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
mbed_official	85:e1a8e879a6a9	5219	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
mbed_official	85:e1a8e879a6a9	5220	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
mbed_official	85:e1a8e879a6a9	5221	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
mbed_official	85:e1a8e879a6a9	5222	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
mbed_official	85:e1a8e879a6a9	5223	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
mbed_official	85:e1a8e879a6a9	5224
mbed_official	85:e1a8e879a6a9	5225	/* Register: RADIO_MODE */
mbed_official	85:e1a8e879a6a9	5226	/* Description: Data rate and modulation. */
mbed_official	85:e1a8e879a6a9	5227
mbed_official	85:e1a8e879a6a9	5228	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
mbed_official	85:e1a8e879a6a9	5229	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
mbed_official	85:e1a8e879a6a9	5230	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
mbed_official	85:e1a8e879a6a9	5231	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
mbed_official	85:e1a8e879a6a9	5232	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
mbed_official	85:e1a8e879a6a9	5233	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
mbed_official	85:e1a8e879a6a9	5234	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
mbed_official	85:e1a8e879a6a9	5235
mbed_official	85:e1a8e879a6a9	5236	/* Register: RADIO_PCNF0 */
mbed_official	85:e1a8e879a6a9	5237	/* Description: Packet configuration 0. */
mbed_official	85:e1a8e879a6a9	5238
mbed_official	85:e1a8e879a6a9	5239	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5240	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
mbed_official	85:e1a8e879a6a9	5241	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
mbed_official	85:e1a8e879a6a9	5242
mbed_official	85:e1a8e879a6a9	5243	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5244	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
mbed_official	85:e1a8e879a6a9	5245	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
mbed_official	85:e1a8e879a6a9	5246
mbed_official	85:e1a8e879a6a9	5247	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5248	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
mbed_official	85:e1a8e879a6a9	5249	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
mbed_official	85:e1a8e879a6a9	5250
mbed_official	85:e1a8e879a6a9	5251	/* Register: RADIO_PCNF1 */
mbed_official	85:e1a8e879a6a9	5252	/* Description: Packet configuration 1. */
mbed_official	85:e1a8e879a6a9	5253
mbed_official	85:e1a8e879a6a9	5254	/* Bit 25 : Packet whitening enable. */
mbed_official	85:e1a8e879a6a9	5255	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
mbed_official	85:e1a8e879a6a9	5256	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
mbed_official	85:e1a8e879a6a9	5257	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
mbed_official	85:e1a8e879a6a9	5258	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
mbed_official	85:e1a8e879a6a9	5259
mbed_official	85:e1a8e879a6a9	5260	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5261	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
mbed_official	85:e1a8e879a6a9	5262	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
mbed_official	85:e1a8e879a6a9	5263	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
mbed_official	85:e1a8e879a6a9	5264	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
mbed_official	85:e1a8e879a6a9	5265
mbed_official	85:e1a8e879a6a9	5266	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5267	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
mbed_official	85:e1a8e879a6a9	5268	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
mbed_official	85:e1a8e879a6a9	5269
mbed_official	85:e1a8e879a6a9	5270	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5271	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
mbed_official	85:e1a8e879a6a9	5272	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
mbed_official	85:e1a8e879a6a9	5273
mbed_official	85:e1a8e879a6a9	5274	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
mbed_official	85:e1a8e879a6a9	5275	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
mbed_official	85:e1a8e879a6a9	5276	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
mbed_official	85:e1a8e879a6a9	5277
mbed_official	85:e1a8e879a6a9	5278	/* Register: RADIO_PREFIX0 */
mbed_official	85:e1a8e879a6a9	5279	/* Description: Prefixes bytes for logical addresses 0 to 3. */
mbed_official	85:e1a8e879a6a9	5280
mbed_official	85:e1a8e879a6a9	5281	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5282	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
mbed_official	85:e1a8e879a6a9	5283	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
mbed_official	85:e1a8e879a6a9	5284
mbed_official	85:e1a8e879a6a9	5285	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5286	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
mbed_official	85:e1a8e879a6a9	5287	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
mbed_official	85:e1a8e879a6a9	5288
mbed_official	85:e1a8e879a6a9	5289	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5290	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
mbed_official	85:e1a8e879a6a9	5291	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
mbed_official	85:e1a8e879a6a9	5292
mbed_official	85:e1a8e879a6a9	5293	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5294	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
mbed_official	85:e1a8e879a6a9	5295	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
mbed_official	85:e1a8e879a6a9	5296
mbed_official	85:e1a8e879a6a9	5297	/* Register: RADIO_PREFIX1 */
mbed_official	85:e1a8e879a6a9	5298	/* Description: Prefixes bytes for logical addresses 4 to 7. */
mbed_official	85:e1a8e879a6a9	5299
mbed_official	85:e1a8e879a6a9	5300	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5301	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
mbed_official	85:e1a8e879a6a9	5302	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
mbed_official	85:e1a8e879a6a9	5303
mbed_official	85:e1a8e879a6a9	5304	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5305	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
mbed_official	85:e1a8e879a6a9	5306	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
mbed_official	85:e1a8e879a6a9	5307
mbed_official	85:e1a8e879a6a9	5308	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5309	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
mbed_official	85:e1a8e879a6a9	5310	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
mbed_official	85:e1a8e879a6a9	5311
mbed_official	85:e1a8e879a6a9	5312	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5313	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
mbed_official	85:e1a8e879a6a9	5314	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
mbed_official	85:e1a8e879a6a9	5315
mbed_official	85:e1a8e879a6a9	5316	/* Register: RADIO_TXADDRESS */
mbed_official	85:e1a8e879a6a9	5317	/* Description: Transmit address select. */
mbed_official	85:e1a8e879a6a9	5318
mbed_official	85:e1a8e879a6a9	5319	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5320	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
mbed_official	85:e1a8e879a6a9	5321	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
mbed_official	85:e1a8e879a6a9	5322
mbed_official	85:e1a8e879a6a9	5323	/* Register: RADIO_RXADDRESSES */
mbed_official	85:e1a8e879a6a9	5324	/* Description: Receive address select. */
mbed_official	85:e1a8e879a6a9	5325
mbed_official	85:e1a8e879a6a9	5326	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5327	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
mbed_official	85:e1a8e879a6a9	5328	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
mbed_official	85:e1a8e879a6a9	5329	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
mbed_official	85:e1a8e879a6a9	5330	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
mbed_official	85:e1a8e879a6a9	5331
mbed_official	85:e1a8e879a6a9	5332	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5333	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
mbed_official	85:e1a8e879a6a9	5334	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
mbed_official	85:e1a8e879a6a9	5335	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
mbed_official	85:e1a8e879a6a9	5336	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
mbed_official	85:e1a8e879a6a9	5337
mbed_official	85:e1a8e879a6a9	5338	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5339	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
mbed_official	85:e1a8e879a6a9	5340	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
mbed_official	85:e1a8e879a6a9	5341	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
mbed_official	85:e1a8e879a6a9	5342	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
mbed_official	85:e1a8e879a6a9	5343
mbed_official	85:e1a8e879a6a9	5344	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5345	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
mbed_official	85:e1a8e879a6a9	5346	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
mbed_official	85:e1a8e879a6a9	5347	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
mbed_official	85:e1a8e879a6a9	5348	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
mbed_official	85:e1a8e879a6a9	5349
mbed_official	85:e1a8e879a6a9	5350	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5351	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
mbed_official	85:e1a8e879a6a9	5352	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
mbed_official	85:e1a8e879a6a9	5353	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
mbed_official	85:e1a8e879a6a9	5354	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
mbed_official	85:e1a8e879a6a9	5355
mbed_official	85:e1a8e879a6a9	5356	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5357	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
mbed_official	85:e1a8e879a6a9	5358	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
mbed_official	85:e1a8e879a6a9	5359	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
mbed_official	85:e1a8e879a6a9	5360	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
mbed_official	85:e1a8e879a6a9	5361
mbed_official	85:e1a8e879a6a9	5362	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5363	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
mbed_official	85:e1a8e879a6a9	5364	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
mbed_official	85:e1a8e879a6a9	5365	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
mbed_official	85:e1a8e879a6a9	5366	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
mbed_official	85:e1a8e879a6a9	5367
mbed_official	85:e1a8e879a6a9	5368	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5369	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
mbed_official	85:e1a8e879a6a9	5370	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
mbed_official	85:e1a8e879a6a9	5371	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
mbed_official	85:e1a8e879a6a9	5372	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
mbed_official	85:e1a8e879a6a9	5373
mbed_official	85:e1a8e879a6a9	5374	/* Register: RADIO_CRCCNF */
mbed_official	85:e1a8e879a6a9	5375	/* Description: CRC configuration. */
mbed_official	85:e1a8e879a6a9	5376
mbed_official	85:e1a8e879a6a9	5377	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
mbed_official	501:36015dec7d16	5378	#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /!< Position of SKIPADDR field. /
mbed_official	501:36015dec7d16	5379	#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /!< Bit mask of SKIPADDR field. /
mbed_official	501:36015dec7d16	5380	#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /!< Include packet address in CRC calculation. /
mbed_official	501:36015dec7d16	5381	#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
mbed_official	85:e1a8e879a6a9	5382
mbed_official	85:e1a8e879a6a9	5383	/* Bits 1..0 : CRC length. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5384	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
mbed_official	85:e1a8e879a6a9	5385	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
mbed_official	85:e1a8e879a6a9	5386	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
mbed_official	85:e1a8e879a6a9	5387	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
mbed_official	85:e1a8e879a6a9	5388	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
mbed_official	85:e1a8e879a6a9	5389	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
mbed_official	85:e1a8e879a6a9	5390
mbed_official	85:e1a8e879a6a9	5391	/* Register: RADIO_CRCPOLY */
mbed_official	85:e1a8e879a6a9	5392	/* Description: CRC polynomial. */
mbed_official	85:e1a8e879a6a9	5393
mbed_official	501:36015dec7d16	5394	/* Bits 23..0 : CRC polynomial. Decision point: START task. */
mbed_official	501:36015dec7d16	5395	#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /!< Position of CRCPOLY field. /
mbed_official	501:36015dec7d16	5396	#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
mbed_official	85:e1a8e879a6a9	5397
mbed_official	85:e1a8e879a6a9	5398	/* Register: RADIO_CRCINIT */
mbed_official	85:e1a8e879a6a9	5399	/* Description: CRC initial value. */
mbed_official	85:e1a8e879a6a9	5400
mbed_official	85:e1a8e879a6a9	5401	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
mbed_official	85:e1a8e879a6a9	5402	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
mbed_official	85:e1a8e879a6a9	5403	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
mbed_official	85:e1a8e879a6a9	5404
mbed_official	85:e1a8e879a6a9	5405	/* Register: RADIO_TEST */
mbed_official	85:e1a8e879a6a9	5406	/* Description: Test features enable register. */
mbed_official	85:e1a8e879a6a9	5407
mbed_official	85:e1a8e879a6a9	5408	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
mbed_official	501:36015dec7d16	5409	#define RADIO_TEST_PLLLOCK_Pos (1UL) /!< Position of PLLLOCK field. /
mbed_official	501:36015dec7d16	5410	#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /!< Bit mask of PLLLOCK field. /
mbed_official	501:36015dec7d16	5411	#define RADIO_TEST_PLLLOCK_Disabled (0UL) /!< PLL lock disabled. /
mbed_official	501:36015dec7d16	5412	#define RADIO_TEST_PLLLOCK_Enabled (1UL) /!< PLL lock enabled. /
mbed_official	85:e1a8e879a6a9	5413
mbed_official	85:e1a8e879a6a9	5414	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
mbed_official	501:36015dec7d16	5415	#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /!< Position of CONSTCARRIER field. /
mbed_official	501:36015dec7d16	5416	#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /!< Bit mask of CONSTCARRIER field. /
mbed_official	501:36015dec7d16	5417	#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /!< Constant carrier disabled. /
mbed_official	501:36015dec7d16	5418	#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /!< Constant carrier enabled. /
mbed_official	85:e1a8e879a6a9	5419
mbed_official	85:e1a8e879a6a9	5420	/* Register: RADIO_TIFS */
mbed_official	85:e1a8e879a6a9	5421	/* Description: Inter Frame Spacing in microseconds. */
mbed_official	85:e1a8e879a6a9	5422
mbed_official	85:e1a8e879a6a9	5423	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
mbed_official	85:e1a8e879a6a9	5424	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
mbed_official	85:e1a8e879a6a9	5425	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
mbed_official	85:e1a8e879a6a9	5426
mbed_official	85:e1a8e879a6a9	5427	/* Register: RADIO_RSSISAMPLE */
mbed_official	85:e1a8e879a6a9	5428	/* Description: RSSI sample. */
mbed_official	85:e1a8e879a6a9	5429
mbed_official	85:e1a8e879a6a9	5430	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
mbed_official	85:e1a8e879a6a9	5431	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
mbed_official	85:e1a8e879a6a9	5432	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
mbed_official	85:e1a8e879a6a9	5433
mbed_official	85:e1a8e879a6a9	5434	/* Register: RADIO_STATE */
mbed_official	85:e1a8e879a6a9	5435	/* Description: Current radio state. */
mbed_official	85:e1a8e879a6a9	5436
mbed_official	85:e1a8e879a6a9	5437	/* Bits 3..0 : Current radio state. */
mbed_official	85:e1a8e879a6a9	5438	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
mbed_official	85:e1a8e879a6a9	5439	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
mbed_official	85:e1a8e879a6a9	5440	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
mbed_official	85:e1a8e879a6a9	5441	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
mbed_official	85:e1a8e879a6a9	5442	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
mbed_official	85:e1a8e879a6a9	5443	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
mbed_official	85:e1a8e879a6a9	5444	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
mbed_official	85:e1a8e879a6a9	5445	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
mbed_official	85:e1a8e879a6a9	5446	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
mbed_official	85:e1a8e879a6a9	5447	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
mbed_official	85:e1a8e879a6a9	5448	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
mbed_official	85:e1a8e879a6a9	5449
mbed_official	85:e1a8e879a6a9	5450	/* Register: RADIO_DATAWHITEIV */
mbed_official	85:e1a8e879a6a9	5451	/* Description: Data whitening initial value. */
mbed_official	85:e1a8e879a6a9	5452
mbed_official	501:36015dec7d16	5453	/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
mbed_official	85:e1a8e879a6a9	5454	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
mbed_official	501:36015dec7d16	5455	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
mbed_official	85:e1a8e879a6a9	5456
mbed_official	85:e1a8e879a6a9	5457	/* Register: RADIO_DAP */
mbed_official	85:e1a8e879a6a9	5458	/* Description: Device address prefix. */
mbed_official	85:e1a8e879a6a9	5459
mbed_official	85:e1a8e879a6a9	5460	/* Bits 15..0 : Device address prefix. */
mbed_official	85:e1a8e879a6a9	5461	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
mbed_official	85:e1a8e879a6a9	5462	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
mbed_official	85:e1a8e879a6a9	5463
mbed_official	85:e1a8e879a6a9	5464	/* Register: RADIO_DACNF */
mbed_official	85:e1a8e879a6a9	5465	/* Description: Device address match configuration. */
mbed_official	85:e1a8e879a6a9	5466
mbed_official	85:e1a8e879a6a9	5467	/* Bit 15 : TxAdd for device address 7. */
mbed_official	85:e1a8e879a6a9	5468	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
mbed_official	85:e1a8e879a6a9	5469	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
mbed_official	85:e1a8e879a6a9	5470
mbed_official	85:e1a8e879a6a9	5471	/* Bit 14 : TxAdd for device address 6. */
mbed_official	85:e1a8e879a6a9	5472	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
mbed_official	85:e1a8e879a6a9	5473	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
mbed_official	85:e1a8e879a6a9	5474
mbed_official	85:e1a8e879a6a9	5475	/* Bit 13 : TxAdd for device address 5. */
mbed_official	85:e1a8e879a6a9	5476	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
mbed_official	85:e1a8e879a6a9	5477	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
mbed_official	85:e1a8e879a6a9	5478
mbed_official	85:e1a8e879a6a9	5479	/* Bit 12 : TxAdd for device address 4. */
mbed_official	85:e1a8e879a6a9	5480	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
mbed_official	85:e1a8e879a6a9	5481	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
mbed_official	85:e1a8e879a6a9	5482
mbed_official	85:e1a8e879a6a9	5483	/* Bit 11 : TxAdd for device address 3. */
mbed_official	85:e1a8e879a6a9	5484	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
mbed_official	85:e1a8e879a6a9	5485	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
mbed_official	85:e1a8e879a6a9	5486
mbed_official	85:e1a8e879a6a9	5487	/* Bit 10 : TxAdd for device address 2. */
mbed_official	85:e1a8e879a6a9	5488	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
mbed_official	85:e1a8e879a6a9	5489	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
mbed_official	85:e1a8e879a6a9	5490
mbed_official	85:e1a8e879a6a9	5491	/* Bit 9 : TxAdd for device address 1. */
mbed_official	85:e1a8e879a6a9	5492	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
mbed_official	85:e1a8e879a6a9	5493	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
mbed_official	85:e1a8e879a6a9	5494
mbed_official	85:e1a8e879a6a9	5495	/* Bit 8 : TxAdd for device address 0. */
mbed_official	85:e1a8e879a6a9	5496	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
mbed_official	85:e1a8e879a6a9	5497	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
mbed_official	85:e1a8e879a6a9	5498
mbed_official	85:e1a8e879a6a9	5499	/* Bit 7 : Enable or disable device address matching using device address 7. */
mbed_official	85:e1a8e879a6a9	5500	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
mbed_official	85:e1a8e879a6a9	5501	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
mbed_official	85:e1a8e879a6a9	5502	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	5503	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
mbed_official	85:e1a8e879a6a9	5504
mbed_official	85:e1a8e879a6a9	5505	/* Bit 6 : Enable or disable device address matching using device address 6. */
mbed_official	85:e1a8e879a6a9	5506	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
mbed_official	85:e1a8e879a6a9	5507	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
mbed_official	85:e1a8e879a6a9	5508	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	5509	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
mbed_official	85:e1a8e879a6a9	5510
mbed_official	85:e1a8e879a6a9	5511	/* Bit 5 : Enable or disable device address matching using device address 5. */
mbed_official	85:e1a8e879a6a9	5512	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
mbed_official	85:e1a8e879a6a9	5513	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
mbed_official	85:e1a8e879a6a9	5514	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	5515	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
mbed_official	85:e1a8e879a6a9	5516
mbed_official	85:e1a8e879a6a9	5517	/* Bit 4 : Enable or disable device address matching using device address 4. */
mbed_official	85:e1a8e879a6a9	5518	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
mbed_official	85:e1a8e879a6a9	5519	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
mbed_official	85:e1a8e879a6a9	5520	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	5521	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
mbed_official	85:e1a8e879a6a9	5522
mbed_official	85:e1a8e879a6a9	5523	/* Bit 3 : Enable or disable device address matching using device address 3. */
mbed_official	85:e1a8e879a6a9	5524	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
mbed_official	85:e1a8e879a6a9	5525	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
mbed_official	85:e1a8e879a6a9	5526	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	5527	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
mbed_official	85:e1a8e879a6a9	5528
mbed_official	85:e1a8e879a6a9	5529	/* Bit 2 : Enable or disable device address matching using device address 2. */
mbed_official	85:e1a8e879a6a9	5530	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
mbed_official	85:e1a8e879a6a9	5531	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
mbed_official	85:e1a8e879a6a9	5532	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	5533	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
mbed_official	85:e1a8e879a6a9	5534
mbed_official	85:e1a8e879a6a9	5535	/* Bit 1 : Enable or disable device address matching using device address 1. */
mbed_official	85:e1a8e879a6a9	5536	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
mbed_official	85:e1a8e879a6a9	5537	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
mbed_official	85:e1a8e879a6a9	5538	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	5539	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
mbed_official	85:e1a8e879a6a9	5540
mbed_official	85:e1a8e879a6a9	5541	/* Bit 0 : Enable or disable device address matching using device address 0. */
mbed_official	85:e1a8e879a6a9	5542	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
mbed_official	85:e1a8e879a6a9	5543	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
mbed_official	85:e1a8e879a6a9	5544	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	5545	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
mbed_official	85:e1a8e879a6a9	5546
mbed_official	85:e1a8e879a6a9	5547	/* Register: RADIO_OVERRIDE0 */
mbed_official	85:e1a8e879a6a9	5548	/* Description: Trim value override register 0. */
mbed_official	85:e1a8e879a6a9	5549
mbed_official	501:36015dec7d16	5550	/* Bits 31..0 : Trim value override 0. */
mbed_official	85:e1a8e879a6a9	5551	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
mbed_official	85:e1a8e879a6a9	5552	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
mbed_official	85:e1a8e879a6a9	5553
mbed_official	85:e1a8e879a6a9	5554	/* Register: RADIO_OVERRIDE1 */
mbed_official	85:e1a8e879a6a9	5555	/* Description: Trim value override register 1. */
mbed_official	85:e1a8e879a6a9	5556
mbed_official	501:36015dec7d16	5557	/* Bits 31..0 : Trim value override 1. */
mbed_official	85:e1a8e879a6a9	5558	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
mbed_official	85:e1a8e879a6a9	5559	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
mbed_official	85:e1a8e879a6a9	5560
mbed_official	85:e1a8e879a6a9	5561	/* Register: RADIO_OVERRIDE2 */
mbed_official	85:e1a8e879a6a9	5562	/* Description: Trim value override register 2. */
mbed_official	85:e1a8e879a6a9	5563
mbed_official	501:36015dec7d16	5564	/* Bits 31..0 : Trim value override 2. */
mbed_official	85:e1a8e879a6a9	5565	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
mbed_official	85:e1a8e879a6a9	5566	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
mbed_official	85:e1a8e879a6a9	5567
mbed_official	85:e1a8e879a6a9	5568	/* Register: RADIO_OVERRIDE3 */
mbed_official	85:e1a8e879a6a9	5569	/* Description: Trim value override register 3. */
mbed_official	85:e1a8e879a6a9	5570
mbed_official	501:36015dec7d16	5571	/* Bits 31..0 : Trim value override 3. */
mbed_official	85:e1a8e879a6a9	5572	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
mbed_official	85:e1a8e879a6a9	5573	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
mbed_official	85:e1a8e879a6a9	5574
mbed_official	85:e1a8e879a6a9	5575	/* Register: RADIO_OVERRIDE4 */
mbed_official	85:e1a8e879a6a9	5576	/* Description: Trim value override register 4. */
mbed_official	85:e1a8e879a6a9	5577
mbed_official	85:e1a8e879a6a9	5578	/* Bit 31 : Enable or disable override of default trim values. */
mbed_official	85:e1a8e879a6a9	5579	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
mbed_official	85:e1a8e879a6a9	5580	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
mbed_official	85:e1a8e879a6a9	5581	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
mbed_official	85:e1a8e879a6a9	5582	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
mbed_official	85:e1a8e879a6a9	5583
mbed_official	501:36015dec7d16	5584	/* Bits 27..0 : Trim value override 4. */
mbed_official	85:e1a8e879a6a9	5585	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
mbed_official	85:e1a8e879a6a9	5586	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
mbed_official	85:e1a8e879a6a9	5587
mbed_official	85:e1a8e879a6a9	5588	/* Register: RADIO_POWER */
mbed_official	85:e1a8e879a6a9	5589	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	5590
mbed_official	85:e1a8e879a6a9	5591	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	5592	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	5593	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	5594	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	5595	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	5596
mbed_official	85:e1a8e879a6a9	5597
mbed_official	85:e1a8e879a6a9	5598	/* Peripheral: RNG */
mbed_official	85:e1a8e879a6a9	5599	/* Description: Random Number Generator. */
mbed_official	85:e1a8e879a6a9	5600
mbed_official	85:e1a8e879a6a9	5601	/* Register: RNG_SHORTS */
mbed_official	501:36015dec7d16	5602	/* Description: Shortcuts for the RNG. */
mbed_official	501:36015dec7d16	5603
mbed_official	501:36015dec7d16	5604	/* Bit 0 : Shortcut between VALRDY event and STOP task. */
mbed_official	85:e1a8e879a6a9	5605	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
mbed_official	85:e1a8e879a6a9	5606	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
mbed_official	85:e1a8e879a6a9	5607	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	5608	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	5609
mbed_official	85:e1a8e879a6a9	5610	/* Register: RNG_INTENSET */
mbed_official	85:e1a8e879a6a9	5611	/* Description: Interrupt enable set register */
mbed_official	85:e1a8e879a6a9	5612
mbed_official	85:e1a8e879a6a9	5613	/* Bit 0 : Enable interrupt on VALRDY event. */
mbed_official	85:e1a8e879a6a9	5614	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
mbed_official	85:e1a8e879a6a9	5615	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
mbed_official	85:e1a8e879a6a9	5616	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5617	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5618	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5619
mbed_official	85:e1a8e879a6a9	5620	/* Register: RNG_INTENCLR */
mbed_official	85:e1a8e879a6a9	5621	/* Description: Interrupt enable clear register */
mbed_official	85:e1a8e879a6a9	5622
mbed_official	85:e1a8e879a6a9	5623	/* Bit 0 : Disable interrupt on VALRDY event. */
mbed_official	85:e1a8e879a6a9	5624	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
mbed_official	85:e1a8e879a6a9	5625	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
mbed_official	85:e1a8e879a6a9	5626	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5627	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5628	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5629
mbed_official	85:e1a8e879a6a9	5630	/* Register: RNG_CONFIG */
mbed_official	85:e1a8e879a6a9	5631	/* Description: Configuration register. */
mbed_official	85:e1a8e879a6a9	5632
mbed_official	85:e1a8e879a6a9	5633	/* Bit 0 : Digital error correction enable. */
mbed_official	85:e1a8e879a6a9	5634	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
mbed_official	85:e1a8e879a6a9	5635	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
mbed_official	85:e1a8e879a6a9	5636	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
mbed_official	85:e1a8e879a6a9	5637	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
mbed_official	85:e1a8e879a6a9	5638
mbed_official	85:e1a8e879a6a9	5639	/* Register: RNG_VALUE */
mbed_official	85:e1a8e879a6a9	5640	/* Description: RNG random number. */
mbed_official	85:e1a8e879a6a9	5641
mbed_official	85:e1a8e879a6a9	5642	/* Bits 7..0 : Generated random number. */
mbed_official	85:e1a8e879a6a9	5643	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
mbed_official	85:e1a8e879a6a9	5644	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
mbed_official	85:e1a8e879a6a9	5645
mbed_official	85:e1a8e879a6a9	5646	/* Register: RNG_POWER */
mbed_official	85:e1a8e879a6a9	5647	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	5648
mbed_official	85:e1a8e879a6a9	5649	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	5650	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	5651	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	5652	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	5653	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	5654
mbed_official	85:e1a8e879a6a9	5655
mbed_official	85:e1a8e879a6a9	5656	/* Peripheral: RTC */
mbed_official	85:e1a8e879a6a9	5657	/* Description: Real time counter 0. */
mbed_official	85:e1a8e879a6a9	5658
mbed_official	85:e1a8e879a6a9	5659	/* Register: RTC_INTENSET */
mbed_official	85:e1a8e879a6a9	5660	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	5661
mbed_official	85:e1a8e879a6a9	5662	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
mbed_official	85:e1a8e879a6a9	5663	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	5664	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	5665	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5666	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5667	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5668
mbed_official	85:e1a8e879a6a9	5669	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
mbed_official	85:e1a8e879a6a9	5670	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	5671	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	5672	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5673	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5674	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5675
mbed_official	85:e1a8e879a6a9	5676	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
mbed_official	85:e1a8e879a6a9	5677	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	5678	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	5679	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5680	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5681	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5682
mbed_official	85:e1a8e879a6a9	5683	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
mbed_official	85:e1a8e879a6a9	5684	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	5685	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	5686	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5687	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5688	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5689
mbed_official	85:e1a8e879a6a9	5690	/* Bit 1 : Enable interrupt on OVRFLW event. */
mbed_official	85:e1a8e879a6a9	5691	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
mbed_official	85:e1a8e879a6a9	5692	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
mbed_official	85:e1a8e879a6a9	5693	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5694	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5695	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5696
mbed_official	85:e1a8e879a6a9	5697	/* Bit 0 : Enable interrupt on TICK event. */
mbed_official	85:e1a8e879a6a9	5698	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
mbed_official	85:e1a8e879a6a9	5699	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
mbed_official	85:e1a8e879a6a9	5700	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5701	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5702	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5703
mbed_official	85:e1a8e879a6a9	5704	/* Register: RTC_INTENCLR */
mbed_official	85:e1a8e879a6a9	5705	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	5706
mbed_official	85:e1a8e879a6a9	5707	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
mbed_official	85:e1a8e879a6a9	5708	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	5709	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	5710	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5711	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5712	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5713
mbed_official	85:e1a8e879a6a9	5714	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
mbed_official	85:e1a8e879a6a9	5715	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	5716	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	5717	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5718	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5719	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5720
mbed_official	85:e1a8e879a6a9	5721	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
mbed_official	85:e1a8e879a6a9	5722	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	5723	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	5724	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5725	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5726	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5727
mbed_official	85:e1a8e879a6a9	5728	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
mbed_official	85:e1a8e879a6a9	5729	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	5730	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	5731	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5732	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5733	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5734
mbed_official	85:e1a8e879a6a9	5735	/* Bit 1 : Disable interrupt on OVRFLW event. */
mbed_official	85:e1a8e879a6a9	5736	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
mbed_official	85:e1a8e879a6a9	5737	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
mbed_official	85:e1a8e879a6a9	5738	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5739	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5740	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5741
mbed_official	85:e1a8e879a6a9	5742	/* Bit 0 : Disable interrupt on TICK event. */
mbed_official	85:e1a8e879a6a9	5743	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
mbed_official	85:e1a8e879a6a9	5744	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
mbed_official	85:e1a8e879a6a9	5745	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5746	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5747	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5748
mbed_official	85:e1a8e879a6a9	5749	/* Register: RTC_EVTEN */
mbed_official	85:e1a8e879a6a9	5750	/* Description: Configures event enable routing to PPI for each RTC event. */
mbed_official	85:e1a8e879a6a9	5751
mbed_official	85:e1a8e879a6a9	5752	/* Bit 19 : COMPARE[3] event enable. */
mbed_official	85:e1a8e879a6a9	5753	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	5754	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	5755	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5756	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5757
mbed_official	85:e1a8e879a6a9	5758	/* Bit 18 : COMPARE[2] event enable. */
mbed_official	85:e1a8e879a6a9	5759	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	5760	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	5761	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5762	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5763
mbed_official	85:e1a8e879a6a9	5764	/* Bit 17 : COMPARE[1] event enable. */
mbed_official	85:e1a8e879a6a9	5765	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	5766	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	5767	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5768	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5769
mbed_official	85:e1a8e879a6a9	5770	/* Bit 16 : COMPARE[0] event enable. */
mbed_official	85:e1a8e879a6a9	5771	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	5772	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	5773	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5774	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5775
mbed_official	85:e1a8e879a6a9	5776	/* Bit 1 : OVRFLW event enable. */
mbed_official	85:e1a8e879a6a9	5777	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
mbed_official	85:e1a8e879a6a9	5778	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
mbed_official	85:e1a8e879a6a9	5779	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5780	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5781
mbed_official	85:e1a8e879a6a9	5782	/* Bit 0 : TICK event enable. */
mbed_official	85:e1a8e879a6a9	5783	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
mbed_official	85:e1a8e879a6a9	5784	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
mbed_official	85:e1a8e879a6a9	5785	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5786	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5787
mbed_official	85:e1a8e879a6a9	5788	/* Register: RTC_EVTENSET */
mbed_official	85:e1a8e879a6a9	5789	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
mbed_official	85:e1a8e879a6a9	5790
mbed_official	85:e1a8e879a6a9	5791	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
mbed_official	85:e1a8e879a6a9	5792	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	5793	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	5794	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5795	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5796	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
mbed_official	85:e1a8e879a6a9	5797
mbed_official	85:e1a8e879a6a9	5798	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
mbed_official	85:e1a8e879a6a9	5799	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	5800	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	5801	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5802	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5803	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
mbed_official	85:e1a8e879a6a9	5804
mbed_official	85:e1a8e879a6a9	5805	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
mbed_official	85:e1a8e879a6a9	5806	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	5807	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	5808	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5809	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5810	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
mbed_official	85:e1a8e879a6a9	5811
mbed_official	85:e1a8e879a6a9	5812	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
mbed_official	85:e1a8e879a6a9	5813	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	5814	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	5815	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5816	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5817	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
mbed_official	85:e1a8e879a6a9	5818
mbed_official	85:e1a8e879a6a9	5819	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
mbed_official	85:e1a8e879a6a9	5820	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
mbed_official	85:e1a8e879a6a9	5821	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
mbed_official	85:e1a8e879a6a9	5822	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5823	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5824	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
mbed_official	85:e1a8e879a6a9	5825
mbed_official	85:e1a8e879a6a9	5826	/* Bit 0 : Enable routing to PPI of TICK event. */
mbed_official	85:e1a8e879a6a9	5827	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
mbed_official	85:e1a8e879a6a9	5828	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
mbed_official	85:e1a8e879a6a9	5829	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5830	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5831	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
mbed_official	85:e1a8e879a6a9	5832
mbed_official	85:e1a8e879a6a9	5833	/* Register: RTC_EVTENCLR */
mbed_official	85:e1a8e879a6a9	5834	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
mbed_official	85:e1a8e879a6a9	5835
mbed_official	85:e1a8e879a6a9	5836	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
mbed_official	85:e1a8e879a6a9	5837	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	5838	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	5839	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5840	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5841	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
mbed_official	85:e1a8e879a6a9	5842
mbed_official	85:e1a8e879a6a9	5843	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
mbed_official	85:e1a8e879a6a9	5844	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	5845	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	5846	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5847	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5848	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
mbed_official	85:e1a8e879a6a9	5849
mbed_official	85:e1a8e879a6a9	5850	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
mbed_official	85:e1a8e879a6a9	5851	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	5852	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	5853	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5854	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5855	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
mbed_official	85:e1a8e879a6a9	5856
mbed_official	85:e1a8e879a6a9	5857	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
mbed_official	85:e1a8e879a6a9	5858	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	5859	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	5860	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5861	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5862	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
mbed_official	85:e1a8e879a6a9	5863
mbed_official	85:e1a8e879a6a9	5864	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
mbed_official	85:e1a8e879a6a9	5865	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
mbed_official	85:e1a8e879a6a9	5866	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
mbed_official	85:e1a8e879a6a9	5867	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5868	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5869	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
mbed_official	85:e1a8e879a6a9	5870
mbed_official	85:e1a8e879a6a9	5871	/* Bit 0 : Disable routing to PPI of TICK event. */
mbed_official	85:e1a8e879a6a9	5872	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
mbed_official	85:e1a8e879a6a9	5873	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
mbed_official	85:e1a8e879a6a9	5874	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
mbed_official	85:e1a8e879a6a9	5875	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
mbed_official	85:e1a8e879a6a9	5876	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
mbed_official	85:e1a8e879a6a9	5877
mbed_official	85:e1a8e879a6a9	5878	/* Register: RTC_COUNTER */
mbed_official	85:e1a8e879a6a9	5879	/* Description: Current COUNTER value. */
mbed_official	85:e1a8e879a6a9	5880
mbed_official	85:e1a8e879a6a9	5881	/* Bits 23..0 : Counter value. */
mbed_official	85:e1a8e879a6a9	5882	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
mbed_official	85:e1a8e879a6a9	5883	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
mbed_official	85:e1a8e879a6a9	5884
mbed_official	85:e1a8e879a6a9	5885	/* Register: RTC_PRESCALER */
mbed_official	85:e1a8e879a6a9	5886	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
mbed_official	85:e1a8e879a6a9	5887
mbed_official	85:e1a8e879a6a9	5888	/* Bits 11..0 : RTC PRESCALER value. */
mbed_official	85:e1a8e879a6a9	5889	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
mbed_official	85:e1a8e879a6a9	5890	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
mbed_official	85:e1a8e879a6a9	5891
mbed_official	85:e1a8e879a6a9	5892	/* Register: RTC_CC */
mbed_official	85:e1a8e879a6a9	5893	/* Description: Capture/compare registers. */
mbed_official	85:e1a8e879a6a9	5894
mbed_official	85:e1a8e879a6a9	5895	/* Bits 23..0 : Compare value. */
mbed_official	85:e1a8e879a6a9	5896	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
mbed_official	85:e1a8e879a6a9	5897	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
mbed_official	85:e1a8e879a6a9	5898
mbed_official	85:e1a8e879a6a9	5899	/* Register: RTC_POWER */
mbed_official	85:e1a8e879a6a9	5900	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	5901
mbed_official	85:e1a8e879a6a9	5902	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	5903	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	5904	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	5905	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	5906	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	5907
mbed_official	85:e1a8e879a6a9	5908
mbed_official	85:e1a8e879a6a9	5909	/* Peripheral: SPI */
mbed_official	85:e1a8e879a6a9	5910	/* Description: SPI master 0. */
mbed_official	85:e1a8e879a6a9	5911
mbed_official	85:e1a8e879a6a9	5912	/* Register: SPI_INTENSET */
mbed_official	85:e1a8e879a6a9	5913	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	5914
mbed_official	85:e1a8e879a6a9	5915	/* Bit 2 : Enable interrupt on READY event. */
mbed_official	85:e1a8e879a6a9	5916	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
mbed_official	85:e1a8e879a6a9	5917	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
mbed_official	85:e1a8e879a6a9	5918	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5919	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5920	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5921
mbed_official	85:e1a8e879a6a9	5922	/* Register: SPI_INTENCLR */
mbed_official	85:e1a8e879a6a9	5923	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	5924
mbed_official	85:e1a8e879a6a9	5925	/* Bit 2 : Disable interrupt on READY event. */
mbed_official	85:e1a8e879a6a9	5926	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
mbed_official	85:e1a8e879a6a9	5927	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
mbed_official	85:e1a8e879a6a9	5928	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	5929	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	5930	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	5931
mbed_official	85:e1a8e879a6a9	5932	/* Register: SPI_ENABLE */
mbed_official	85:e1a8e879a6a9	5933	/* Description: Enable SPI. */
mbed_official	85:e1a8e879a6a9	5934
mbed_official	85:e1a8e879a6a9	5935	/* Bits 2..0 : Enable or disable SPI. */
mbed_official	85:e1a8e879a6a9	5936	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
mbed_official	85:e1a8e879a6a9	5937	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
mbed_official	85:e1a8e879a6a9	5938	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
mbed_official	85:e1a8e879a6a9	5939	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
mbed_official	85:e1a8e879a6a9	5940
mbed_official	85:e1a8e879a6a9	5941	/* Register: SPI_RXD */
mbed_official	85:e1a8e879a6a9	5942	/* Description: RX data. */
mbed_official	85:e1a8e879a6a9	5943
mbed_official	85:e1a8e879a6a9	5944	/* Bits 7..0 : RX data from last transfer. */
mbed_official	85:e1a8e879a6a9	5945	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
mbed_official	85:e1a8e879a6a9	5946	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
mbed_official	85:e1a8e879a6a9	5947
mbed_official	85:e1a8e879a6a9	5948	/* Register: SPI_TXD */
mbed_official	85:e1a8e879a6a9	5949	/* Description: TX data. */
mbed_official	85:e1a8e879a6a9	5950
mbed_official	85:e1a8e879a6a9	5951	/* Bits 7..0 : TX data for next transfer. */
mbed_official	85:e1a8e879a6a9	5952	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
mbed_official	85:e1a8e879a6a9	5953	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
mbed_official	85:e1a8e879a6a9	5954
mbed_official	85:e1a8e879a6a9	5955	/* Register: SPI_FREQUENCY */
mbed_official	85:e1a8e879a6a9	5956	/* Description: SPI frequency */
mbed_official	85:e1a8e879a6a9	5957
mbed_official	85:e1a8e879a6a9	5958	/* Bits 31..0 : SPI data rate. */
mbed_official	85:e1a8e879a6a9	5959	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
mbed_official	85:e1a8e879a6a9	5960	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
mbed_official	85:e1a8e879a6a9	5961	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
mbed_official	85:e1a8e879a6a9	5962	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
mbed_official	85:e1a8e879a6a9	5963	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
mbed_official	85:e1a8e879a6a9	5964	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
mbed_official	85:e1a8e879a6a9	5965	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
mbed_official	85:e1a8e879a6a9	5966	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
mbed_official	85:e1a8e879a6a9	5967	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
mbed_official	85:e1a8e879a6a9	5968
mbed_official	85:e1a8e879a6a9	5969	/* Register: SPI_CONFIG */
mbed_official	85:e1a8e879a6a9	5970	/* Description: Configuration register. */
mbed_official	85:e1a8e879a6a9	5971
mbed_official	85:e1a8e879a6a9	5972	/* Bit 2 : Serial clock (SCK) polarity. */
mbed_official	85:e1a8e879a6a9	5973	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
mbed_official	85:e1a8e879a6a9	5974	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
mbed_official	85:e1a8e879a6a9	5975	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
mbed_official	85:e1a8e879a6a9	5976	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
mbed_official	85:e1a8e879a6a9	5977
mbed_official	85:e1a8e879a6a9	5978	/* Bit 1 : Serial clock (SCK) phase. */
mbed_official	85:e1a8e879a6a9	5979	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
mbed_official	85:e1a8e879a6a9	5980	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
mbed_official	85:e1a8e879a6a9	5981	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
mbed_official	85:e1a8e879a6a9	5982	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
mbed_official	85:e1a8e879a6a9	5983
mbed_official	85:e1a8e879a6a9	5984	/* Bit 0 : Bit order. */
mbed_official	85:e1a8e879a6a9	5985	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
mbed_official	85:e1a8e879a6a9	5986	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
mbed_official	85:e1a8e879a6a9	5987	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
mbed_official	85:e1a8e879a6a9	5988	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
mbed_official	85:e1a8e879a6a9	5989
mbed_official	85:e1a8e879a6a9	5990	/* Register: SPI_POWER */
mbed_official	85:e1a8e879a6a9	5991	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	5992
mbed_official	85:e1a8e879a6a9	5993	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	5994	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	5995	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	5996	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	5997	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	5998
mbed_official	85:e1a8e879a6a9	5999
mbed_official	501:36015dec7d16	6000	/* Peripheral: SPIM */
mbed_official	501:36015dec7d16	6001	/* Description: SPI master with easyDMA 1. */
mbed_official	501:36015dec7d16	6002
mbed_official	501:36015dec7d16	6003	/* Register: SPIM_SHORTS */
mbed_official	501:36015dec7d16	6004	/* Description: Shortcuts for SPIM. */
mbed_official	501:36015dec7d16	6005
mbed_official	501:36015dec7d16	6006	/* Bit 17 : Shortcut between END event and START task. */
mbed_official	501:36015dec7d16	6007	#define SPIM_SHORTS_END_START_Pos (17UL) /!< Position of END_START field. /
mbed_official	501:36015dec7d16	6008	#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
mbed_official	501:36015dec7d16	6009	#define SPIM_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	501:36015dec7d16	6010	#define SPIM_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	501:36015dec7d16	6011
mbed_official	501:36015dec7d16	6012	/* Register: SPIM_INTENSET */
mbed_official	501:36015dec7d16	6013	/* Description: Interrupt enable set register. */
mbed_official	501:36015dec7d16	6014
mbed_official	501:36015dec7d16	6015	/* Bit 19 : Enable interrupt on STARTED event. */
mbed_official	501:36015dec7d16	6016	#define SPIM_INTENSET_STARTED_Pos (19UL) /!< Position of STARTED field. /
mbed_official	501:36015dec7d16	6017	#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /!< Bit mask of STARTED field. /
mbed_official	501:36015dec7d16	6018	#define SPIM_INTENSET_STARTED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	501:36015dec7d16	6019	#define SPIM_INTENSET_STARTED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	501:36015dec7d16	6020	#define SPIM_INTENSET_STARTED_Set (1UL) /!< Enable interrupt on write. /
mbed_official	501:36015dec7d16	6021
mbed_official	501:36015dec7d16	6022	/* Bit 8 : Enable interrupt on ENDTX event. */
mbed_official	501:36015dec7d16	6023	#define SPIM_INTENSET_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
mbed_official	501:36015dec7d16	6024	#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /!< Bit mask of ENDTX field. /
mbed_official	501:36015dec7d16	6025	#define SPIM_INTENSET_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	501:36015dec7d16	6026	#define SPIM_INTENSET_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	501:36015dec7d16	6027	#define SPIM_INTENSET_ENDTX_Set (1UL) /!< Enable interrupt on write. /
mbed_official	501:36015dec7d16	6028
mbed_official	501:36015dec7d16	6029	/* Bit 6 : Enable interrupt on END event. */
mbed_official	501:36015dec7d16	6030	#define SPIM_INTENSET_END_Pos (6UL) /!< Position of END field. /
mbed_official	501:36015dec7d16	6031	#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /!< Bit mask of END field. /
mbed_official	501:36015dec7d16	6032	#define SPIM_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	501:36015dec7d16	6033	#define SPIM_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	501:36015dec7d16	6034	#define SPIM_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
mbed_official	501:36015dec7d16	6035
mbed_official	501:36015dec7d16	6036	/* Bit 4 : Enable interrupt on ENDRX event. */
mbed_official	501:36015dec7d16	6037	#define SPIM_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
mbed_official	501:36015dec7d16	6038	#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
mbed_official	501:36015dec7d16	6039	#define SPIM_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	501:36015dec7d16	6040	#define SPIM_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	501:36015dec7d16	6041	#define SPIM_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
mbed_official	501:36015dec7d16	6042
mbed_official	501:36015dec7d16	6043	/* Bit 1 : Enable interrupt on STOPPED event. */
mbed_official	501:36015dec7d16	6044	#define SPIM_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
mbed_official	501:36015dec7d16	6045	#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
mbed_official	501:36015dec7d16	6046	#define SPIM_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	501:36015dec7d16	6047	#define SPIM_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	501:36015dec7d16	6048	#define SPIM_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
mbed_official	501:36015dec7d16	6049
mbed_official	501:36015dec7d16	6050	/* Register: SPIM_INTENCLR */
mbed_official	501:36015dec7d16	6051	/* Description: Interrupt enable clear register. */
mbed_official	501:36015dec7d16	6052
mbed_official	501:36015dec7d16	6053	/* Bit 19 : Disable interrupt on STARTED event. */
mbed_official	501:36015dec7d16	6054	#define SPIM_INTENCLR_STARTED_Pos (19UL) /!< Position of STARTED field. /
mbed_official	501:36015dec7d16	6055	#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /!< Bit mask of STARTED field. /
mbed_official	501:36015dec7d16	6056	#define SPIM_INTENCLR_STARTED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	501:36015dec7d16	6057	#define SPIM_INTENCLR_STARTED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	501:36015dec7d16	6058	#define SPIM_INTENCLR_STARTED_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	501:36015dec7d16	6059
mbed_official	501:36015dec7d16	6060	/* Bit 8 : Disable interrupt on ENDTX event. */
mbed_official	501:36015dec7d16	6061	#define SPIM_INTENCLR_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
mbed_official	501:36015dec7d16	6062	#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /!< Bit mask of ENDTX field. /
mbed_official	501:36015dec7d16	6063	#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	501:36015dec7d16	6064	#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	501:36015dec7d16	6065	#define SPIM_INTENCLR_ENDTX_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	501:36015dec7d16	6066
mbed_official	501:36015dec7d16	6067	/* Bit 6 : Disable interrupt on END event. */
mbed_official	501:36015dec7d16	6068	#define SPIM_INTENCLR_END_Pos (6UL) /!< Position of END field. /
mbed_official	501:36015dec7d16	6069	#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /!< Bit mask of END field. /
mbed_official	501:36015dec7d16	6070	#define SPIM_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	501:36015dec7d16	6071	#define SPIM_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	501:36015dec7d16	6072	#define SPIM_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	501:36015dec7d16	6073
mbed_official	501:36015dec7d16	6074	/* Bit 4 : Disable interrupt on ENDRX event. */
mbed_official	501:36015dec7d16	6075	#define SPIM_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
mbed_official	501:36015dec7d16	6076	#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
mbed_official	501:36015dec7d16	6077	#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	501:36015dec7d16	6078	#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	501:36015dec7d16	6079	#define SPIM_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	501:36015dec7d16	6080
mbed_official	501:36015dec7d16	6081	/* Bit 1 : Disable interrupt on STOPPED event. */
mbed_official	501:36015dec7d16	6082	#define SPIM_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
mbed_official	501:36015dec7d16	6083	#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
mbed_official	501:36015dec7d16	6084	#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	501:36015dec7d16	6085	#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	501:36015dec7d16	6086	#define SPIM_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	501:36015dec7d16	6087
mbed_official	501:36015dec7d16	6088	/* Register: SPIM_ENABLE */
mbed_official	501:36015dec7d16	6089	/* Description: Enable SPIM. */
mbed_official	501:36015dec7d16	6090
mbed_official	501:36015dec7d16	6091	/* Bits 3..0 : Enable or disable SPIM. */
mbed_official	501:36015dec7d16	6092	#define SPIM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
mbed_official	501:36015dec7d16	6093	#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
mbed_official	501:36015dec7d16	6094	#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIM. /
mbed_official	501:36015dec7d16	6095	#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /!< Enable SPIM. /
mbed_official	501:36015dec7d16	6096
mbed_official	501:36015dec7d16	6097	/* Register: SPIM_RXDDATA */
mbed_official	501:36015dec7d16	6098	/* Description: RXD register. */
mbed_official	501:36015dec7d16	6099
mbed_official	501:36015dec7d16	6100	/* Bits 7..0 : RX data received. Double buffered. */
mbed_official	501:36015dec7d16	6101	#define SPIM_RXDDATA_RXD_Pos (0UL) /!< Position of RXD field. /
mbed_official	501:36015dec7d16	6102	#define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /!< Bit mask of RXD field. /
mbed_official	501:36015dec7d16	6103
mbed_official	501:36015dec7d16	6104	/* Register: SPIM_TXDDATA */
mbed_official	501:36015dec7d16	6105	/* Description: TXD register. */
mbed_official	501:36015dec7d16	6106
mbed_official	501:36015dec7d16	6107	/* Bits 7..0 : TX data to send. Double buffered. */
mbed_official	501:36015dec7d16	6108	#define SPIM_TXDDATA_TXD_Pos (0UL) /!< Position of TXD field. /
mbed_official	501:36015dec7d16	6109	#define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /!< Bit mask of TXD field. /
mbed_official	501:36015dec7d16	6110
mbed_official	501:36015dec7d16	6111	/* Register: SPIM_FREQUENCY */
mbed_official	501:36015dec7d16	6112	/* Description: SPI frequency. */
mbed_official	501:36015dec7d16	6113
mbed_official	501:36015dec7d16	6114	/* Bits 31..0 : SPI master data rate. */
mbed_official	501:36015dec7d16	6115	#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
mbed_official	501:36015dec7d16	6116	#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
mbed_official	501:36015dec7d16	6117	#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125 kbps. /
mbed_official	501:36015dec7d16	6118	#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
mbed_official	501:36015dec7d16	6119	#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500 kbps. /
mbed_official	501:36015dec7d16	6120	#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1 Mbps. /
mbed_official	501:36015dec7d16	6121	#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2 Mbps. /
mbed_official	501:36015dec7d16	6122	#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4 Mbps. /
mbed_official	501:36015dec7d16	6123	#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8 Mbps. /
mbed_official	501:36015dec7d16	6124
mbed_official	501:36015dec7d16	6125	/* Register: SPIM_CONFIG */
mbed_official	501:36015dec7d16	6126	/* Description: Configuration register. */
mbed_official	501:36015dec7d16	6127
mbed_official	501:36015dec7d16	6128	/* Bit 2 : Serial clock (SCK) polarity. */
mbed_official	501:36015dec7d16	6129	#define SPIM_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
mbed_official	501:36015dec7d16	6130	#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
mbed_official	501:36015dec7d16	6131	#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
mbed_official	501:36015dec7d16	6132	#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
mbed_official	501:36015dec7d16	6133
mbed_official	501:36015dec7d16	6134	/* Bit 1 : Serial clock (SCK) phase. */
mbed_official	501:36015dec7d16	6135	#define SPIM_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
mbed_official	501:36015dec7d16	6136	#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
mbed_official	501:36015dec7d16	6137	#define SPIM_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
mbed_official	501:36015dec7d16	6138	#define SPIM_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
mbed_official	501:36015dec7d16	6139
mbed_official	501:36015dec7d16	6140	/* Bit 0 : Bit order. */
mbed_official	501:36015dec7d16	6141	#define SPIM_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
mbed_official	501:36015dec7d16	6142	#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
mbed_official	501:36015dec7d16	6143	#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
mbed_official	501:36015dec7d16	6144	#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
mbed_official	501:36015dec7d16	6145
mbed_official	501:36015dec7d16	6146	/* Register: SPIM_ORC */
mbed_official	501:36015dec7d16	6147	/* Description: Over-read character. */
mbed_official	501:36015dec7d16	6148
mbed_official	501:36015dec7d16	6149	/* Bits 7..0 : Over-read character. */
mbed_official	501:36015dec7d16	6150	#define SPIM_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
mbed_official	501:36015dec7d16	6151	#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /!< Bit mask of ORC field. /
mbed_official	501:36015dec7d16	6152
mbed_official	501:36015dec7d16	6153	/* Register: SPIM_POWER */
mbed_official	501:36015dec7d16	6154	/* Description: Peripheral power control. */
mbed_official	501:36015dec7d16	6155
mbed_official	501:36015dec7d16	6156	/* Bit 0 : Peripheral power control. */
mbed_official	501:36015dec7d16	6157	#define SPIM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	501:36015dec7d16	6158	#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	501:36015dec7d16	6159	#define SPIM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	501:36015dec7d16	6160	#define SPIM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	501:36015dec7d16	6161
mbed_official	501:36015dec7d16	6162	/* Register: SPIM_RXD_PTR */
mbed_official	501:36015dec7d16	6163	/* Description: Data pointer. */
mbed_official	501:36015dec7d16	6164
mbed_official	501:36015dec7d16	6165	/* Bits 31..0 : Data pointer. */
mbed_official	501:36015dec7d16	6166	#define SPIM_RXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
mbed_official	501:36015dec7d16	6167	#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
mbed_official	501:36015dec7d16	6168
mbed_official	501:36015dec7d16	6169	/* Register: SPIM_RXD_MAXCNT */
mbed_official	501:36015dec7d16	6170	/* Description: Maximum number of buffer bytes to receive. */
mbed_official	501:36015dec7d16	6171
mbed_official	501:36015dec7d16	6172	/* Bits 7..0 : Maximum number of buffer bytes to receive. */
mbed_official	501:36015dec7d16	6173	#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
mbed_official	501:36015dec7d16	6174	#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
mbed_official	501:36015dec7d16	6175
mbed_official	501:36015dec7d16	6176	/* Register: SPIM_RXD_AMOUNT */
mbed_official	501:36015dec7d16	6177	/* Description: Number of bytes received in the last transaction. */
mbed_official	501:36015dec7d16	6178
mbed_official	501:36015dec7d16	6179	/* Bits 7..0 : Number of bytes received in the last transaction. */
mbed_official	501:36015dec7d16	6180	#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
mbed_official	501:36015dec7d16	6181	#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
mbed_official	501:36015dec7d16	6182
mbed_official	501:36015dec7d16	6183	/* Register: SPIM_TXD_PTR */
mbed_official	501:36015dec7d16	6184	/* Description: Data pointer. */
mbed_official	501:36015dec7d16	6185
mbed_official	501:36015dec7d16	6186	/* Bits 31..0 : Data pointer. */
mbed_official	501:36015dec7d16	6187	#define SPIM_TXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
mbed_official	501:36015dec7d16	6188	#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
mbed_official	501:36015dec7d16	6189
mbed_official	501:36015dec7d16	6190	/* Register: SPIM_TXD_MAXCNT */
mbed_official	501:36015dec7d16	6191	/* Description: Maximum number of buffer bytes to send. */
mbed_official	501:36015dec7d16	6192
mbed_official	501:36015dec7d16	6193	/* Bits 7..0 : Maximum number of buffer bytes to send. */
mbed_official	501:36015dec7d16	6194	#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
mbed_official	501:36015dec7d16	6195	#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
mbed_official	501:36015dec7d16	6196
mbed_official	501:36015dec7d16	6197	/* Register: SPIM_TXD_AMOUNT */
mbed_official	501:36015dec7d16	6198	/* Description: Number of bytes sent in the last transaction. */
mbed_official	501:36015dec7d16	6199
mbed_official	501:36015dec7d16	6200	/* Bits 7..0 : Number of bytes sent in the last transaction. */
mbed_official	501:36015dec7d16	6201	#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
mbed_official	501:36015dec7d16	6202	#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
mbed_official	501:36015dec7d16	6203
mbed_official	501:36015dec7d16	6204
mbed_official	85:e1a8e879a6a9	6205	/* Peripheral: SPIS */
mbed_official	85:e1a8e879a6a9	6206	/* Description: SPI slave 1. */
mbed_official	85:e1a8e879a6a9	6207
mbed_official	85:e1a8e879a6a9	6208	/* Register: SPIS_SHORTS */
mbed_official	85:e1a8e879a6a9	6209	/* Description: Shortcuts for SPIS. */
mbed_official	85:e1a8e879a6a9	6210
mbed_official	85:e1a8e879a6a9	6211	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
mbed_official	85:e1a8e879a6a9	6212	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
mbed_official	85:e1a8e879a6a9	6213	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
mbed_official	85:e1a8e879a6a9	6214	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6215	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6216
mbed_official	85:e1a8e879a6a9	6217	/* Register: SPIS_INTENSET */
mbed_official	85:e1a8e879a6a9	6218	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	6219
mbed_official	85:e1a8e879a6a9	6220	/* Bit 10 : Enable interrupt on ACQUIRED event. */
mbed_official	85:e1a8e879a6a9	6221	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
mbed_official	85:e1a8e879a6a9	6222	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
mbed_official	85:e1a8e879a6a9	6223	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6224	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6225	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6226
mbed_official	85:e1a8e879a6a9	6227	/* Bit 1 : Enable interrupt on END event. */
mbed_official	85:e1a8e879a6a9	6228	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
mbed_official	85:e1a8e879a6a9	6229	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
mbed_official	85:e1a8e879a6a9	6230	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6231	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6232	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6233
mbed_official	85:e1a8e879a6a9	6234	/* Register: SPIS_INTENCLR */
mbed_official	85:e1a8e879a6a9	6235	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	6236
mbed_official	85:e1a8e879a6a9	6237	/* Bit 10 : Disable interrupt on ACQUIRED event. */
mbed_official	85:e1a8e879a6a9	6238	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
mbed_official	85:e1a8e879a6a9	6239	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
mbed_official	85:e1a8e879a6a9	6240	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6241	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6242	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6243
mbed_official	85:e1a8e879a6a9	6244	/* Bit 1 : Disable interrupt on END event. */
mbed_official	85:e1a8e879a6a9	6245	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
mbed_official	85:e1a8e879a6a9	6246	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
mbed_official	85:e1a8e879a6a9	6247	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6248	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6249	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6250
mbed_official	85:e1a8e879a6a9	6251	/* Register: SPIS_SEMSTAT */
mbed_official	85:e1a8e879a6a9	6252	/* Description: Semaphore status. */
mbed_official	85:e1a8e879a6a9	6253
mbed_official	85:e1a8e879a6a9	6254	/* Bits 1..0 : Semaphore status. */
mbed_official	85:e1a8e879a6a9	6255	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
mbed_official	85:e1a8e879a6a9	6256	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
mbed_official	85:e1a8e879a6a9	6257	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
mbed_official	85:e1a8e879a6a9	6258	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
mbed_official	85:e1a8e879a6a9	6259	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
mbed_official	85:e1a8e879a6a9	6260	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
mbed_official	85:e1a8e879a6a9	6261
mbed_official	85:e1a8e879a6a9	6262	/* Register: SPIS_STATUS */
mbed_official	85:e1a8e879a6a9	6263	/* Description: Status from last transaction. */
mbed_official	85:e1a8e879a6a9	6264
mbed_official	85:e1a8e879a6a9	6265	/* Bit 1 : RX buffer overflow detected, and prevented. */
mbed_official	85:e1a8e879a6a9	6266	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
mbed_official	85:e1a8e879a6a9	6267	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
mbed_official	85:e1a8e879a6a9	6268	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
mbed_official	85:e1a8e879a6a9	6269	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
mbed_official	85:e1a8e879a6a9	6270	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
mbed_official	85:e1a8e879a6a9	6271
mbed_official	85:e1a8e879a6a9	6272	/* Bit 0 : TX buffer overread detected, and prevented. */
mbed_official	85:e1a8e879a6a9	6273	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
mbed_official	85:e1a8e879a6a9	6274	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
mbed_official	85:e1a8e879a6a9	6275	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
mbed_official	85:e1a8e879a6a9	6276	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
mbed_official	85:e1a8e879a6a9	6277	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
mbed_official	85:e1a8e879a6a9	6278
mbed_official	85:e1a8e879a6a9	6279	/* Register: SPIS_ENABLE */
mbed_official	85:e1a8e879a6a9	6280	/* Description: Enable SPIS. */
mbed_official	85:e1a8e879a6a9	6281
mbed_official	85:e1a8e879a6a9	6282	/* Bits 2..0 : Enable or disable SPIS. */
mbed_official	85:e1a8e879a6a9	6283	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
mbed_official	85:e1a8e879a6a9	6284	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
mbed_official	85:e1a8e879a6a9	6285	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
mbed_official	85:e1a8e879a6a9	6286	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
mbed_official	85:e1a8e879a6a9	6287
mbed_official	85:e1a8e879a6a9	6288	/* Register: SPIS_MAXRX */
mbed_official	85:e1a8e879a6a9	6289	/* Description: Maximum number of bytes in the receive buffer. */
mbed_official	85:e1a8e879a6a9	6290
mbed_official	85:e1a8e879a6a9	6291	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
mbed_official	85:e1a8e879a6a9	6292	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
mbed_official	85:e1a8e879a6a9	6293	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
mbed_official	85:e1a8e879a6a9	6294
mbed_official	85:e1a8e879a6a9	6295	/* Register: SPIS_AMOUNTRX */
mbed_official	85:e1a8e879a6a9	6296	/* Description: Number of bytes received in last granted transaction. */
mbed_official	85:e1a8e879a6a9	6297
mbed_official	85:e1a8e879a6a9	6298	/* Bits 7..0 : Number of bytes received in last granted transaction. */
mbed_official	85:e1a8e879a6a9	6299	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
mbed_official	85:e1a8e879a6a9	6300	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
mbed_official	85:e1a8e879a6a9	6301
mbed_official	85:e1a8e879a6a9	6302	/* Register: SPIS_MAXTX */
mbed_official	85:e1a8e879a6a9	6303	/* Description: Maximum number of bytes in the transmit buffer. */
mbed_official	85:e1a8e879a6a9	6304
mbed_official	85:e1a8e879a6a9	6305	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
mbed_official	85:e1a8e879a6a9	6306	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
mbed_official	85:e1a8e879a6a9	6307	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
mbed_official	85:e1a8e879a6a9	6308
mbed_official	85:e1a8e879a6a9	6309	/* Register: SPIS_AMOUNTTX */
mbed_official	85:e1a8e879a6a9	6310	/* Description: Number of bytes transmitted in last granted transaction. */
mbed_official	85:e1a8e879a6a9	6311
mbed_official	85:e1a8e879a6a9	6312	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
mbed_official	85:e1a8e879a6a9	6313	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
mbed_official	85:e1a8e879a6a9	6314	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
mbed_official	85:e1a8e879a6a9	6315
mbed_official	85:e1a8e879a6a9	6316	/* Register: SPIS_CONFIG */
mbed_official	85:e1a8e879a6a9	6317	/* Description: Configuration register. */
mbed_official	85:e1a8e879a6a9	6318
mbed_official	85:e1a8e879a6a9	6319	/* Bit 2 : Serial clock (SCK) polarity. */
mbed_official	85:e1a8e879a6a9	6320	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
mbed_official	85:e1a8e879a6a9	6321	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
mbed_official	85:e1a8e879a6a9	6322	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
mbed_official	85:e1a8e879a6a9	6323	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
mbed_official	85:e1a8e879a6a9	6324
mbed_official	85:e1a8e879a6a9	6325	/* Bit 1 : Serial clock (SCK) phase. */
mbed_official	85:e1a8e879a6a9	6326	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
mbed_official	85:e1a8e879a6a9	6327	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
mbed_official	85:e1a8e879a6a9	6328	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
mbed_official	85:e1a8e879a6a9	6329	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
mbed_official	85:e1a8e879a6a9	6330
mbed_official	85:e1a8e879a6a9	6331	/* Bit 0 : Bit order. */
mbed_official	85:e1a8e879a6a9	6332	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
mbed_official	85:e1a8e879a6a9	6333	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
mbed_official	85:e1a8e879a6a9	6334	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
mbed_official	85:e1a8e879a6a9	6335	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
mbed_official	85:e1a8e879a6a9	6336
mbed_official	85:e1a8e879a6a9	6337	/* Register: SPIS_DEF */
mbed_official	85:e1a8e879a6a9	6338	/* Description: Default character. */
mbed_official	85:e1a8e879a6a9	6339
mbed_official	85:e1a8e879a6a9	6340	/* Bits 7..0 : Default character. */
mbed_official	85:e1a8e879a6a9	6341	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
mbed_official	85:e1a8e879a6a9	6342	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
mbed_official	85:e1a8e879a6a9	6343
mbed_official	85:e1a8e879a6a9	6344	/* Register: SPIS_ORC */
mbed_official	85:e1a8e879a6a9	6345	/* Description: Over-read character. */
mbed_official	85:e1a8e879a6a9	6346
mbed_official	85:e1a8e879a6a9	6347	/* Bits 7..0 : Over-read character. */
mbed_official	85:e1a8e879a6a9	6348	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
mbed_official	85:e1a8e879a6a9	6349	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
mbed_official	85:e1a8e879a6a9	6350
mbed_official	85:e1a8e879a6a9	6351	/* Register: SPIS_POWER */
mbed_official	85:e1a8e879a6a9	6352	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	6353
mbed_official	85:e1a8e879a6a9	6354	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	6355	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	6356	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	6357	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	6358	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	6359
mbed_official	85:e1a8e879a6a9	6360
mbed_official	85:e1a8e879a6a9	6361	/* Peripheral: TEMP */
mbed_official	85:e1a8e879a6a9	6362	/* Description: Temperature Sensor. */
mbed_official	85:e1a8e879a6a9	6363
mbed_official	85:e1a8e879a6a9	6364	/* Register: TEMP_INTENSET */
mbed_official	85:e1a8e879a6a9	6365	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	6366
mbed_official	85:e1a8e879a6a9	6367	/* Bit 0 : Enable interrupt on DATARDY event. */
mbed_official	85:e1a8e879a6a9	6368	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
mbed_official	85:e1a8e879a6a9	6369	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
mbed_official	85:e1a8e879a6a9	6370	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6371	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6372	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6373
mbed_official	85:e1a8e879a6a9	6374	/* Register: TEMP_INTENCLR */
mbed_official	85:e1a8e879a6a9	6375	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	6376
mbed_official	85:e1a8e879a6a9	6377	/* Bit 0 : Disable interrupt on DATARDY event. */
mbed_official	85:e1a8e879a6a9	6378	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
mbed_official	85:e1a8e879a6a9	6379	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
mbed_official	85:e1a8e879a6a9	6380	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6381	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6382	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6383
mbed_official	85:e1a8e879a6a9	6384	/* Register: TEMP_POWER */
mbed_official	85:e1a8e879a6a9	6385	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	6386
mbed_official	85:e1a8e879a6a9	6387	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	6388	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	6389	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	6390	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	6391	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	6392
mbed_official	85:e1a8e879a6a9	6393
mbed_official	85:e1a8e879a6a9	6394	/* Peripheral: TIMER */
mbed_official	85:e1a8e879a6a9	6395	/* Description: Timer 0. */
mbed_official	85:e1a8e879a6a9	6396
mbed_official	85:e1a8e879a6a9	6397	/* Register: TIMER_SHORTS */
mbed_official	85:e1a8e879a6a9	6398	/* Description: Shortcuts for Timer. */
mbed_official	85:e1a8e879a6a9	6399
mbed_official	85:e1a8e879a6a9	6400	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
mbed_official	85:e1a8e879a6a9	6401	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
mbed_official	85:e1a8e879a6a9	6402	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
mbed_official	85:e1a8e879a6a9	6403	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6404	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6405
mbed_official	85:e1a8e879a6a9	6406	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
mbed_official	85:e1a8e879a6a9	6407	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
mbed_official	85:e1a8e879a6a9	6408	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
mbed_official	85:e1a8e879a6a9	6409	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6410	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6411
mbed_official	85:e1a8e879a6a9	6412	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
mbed_official	85:e1a8e879a6a9	6413	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
mbed_official	85:e1a8e879a6a9	6414	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
mbed_official	85:e1a8e879a6a9	6415	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6416	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6417
mbed_official	85:e1a8e879a6a9	6418	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
mbed_official	85:e1a8e879a6a9	6419	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
mbed_official	85:e1a8e879a6a9	6420	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
mbed_official	85:e1a8e879a6a9	6421	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6422	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6423
mbed_official	85:e1a8e879a6a9	6424	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
mbed_official	85:e1a8e879a6a9	6425	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
mbed_official	85:e1a8e879a6a9	6426	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
mbed_official	85:e1a8e879a6a9	6427	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6428	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6429
mbed_official	85:e1a8e879a6a9	6430	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
mbed_official	85:e1a8e879a6a9	6431	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
mbed_official	85:e1a8e879a6a9	6432	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
mbed_official	85:e1a8e879a6a9	6433	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6434	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6435
mbed_official	85:e1a8e879a6a9	6436	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
mbed_official	85:e1a8e879a6a9	6437	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
mbed_official	85:e1a8e879a6a9	6438	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
mbed_official	85:e1a8e879a6a9	6439	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6440	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6441
mbed_official	85:e1a8e879a6a9	6442	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
mbed_official	85:e1a8e879a6a9	6443	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
mbed_official	85:e1a8e879a6a9	6444	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
mbed_official	85:e1a8e879a6a9	6445	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6446	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6447
mbed_official	85:e1a8e879a6a9	6448	/* Register: TIMER_INTENSET */
mbed_official	85:e1a8e879a6a9	6449	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	6450
mbed_official	85:e1a8e879a6a9	6451	/* Bit 19 : Enable interrupt on COMPARE[3] */
mbed_official	85:e1a8e879a6a9	6452	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	6453	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	6454	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6455	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6456	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6457
mbed_official	85:e1a8e879a6a9	6458	/* Bit 18 : Enable interrupt on COMPARE[2] */
mbed_official	85:e1a8e879a6a9	6459	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	6460	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	6461	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6462	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6463	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6464
mbed_official	85:e1a8e879a6a9	6465	/* Bit 17 : Enable interrupt on COMPARE[1] */
mbed_official	85:e1a8e879a6a9	6466	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	6467	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	6468	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6469	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6470	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6471
mbed_official	85:e1a8e879a6a9	6472	/* Bit 16 : Enable interrupt on COMPARE[0] */
mbed_official	85:e1a8e879a6a9	6473	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	6474	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	6475	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6476	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6477	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6478
mbed_official	85:e1a8e879a6a9	6479	/* Register: TIMER_INTENCLR */
mbed_official	85:e1a8e879a6a9	6480	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	6481
mbed_official	85:e1a8e879a6a9	6482	/* Bit 19 : Disable interrupt on COMPARE[3] */
mbed_official	85:e1a8e879a6a9	6483	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	6484	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
mbed_official	85:e1a8e879a6a9	6485	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6486	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6487	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6488
mbed_official	85:e1a8e879a6a9	6489	/* Bit 18 : Disable interrupt on COMPARE[2] */
mbed_official	85:e1a8e879a6a9	6490	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	6491	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
mbed_official	85:e1a8e879a6a9	6492	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6493	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6494	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6495
mbed_official	85:e1a8e879a6a9	6496	/* Bit 17 : Disable interrupt on COMPARE[1] */
mbed_official	85:e1a8e879a6a9	6497	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	6498	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
mbed_official	85:e1a8e879a6a9	6499	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6500	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6501	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6502
mbed_official	85:e1a8e879a6a9	6503	/* Bit 16 : Disable interrupt on COMPARE[0] */
mbed_official	85:e1a8e879a6a9	6504	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	6505	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
mbed_official	85:e1a8e879a6a9	6506	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6507	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6508	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6509
mbed_official	85:e1a8e879a6a9	6510	/* Register: TIMER_MODE */
mbed_official	85:e1a8e879a6a9	6511	/* Description: Timer Mode selection. */
mbed_official	85:e1a8e879a6a9	6512
mbed_official	85:e1a8e879a6a9	6513	/* Bit 0 : Select Normal or Counter mode. */
mbed_official	85:e1a8e879a6a9	6514	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
mbed_official	85:e1a8e879a6a9	6515	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
mbed_official	85:e1a8e879a6a9	6516	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
mbed_official	85:e1a8e879a6a9	6517	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
mbed_official	85:e1a8e879a6a9	6518
mbed_official	85:e1a8e879a6a9	6519	/* Register: TIMER_BITMODE */
mbed_official	85:e1a8e879a6a9	6520	/* Description: Sets timer behaviour. */
mbed_official	85:e1a8e879a6a9	6521
mbed_official	85:e1a8e879a6a9	6522	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
mbed_official	85:e1a8e879a6a9	6523	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
mbed_official	85:e1a8e879a6a9	6524	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
mbed_official	85:e1a8e879a6a9	6525	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
mbed_official	85:e1a8e879a6a9	6526	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
mbed_official	85:e1a8e879a6a9	6527	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
mbed_official	85:e1a8e879a6a9	6528	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
mbed_official	85:e1a8e879a6a9	6529
mbed_official	85:e1a8e879a6a9	6530	/* Register: TIMER_PRESCALER */
mbed_official	85:e1a8e879a6a9	6531	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
mbed_official	85:e1a8e879a6a9	6532
mbed_official	85:e1a8e879a6a9	6533	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
mbed_official	85:e1a8e879a6a9	6534	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
mbed_official	85:e1a8e879a6a9	6535	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
mbed_official	85:e1a8e879a6a9	6536
mbed_official	85:e1a8e879a6a9	6537	/* Register: TIMER_POWER */
mbed_official	85:e1a8e879a6a9	6538	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	6539
mbed_official	85:e1a8e879a6a9	6540	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	6541	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	6542	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	6543	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	6544	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	6545
mbed_official	85:e1a8e879a6a9	6546
mbed_official	85:e1a8e879a6a9	6547	/* Peripheral: TWI */
mbed_official	85:e1a8e879a6a9	6548	/* Description: Two-wire interface master 0. */
mbed_official	85:e1a8e879a6a9	6549
mbed_official	85:e1a8e879a6a9	6550	/* Register: TWI_SHORTS */
mbed_official	85:e1a8e879a6a9	6551	/* Description: Shortcuts for TWI. */
mbed_official	85:e1a8e879a6a9	6552
mbed_official	85:e1a8e879a6a9	6553	/* Bit 1 : Shortcut between BB event and the STOP task. */
mbed_official	85:e1a8e879a6a9	6554	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
mbed_official	85:e1a8e879a6a9	6555	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
mbed_official	85:e1a8e879a6a9	6556	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6557	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6558
mbed_official	85:e1a8e879a6a9	6559	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
mbed_official	85:e1a8e879a6a9	6560	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
mbed_official	85:e1a8e879a6a9	6561	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
mbed_official	85:e1a8e879a6a9	6562	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6563	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6564
mbed_official	85:e1a8e879a6a9	6565	/* Register: TWI_INTENSET */
mbed_official	85:e1a8e879a6a9	6566	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	6567
mbed_official	501:36015dec7d16	6568	/* Bit 18 : Enable interrupt on SUSPENDED event. */
mbed_official	501:36015dec7d16	6569	#define TWI_INTENSET_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
mbed_official	501:36015dec7d16	6570	#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
mbed_official	501:36015dec7d16	6571	#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	501:36015dec7d16	6572	#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	501:36015dec7d16	6573	#define TWI_INTENSET_SUSPENDED_Set (1UL) /!< Enable interrupt on write. /
mbed_official	501:36015dec7d16	6574
mbed_official	85:e1a8e879a6a9	6575	/* Bit 14 : Enable interrupt on BB event. */
mbed_official	85:e1a8e879a6a9	6576	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
mbed_official	85:e1a8e879a6a9	6577	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
mbed_official	85:e1a8e879a6a9	6578	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6579	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6580	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6581
mbed_official	85:e1a8e879a6a9	6582	/* Bit 9 : Enable interrupt on ERROR event. */
mbed_official	85:e1a8e879a6a9	6583	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
mbed_official	85:e1a8e879a6a9	6584	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
mbed_official	85:e1a8e879a6a9	6585	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6586	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6587	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6588
mbed_official	85:e1a8e879a6a9	6589	/* Bit 7 : Enable interrupt on TXDSENT event. */
mbed_official	85:e1a8e879a6a9	6590	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
mbed_official	85:e1a8e879a6a9	6591	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
mbed_official	85:e1a8e879a6a9	6592	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6593	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6594	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6595
mbed_official	85:e1a8e879a6a9	6596	/* Bit 2 : Enable interrupt on READY event. */
mbed_official	85:e1a8e879a6a9	6597	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
mbed_official	85:e1a8e879a6a9	6598	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
mbed_official	85:e1a8e879a6a9	6599	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6600	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6601	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6602
mbed_official	85:e1a8e879a6a9	6603	/* Bit 1 : Enable interrupt on STOPPED event. */
mbed_official	85:e1a8e879a6a9	6604	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
mbed_official	85:e1a8e879a6a9	6605	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
mbed_official	85:e1a8e879a6a9	6606	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6607	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6608	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6609
mbed_official	85:e1a8e879a6a9	6610	/* Register: TWI_INTENCLR */
mbed_official	85:e1a8e879a6a9	6611	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	6612
mbed_official	501:36015dec7d16	6613	/* Bit 18 : Disable interrupt on SUSPENDED event. */
mbed_official	501:36015dec7d16	6614	#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
mbed_official	501:36015dec7d16	6615	#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
mbed_official	501:36015dec7d16	6616	#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	501:36015dec7d16	6617	#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	501:36015dec7d16	6618	#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	501:36015dec7d16	6619
mbed_official	85:e1a8e879a6a9	6620	/* Bit 14 : Disable interrupt on BB event. */
mbed_official	85:e1a8e879a6a9	6621	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
mbed_official	85:e1a8e879a6a9	6622	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
mbed_official	85:e1a8e879a6a9	6623	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6624	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6625	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6626
mbed_official	85:e1a8e879a6a9	6627	/* Bit 9 : Disable interrupt on ERROR event. */
mbed_official	85:e1a8e879a6a9	6628	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
mbed_official	85:e1a8e879a6a9	6629	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
mbed_official	85:e1a8e879a6a9	6630	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6631	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6632	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6633
mbed_official	85:e1a8e879a6a9	6634	/* Bit 7 : Disable interrupt on TXDSENT event. */
mbed_official	85:e1a8e879a6a9	6635	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
mbed_official	85:e1a8e879a6a9	6636	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
mbed_official	85:e1a8e879a6a9	6637	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6638	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6639	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6640
mbed_official	85:e1a8e879a6a9	6641	/* Bit 2 : Disable interrupt on RXDREADY event. */
mbed_official	85:e1a8e879a6a9	6642	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
mbed_official	85:e1a8e879a6a9	6643	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
mbed_official	85:e1a8e879a6a9	6644	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6645	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6646	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6647
mbed_official	85:e1a8e879a6a9	6648	/* Bit 1 : Disable interrupt on STOPPED event. */
mbed_official	85:e1a8e879a6a9	6649	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
mbed_official	85:e1a8e879a6a9	6650	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
mbed_official	85:e1a8e879a6a9	6651	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6652	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6653	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6654
mbed_official	85:e1a8e879a6a9	6655	/* Register: TWI_ERRORSRC */
mbed_official	85:e1a8e879a6a9	6656	/* Description: Two-wire error source. Write error field to 1 to clear error. */
mbed_official	85:e1a8e879a6a9	6657
mbed_official	85:e1a8e879a6a9	6658	/* Bit 2 : NACK received after sending a data byte. */
mbed_official	85:e1a8e879a6a9	6659	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
mbed_official	85:e1a8e879a6a9	6660	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
mbed_official	85:e1a8e879a6a9	6661	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
mbed_official	85:e1a8e879a6a9	6662	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
mbed_official	85:e1a8e879a6a9	6663	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
mbed_official	85:e1a8e879a6a9	6664
mbed_official	85:e1a8e879a6a9	6665	/* Bit 1 : NACK received after sending the address. */
mbed_official	85:e1a8e879a6a9	6666	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
mbed_official	85:e1a8e879a6a9	6667	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
mbed_official	85:e1a8e879a6a9	6668	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
mbed_official	85:e1a8e879a6a9	6669	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
mbed_official	85:e1a8e879a6a9	6670	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
mbed_official	85:e1a8e879a6a9	6671
mbed_official	85:e1a8e879a6a9	6672	/* Register: TWI_ENABLE */
mbed_official	85:e1a8e879a6a9	6673	/* Description: Enable two-wire master. */
mbed_official	85:e1a8e879a6a9	6674
mbed_official	85:e1a8e879a6a9	6675	/* Bits 2..0 : Enable or disable W2M */
mbed_official	85:e1a8e879a6a9	6676	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
mbed_official	85:e1a8e879a6a9	6677	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
mbed_official	85:e1a8e879a6a9	6678	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	6679	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
mbed_official	85:e1a8e879a6a9	6680
mbed_official	85:e1a8e879a6a9	6681	/* Register: TWI_RXD */
mbed_official	85:e1a8e879a6a9	6682	/* Description: RX data register. */
mbed_official	85:e1a8e879a6a9	6683
mbed_official	85:e1a8e879a6a9	6684	/* Bits 7..0 : RX data from last transfer. */
mbed_official	85:e1a8e879a6a9	6685	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
mbed_official	85:e1a8e879a6a9	6686	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
mbed_official	85:e1a8e879a6a9	6687
mbed_official	85:e1a8e879a6a9	6688	/* Register: TWI_TXD */
mbed_official	85:e1a8e879a6a9	6689	/* Description: TX data register. */
mbed_official	85:e1a8e879a6a9	6690
mbed_official	85:e1a8e879a6a9	6691	/* Bits 7..0 : TX data for next transfer. */
mbed_official	85:e1a8e879a6a9	6692	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
mbed_official	85:e1a8e879a6a9	6693	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
mbed_official	85:e1a8e879a6a9	6694
mbed_official	85:e1a8e879a6a9	6695	/* Register: TWI_FREQUENCY */
mbed_official	85:e1a8e879a6a9	6696	/* Description: Two-wire frequency. */
mbed_official	85:e1a8e879a6a9	6697
mbed_official	85:e1a8e879a6a9	6698	/* Bits 31..0 : Two-wire master clock frequency. */
mbed_official	85:e1a8e879a6a9	6699	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
mbed_official	85:e1a8e879a6a9	6700	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
mbed_official	85:e1a8e879a6a9	6701	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
mbed_official	85:e1a8e879a6a9	6702	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
mbed_official	85:e1a8e879a6a9	6703	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
mbed_official	85:e1a8e879a6a9	6704
mbed_official	85:e1a8e879a6a9	6705	/* Register: TWI_ADDRESS */
mbed_official	85:e1a8e879a6a9	6706	/* Description: Address used in the two-wire transfer. */
mbed_official	85:e1a8e879a6a9	6707
mbed_official	85:e1a8e879a6a9	6708	/* Bits 6..0 : Two-wire address. */
mbed_official	85:e1a8e879a6a9	6709	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
mbed_official	85:e1a8e879a6a9	6710	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
mbed_official	85:e1a8e879a6a9	6711
mbed_official	85:e1a8e879a6a9	6712	/* Register: TWI_POWER */
mbed_official	85:e1a8e879a6a9	6713	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	6714
mbed_official	85:e1a8e879a6a9	6715	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	6716	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	6717	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	6718	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	6719	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	6720
mbed_official	85:e1a8e879a6a9	6721
mbed_official	85:e1a8e879a6a9	6722	/* Peripheral: UART */
mbed_official	85:e1a8e879a6a9	6723	/* Description: Universal Asynchronous Receiver/Transmitter. */
mbed_official	85:e1a8e879a6a9	6724
mbed_official	85:e1a8e879a6a9	6725	/* Register: UART_SHORTS */
mbed_official	501:36015dec7d16	6726	/* Description: Shortcuts for UART. */
mbed_official	85:e1a8e879a6a9	6727
mbed_official	85:e1a8e879a6a9	6728	/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
mbed_official	85:e1a8e879a6a9	6729	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
mbed_official	85:e1a8e879a6a9	6730	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
mbed_official	85:e1a8e879a6a9	6731	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6732	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6733
mbed_official	85:e1a8e879a6a9	6734	/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
mbed_official	85:e1a8e879a6a9	6735	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
mbed_official	85:e1a8e879a6a9	6736	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
mbed_official	85:e1a8e879a6a9	6737	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
mbed_official	85:e1a8e879a6a9	6738	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
mbed_official	85:e1a8e879a6a9	6739
mbed_official	85:e1a8e879a6a9	6740	/* Register: UART_INTENSET */
mbed_official	85:e1a8e879a6a9	6741	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	6742
mbed_official	85:e1a8e879a6a9	6743	/* Bit 17 : Enable interrupt on RXTO event. */
mbed_official	85:e1a8e879a6a9	6744	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
mbed_official	85:e1a8e879a6a9	6745	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
mbed_official	85:e1a8e879a6a9	6746	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6747	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6748	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6749
mbed_official	85:e1a8e879a6a9	6750	/* Bit 9 : Enable interrupt on ERROR event. */
mbed_official	85:e1a8e879a6a9	6751	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
mbed_official	85:e1a8e879a6a9	6752	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
mbed_official	85:e1a8e879a6a9	6753	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6754	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6755	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6756
mbed_official	85:e1a8e879a6a9	6757	/* Bit 7 : Enable interrupt on TXRDY event. */
mbed_official	85:e1a8e879a6a9	6758	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
mbed_official	85:e1a8e879a6a9	6759	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
mbed_official	85:e1a8e879a6a9	6760	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6761	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6762	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6763
mbed_official	85:e1a8e879a6a9	6764	/* Bit 2 : Enable interrupt on RXRDY event. */
mbed_official	85:e1a8e879a6a9	6765	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
mbed_official	85:e1a8e879a6a9	6766	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
mbed_official	85:e1a8e879a6a9	6767	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6768	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6769	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6770
mbed_official	85:e1a8e879a6a9	6771	/* Bit 1 : Enable interrupt on NCTS event. */
mbed_official	85:e1a8e879a6a9	6772	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
mbed_official	85:e1a8e879a6a9	6773	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
mbed_official	85:e1a8e879a6a9	6774	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6775	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6776	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6777
mbed_official	85:e1a8e879a6a9	6778	/* Bit 0 : Enable interrupt on CTS event. */
mbed_official	85:e1a8e879a6a9	6779	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
mbed_official	85:e1a8e879a6a9	6780	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
mbed_official	85:e1a8e879a6a9	6781	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6782	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6783	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6784
mbed_official	85:e1a8e879a6a9	6785	/* Register: UART_INTENCLR */
mbed_official	85:e1a8e879a6a9	6786	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	6787
mbed_official	85:e1a8e879a6a9	6788	/* Bit 17 : Disable interrupt on RXTO event. */
mbed_official	85:e1a8e879a6a9	6789	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
mbed_official	85:e1a8e879a6a9	6790	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
mbed_official	85:e1a8e879a6a9	6791	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6792	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6793	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6794
mbed_official	85:e1a8e879a6a9	6795	/* Bit 9 : Disable interrupt on ERROR event. */
mbed_official	85:e1a8e879a6a9	6796	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
mbed_official	85:e1a8e879a6a9	6797	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
mbed_official	85:e1a8e879a6a9	6798	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6799	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6800	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6801
mbed_official	85:e1a8e879a6a9	6802	/* Bit 7 : Disable interrupt on TXRDY event. */
mbed_official	85:e1a8e879a6a9	6803	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
mbed_official	85:e1a8e879a6a9	6804	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
mbed_official	85:e1a8e879a6a9	6805	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6806	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6807	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6808
mbed_official	85:e1a8e879a6a9	6809	/* Bit 2 : Disable interrupt on RXRDY event. */
mbed_official	85:e1a8e879a6a9	6810	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
mbed_official	85:e1a8e879a6a9	6811	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
mbed_official	85:e1a8e879a6a9	6812	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6813	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6814	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6815
mbed_official	85:e1a8e879a6a9	6816	/* Bit 1 : Disable interrupt on NCTS event. */
mbed_official	85:e1a8e879a6a9	6817	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
mbed_official	85:e1a8e879a6a9	6818	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
mbed_official	85:e1a8e879a6a9	6819	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6820	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6821	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6822
mbed_official	85:e1a8e879a6a9	6823	/* Bit 0 : Disable interrupt on CTS event. */
mbed_official	85:e1a8e879a6a9	6824	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
mbed_official	85:e1a8e879a6a9	6825	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
mbed_official	85:e1a8e879a6a9	6826	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6827	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6828	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6829
mbed_official	85:e1a8e879a6a9	6830	/* Register: UART_ERRORSRC */
mbed_official	85:e1a8e879a6a9	6831	/* Description: Error source. Write error field to 1 to clear error. */
mbed_official	85:e1a8e879a6a9	6832
mbed_official	85:e1a8e879a6a9	6833	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
mbed_official	85:e1a8e879a6a9	6834	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
mbed_official	85:e1a8e879a6a9	6835	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
mbed_official	85:e1a8e879a6a9	6836	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
mbed_official	85:e1a8e879a6a9	6837	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
mbed_official	85:e1a8e879a6a9	6838	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
mbed_official	85:e1a8e879a6a9	6839
mbed_official	85:e1a8e879a6a9	6840	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
mbed_official	85:e1a8e879a6a9	6841	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
mbed_official	85:e1a8e879a6a9	6842	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
mbed_official	85:e1a8e879a6a9	6843	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
mbed_official	85:e1a8e879a6a9	6844	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
mbed_official	85:e1a8e879a6a9	6845	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
mbed_official	85:e1a8e879a6a9	6846
mbed_official	85:e1a8e879a6a9	6847	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
mbed_official	85:e1a8e879a6a9	6848	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
mbed_official	85:e1a8e879a6a9	6849	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
mbed_official	85:e1a8e879a6a9	6850	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
mbed_official	85:e1a8e879a6a9	6851	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
mbed_official	85:e1a8e879a6a9	6852	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
mbed_official	85:e1a8e879a6a9	6853
mbed_official	85:e1a8e879a6a9	6854	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
mbed_official	85:e1a8e879a6a9	6855	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
mbed_official	85:e1a8e879a6a9	6856	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
mbed_official	85:e1a8e879a6a9	6857	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
mbed_official	85:e1a8e879a6a9	6858	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
mbed_official	85:e1a8e879a6a9	6859	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
mbed_official	85:e1a8e879a6a9	6860
mbed_official	85:e1a8e879a6a9	6861	/* Register: UART_ENABLE */
mbed_official	85:e1a8e879a6a9	6862	/* Description: Enable UART and acquire IOs. */
mbed_official	85:e1a8e879a6a9	6863
mbed_official	85:e1a8e879a6a9	6864	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
mbed_official	85:e1a8e879a6a9	6865	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
mbed_official	85:e1a8e879a6a9	6866	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
mbed_official	85:e1a8e879a6a9	6867	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
mbed_official	85:e1a8e879a6a9	6868	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
mbed_official	85:e1a8e879a6a9	6869
mbed_official	85:e1a8e879a6a9	6870	/* Register: UART_RXD */
mbed_official	501:36015dec7d16	6871	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
mbed_official	85:e1a8e879a6a9	6872
mbed_official	85:e1a8e879a6a9	6873	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
mbed_official	85:e1a8e879a6a9	6874	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
mbed_official	85:e1a8e879a6a9	6875	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
mbed_official	85:e1a8e879a6a9	6876
mbed_official	85:e1a8e879a6a9	6877	/* Register: UART_TXD */
mbed_official	85:e1a8e879a6a9	6878	/* Description: TXD register. */
mbed_official	85:e1a8e879a6a9	6879
mbed_official	85:e1a8e879a6a9	6880	/* Bits 7..0 : TX data for transfer. */
mbed_official	85:e1a8e879a6a9	6881	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
mbed_official	85:e1a8e879a6a9	6882	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
mbed_official	85:e1a8e879a6a9	6883
mbed_official	85:e1a8e879a6a9	6884	/* Register: UART_BAUDRATE */
mbed_official	85:e1a8e879a6a9	6885	/* Description: UART Baudrate. */
mbed_official	85:e1a8e879a6a9	6886
mbed_official	85:e1a8e879a6a9	6887	/* Bits 31..0 : UART baudrate. */
mbed_official	85:e1a8e879a6a9	6888	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
mbed_official	85:e1a8e879a6a9	6889	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
mbed_official	85:e1a8e879a6a9	6890	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
mbed_official	85:e1a8e879a6a9	6891	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
mbed_official	85:e1a8e879a6a9	6892	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
mbed_official	85:e1a8e879a6a9	6893	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
mbed_official	85:e1a8e879a6a9	6894	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
mbed_official	85:e1a8e879a6a9	6895	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
mbed_official	85:e1a8e879a6a9	6896	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
mbed_official	85:e1a8e879a6a9	6897	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
mbed_official	85:e1a8e879a6a9	6898	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
mbed_official	85:e1a8e879a6a9	6899	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
mbed_official	85:e1a8e879a6a9	6900	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
mbed_official	85:e1a8e879a6a9	6901	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
mbed_official	85:e1a8e879a6a9	6902	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
mbed_official	85:e1a8e879a6a9	6903	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
mbed_official	85:e1a8e879a6a9	6904	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /!< 921600 baud. /
mbed_official	85:e1a8e879a6a9	6905	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
mbed_official	85:e1a8e879a6a9	6906
mbed_official	85:e1a8e879a6a9	6907	/* Register: UART_CONFIG */
mbed_official	85:e1a8e879a6a9	6908	/* Description: Configuration of parity and hardware flow control register. */
mbed_official	85:e1a8e879a6a9	6909
mbed_official	85:e1a8e879a6a9	6910	/* Bits 3..1 : Include parity bit. */
mbed_official	85:e1a8e879a6a9	6911	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
mbed_official	85:e1a8e879a6a9	6912	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
mbed_official	85:e1a8e879a6a9	6913	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
mbed_official	85:e1a8e879a6a9	6914	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
mbed_official	85:e1a8e879a6a9	6915
mbed_official	85:e1a8e879a6a9	6916	/* Bit 0 : Hardware flow control. */
mbed_official	85:e1a8e879a6a9	6917	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
mbed_official	85:e1a8e879a6a9	6918	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
mbed_official	85:e1a8e879a6a9	6919	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
mbed_official	85:e1a8e879a6a9	6920	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
mbed_official	85:e1a8e879a6a9	6921
mbed_official	85:e1a8e879a6a9	6922	/* Register: UART_POWER */
mbed_official	85:e1a8e879a6a9	6923	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	6924
mbed_official	85:e1a8e879a6a9	6925	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	6926	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	6927	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	6928	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	6929	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	6930
mbed_official	85:e1a8e879a6a9	6931
mbed_official	85:e1a8e879a6a9	6932	/* Peripheral: UICR */
mbed_official	85:e1a8e879a6a9	6933	/* Description: User Information Configuration. */
mbed_official	85:e1a8e879a6a9	6934
mbed_official	85:e1a8e879a6a9	6935	/* Register: UICR_RBPCONF */
mbed_official	85:e1a8e879a6a9	6936	/* Description: Readback protection configuration. */
mbed_official	85:e1a8e879a6a9	6937
mbed_official	85:e1a8e879a6a9	6938	/* Bits 15..8 : Readback protect all code in the device. */
mbed_official	85:e1a8e879a6a9	6939	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
mbed_official	85:e1a8e879a6a9	6940	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
mbed_official	85:e1a8e879a6a9	6941	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	6942	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
mbed_official	85:e1a8e879a6a9	6943
mbed_official	85:e1a8e879a6a9	6944	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
mbed_official	85:e1a8e879a6a9	6945	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
mbed_official	85:e1a8e879a6a9	6946	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
mbed_official	85:e1a8e879a6a9	6947	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
mbed_official	85:e1a8e879a6a9	6948	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
mbed_official	85:e1a8e879a6a9	6949
mbed_official	85:e1a8e879a6a9	6950	/* Register: UICR_XTALFREQ */
mbed_official	85:e1a8e879a6a9	6951	/* Description: Reset value for CLOCK XTALFREQ register. */
mbed_official	85:e1a8e879a6a9	6952
mbed_official	85:e1a8e879a6a9	6953	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
mbed_official	85:e1a8e879a6a9	6954	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
mbed_official	85:e1a8e879a6a9	6955	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
mbed_official	85:e1a8e879a6a9	6956	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
mbed_official	85:e1a8e879a6a9	6957	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
mbed_official	85:e1a8e879a6a9	6958
mbed_official	85:e1a8e879a6a9	6959	/* Register: UICR_FWID */
mbed_official	85:e1a8e879a6a9	6960	/* Description: Firmware ID. */
mbed_official	85:e1a8e879a6a9	6961
mbed_official	85:e1a8e879a6a9	6962	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
mbed_official	85:e1a8e879a6a9	6963	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
mbed_official	85:e1a8e879a6a9	6964	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
mbed_official	85:e1a8e879a6a9	6965
mbed_official	85:e1a8e879a6a9	6966
mbed_official	85:e1a8e879a6a9	6967	/* Peripheral: WDT */
mbed_official	85:e1a8e879a6a9	6968	/* Description: Watchdog Timer. */
mbed_official	85:e1a8e879a6a9	6969
mbed_official	85:e1a8e879a6a9	6970	/* Register: WDT_INTENSET */
mbed_official	85:e1a8e879a6a9	6971	/* Description: Interrupt enable set register. */
mbed_official	85:e1a8e879a6a9	6972
mbed_official	85:e1a8e879a6a9	6973	/* Bit 0 : Enable interrupt on TIMEOUT event. */
mbed_official	85:e1a8e879a6a9	6974	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
mbed_official	85:e1a8e879a6a9	6975	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
mbed_official	85:e1a8e879a6a9	6976	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6977	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6978	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6979
mbed_official	85:e1a8e879a6a9	6980	/* Register: WDT_INTENCLR */
mbed_official	85:e1a8e879a6a9	6981	/* Description: Interrupt enable clear register. */
mbed_official	85:e1a8e879a6a9	6982
mbed_official	85:e1a8e879a6a9	6983	/* Bit 0 : Disable interrupt on TIMEOUT event. */
mbed_official	85:e1a8e879a6a9	6984	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
mbed_official	85:e1a8e879a6a9	6985	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
mbed_official	85:e1a8e879a6a9	6986	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
mbed_official	85:e1a8e879a6a9	6987	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
mbed_official	85:e1a8e879a6a9	6988	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
mbed_official	85:e1a8e879a6a9	6989
mbed_official	85:e1a8e879a6a9	6990	/* Register: WDT_RUNSTATUS */
mbed_official	85:e1a8e879a6a9	6991	/* Description: Watchdog running status. */
mbed_official	85:e1a8e879a6a9	6992
mbed_official	85:e1a8e879a6a9	6993	/* Bit 0 : Watchdog running status. */
mbed_official	85:e1a8e879a6a9	6994	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
mbed_official	85:e1a8e879a6a9	6995	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
mbed_official	85:e1a8e879a6a9	6996	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
mbed_official	85:e1a8e879a6a9	6997	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
mbed_official	85:e1a8e879a6a9	6998
mbed_official	85:e1a8e879a6a9	6999	/* Register: WDT_REQSTATUS */
mbed_official	85:e1a8e879a6a9	7000	/* Description: Request status. */
mbed_official	85:e1a8e879a6a9	7001
mbed_official	85:e1a8e879a6a9	7002	/* Bit 7 : Request status for RR[7]. */
mbed_official	85:e1a8e879a6a9	7003	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
mbed_official	85:e1a8e879a6a9	7004	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
mbed_official	85:e1a8e879a6a9	7005	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
mbed_official	85:e1a8e879a6a9	7006	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
mbed_official	85:e1a8e879a6a9	7007
mbed_official	85:e1a8e879a6a9	7008	/* Bit 6 : Request status for RR[6]. */
mbed_official	85:e1a8e879a6a9	7009	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
mbed_official	85:e1a8e879a6a9	7010	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
mbed_official	85:e1a8e879a6a9	7011	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
mbed_official	85:e1a8e879a6a9	7012	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
mbed_official	85:e1a8e879a6a9	7013
mbed_official	85:e1a8e879a6a9	7014	/* Bit 5 : Request status for RR[5]. */
mbed_official	85:e1a8e879a6a9	7015	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
mbed_official	85:e1a8e879a6a9	7016	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
mbed_official	85:e1a8e879a6a9	7017	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
mbed_official	85:e1a8e879a6a9	7018	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
mbed_official	85:e1a8e879a6a9	7019
mbed_official	85:e1a8e879a6a9	7020	/* Bit 4 : Request status for RR[4]. */
mbed_official	85:e1a8e879a6a9	7021	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
mbed_official	85:e1a8e879a6a9	7022	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
mbed_official	85:e1a8e879a6a9	7023	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
mbed_official	85:e1a8e879a6a9	7024	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
mbed_official	85:e1a8e879a6a9	7025
mbed_official	85:e1a8e879a6a9	7026	/* Bit 3 : Request status for RR[3]. */
mbed_official	85:e1a8e879a6a9	7027	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
mbed_official	85:e1a8e879a6a9	7028	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
mbed_official	85:e1a8e879a6a9	7029	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
mbed_official	85:e1a8e879a6a9	7030	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
mbed_official	85:e1a8e879a6a9	7031
mbed_official	85:e1a8e879a6a9	7032	/* Bit 2 : Request status for RR[2]. */
mbed_official	85:e1a8e879a6a9	7033	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
mbed_official	85:e1a8e879a6a9	7034	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
mbed_official	85:e1a8e879a6a9	7035	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
mbed_official	85:e1a8e879a6a9	7036	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
mbed_official	85:e1a8e879a6a9	7037
mbed_official	85:e1a8e879a6a9	7038	/* Bit 1 : Request status for RR[1]. */
mbed_official	85:e1a8e879a6a9	7039	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
mbed_official	85:e1a8e879a6a9	7040	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
mbed_official	85:e1a8e879a6a9	7041	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
mbed_official	85:e1a8e879a6a9	7042	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
mbed_official	85:e1a8e879a6a9	7043
mbed_official	85:e1a8e879a6a9	7044	/* Bit 0 : Request status for RR[0]. */
mbed_official	85:e1a8e879a6a9	7045	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
mbed_official	85:e1a8e879a6a9	7046	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
mbed_official	85:e1a8e879a6a9	7047	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
mbed_official	85:e1a8e879a6a9	7048	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
mbed_official	85:e1a8e879a6a9	7049
mbed_official	85:e1a8e879a6a9	7050	/* Register: WDT_RREN */
mbed_official	85:e1a8e879a6a9	7051	/* Description: Reload request enable. */
mbed_official	85:e1a8e879a6a9	7052
mbed_official	85:e1a8e879a6a9	7053	/* Bit 7 : Enable or disable RR[7] register. */
mbed_official	85:e1a8e879a6a9	7054	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
mbed_official	85:e1a8e879a6a9	7055	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
mbed_official	85:e1a8e879a6a9	7056	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
mbed_official	85:e1a8e879a6a9	7057	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
mbed_official	85:e1a8e879a6a9	7058
mbed_official	85:e1a8e879a6a9	7059	/* Bit 6 : Enable or disable RR[6] register. */
mbed_official	85:e1a8e879a6a9	7060	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
mbed_official	85:e1a8e879a6a9	7061	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
mbed_official	85:e1a8e879a6a9	7062	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
mbed_official	85:e1a8e879a6a9	7063	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
mbed_official	85:e1a8e879a6a9	7064
mbed_official	85:e1a8e879a6a9	7065	/* Bit 5 : Enable or disable RR[5] register. */
mbed_official	85:e1a8e879a6a9	7066	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
mbed_official	85:e1a8e879a6a9	7067	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
mbed_official	85:e1a8e879a6a9	7068	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
mbed_official	85:e1a8e879a6a9	7069	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
mbed_official	85:e1a8e879a6a9	7070
mbed_official	85:e1a8e879a6a9	7071	/* Bit 4 : Enable or disable RR[4] register. */
mbed_official	85:e1a8e879a6a9	7072	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
mbed_official	85:e1a8e879a6a9	7073	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
mbed_official	85:e1a8e879a6a9	7074	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
mbed_official	85:e1a8e879a6a9	7075	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
mbed_official	85:e1a8e879a6a9	7076
mbed_official	85:e1a8e879a6a9	7077	/* Bit 3 : Enable or disable RR[3] register. */
mbed_official	85:e1a8e879a6a9	7078	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
mbed_official	85:e1a8e879a6a9	7079	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
mbed_official	85:e1a8e879a6a9	7080	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
mbed_official	85:e1a8e879a6a9	7081	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
mbed_official	85:e1a8e879a6a9	7082
mbed_official	85:e1a8e879a6a9	7083	/* Bit 2 : Enable or disable RR[2] register. */
mbed_official	85:e1a8e879a6a9	7084	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
mbed_official	85:e1a8e879a6a9	7085	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
mbed_official	85:e1a8e879a6a9	7086	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
mbed_official	85:e1a8e879a6a9	7087	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
mbed_official	85:e1a8e879a6a9	7088
mbed_official	85:e1a8e879a6a9	7089	/* Bit 1 : Enable or disable RR[1] register. */
mbed_official	85:e1a8e879a6a9	7090	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
mbed_official	85:e1a8e879a6a9	7091	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
mbed_official	85:e1a8e879a6a9	7092	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
mbed_official	85:e1a8e879a6a9	7093	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
mbed_official	85:e1a8e879a6a9	7094
mbed_official	85:e1a8e879a6a9	7095	/* Bit 0 : Enable or disable RR[0] register. */
mbed_official	85:e1a8e879a6a9	7096	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
mbed_official	85:e1a8e879a6a9	7097	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
mbed_official	85:e1a8e879a6a9	7098	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
mbed_official	85:e1a8e879a6a9	7099	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
mbed_official	85:e1a8e879a6a9	7100
mbed_official	85:e1a8e879a6a9	7101	/* Register: WDT_CONFIG */
mbed_official	85:e1a8e879a6a9	7102	/* Description: Configuration register. */
mbed_official	85:e1a8e879a6a9	7103
mbed_official	85:e1a8e879a6a9	7104	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
mbed_official	85:e1a8e879a6a9	7105	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
mbed_official	85:e1a8e879a6a9	7106	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
mbed_official	85:e1a8e879a6a9	7107	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
mbed_official	85:e1a8e879a6a9	7108	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
mbed_official	85:e1a8e879a6a9	7109
mbed_official	85:e1a8e879a6a9	7110	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
mbed_official	85:e1a8e879a6a9	7111	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
mbed_official	85:e1a8e879a6a9	7112	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
mbed_official	85:e1a8e879a6a9	7113	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
mbed_official	85:e1a8e879a6a9	7114	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
mbed_official	85:e1a8e879a6a9	7115
mbed_official	85:e1a8e879a6a9	7116	/* Register: WDT_RR */
mbed_official	85:e1a8e879a6a9	7117	/* Description: Reload requests registers. */
mbed_official	85:e1a8e879a6a9	7118
mbed_official	85:e1a8e879a6a9	7119	/* Bits 31..0 : Reload register. */
mbed_official	85:e1a8e879a6a9	7120	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
mbed_official	85:e1a8e879a6a9	7121	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
mbed_official	85:e1a8e879a6a9	7122	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
mbed_official	85:e1a8e879a6a9	7123
mbed_official	85:e1a8e879a6a9	7124	/* Register: WDT_POWER */
mbed_official	85:e1a8e879a6a9	7125	/* Description: Peripheral power control. */
mbed_official	85:e1a8e879a6a9	7126
mbed_official	85:e1a8e879a6a9	7127	/* Bit 0 : Peripheral power control. */
mbed_official	85:e1a8e879a6a9	7128	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
mbed_official	85:e1a8e879a6a9	7129	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
mbed_official	85:e1a8e879a6a9	7130	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
mbed_official	85:e1a8e879a6a9	7131	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
mbed_official	85:e1a8e879a6a9	7132
mbed_official	85:e1a8e879a6a9	7133
mbed_official	85:e1a8e879a6a9	7134	/lint --flb "Leave library region" /
mbed_official	85:e1a8e879a6a9	7135	#endif