CMSIS DSP library
Dependents: performance_timer Surfboard_ gps2rtty Capstone ... more
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Diff: cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
- Revision:
- 2:da51fb522205
- Parent:
- 1:fdd22bb7aa52
- Child:
- 3:7a284390b0ce
--- a/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_opt_q15.c Wed Nov 28 12:30:09 2012 +0000 +++ b/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_opt_q15.c Thu May 30 17:10:11 2013 +0100 @@ -2,12 +2,12 @@ * Copyright (C) 2010 ARM Limited. All rights reserved. * * $Date: 15. February 2012 -* $Revision: V1.1.0 +* $Revision: V1.1.0 * -* Project: CMSIS DSP Library -* Title: arm_conv_partial_fast_opt_q15.c +* Project: CMSIS DSP Library +* Title: arm_conv_partial_fast_opt_q15.c * -* Description: Fast Q15 Partial convolution. +* Description: Fast Q15 Partial convolution. * * Target Processor: Cortex-M4/Cortex-M3 * @@ -61,7 +61,7 @@ * * \par Restrictions * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE - * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit + * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit * */ @@ -756,7 +756,7 @@ return (status); } -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ /** * @} end of PartialConv group