Lluis Nadal
AD5627 test. Dual 12-bit DAC with I2C interface.
main.cpp@0:2afedb12bdfd, 2011-08-12 (annotated)
- Committer:
- lnadal
- Date:
- Fri Aug 12 15:27:31 2011 +0000
- Revision:
- 0:2afedb12bdfd
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| lnadal | 0:2afedb12bdfd | 1 | #include "mbed.h" |
| lnadal | 0:2afedb12bdfd | 2 | |
| lnadal | 0:2afedb12bdfd | 3 | /* |
| lnadal | 0:2afedb12bdfd | 4 | ************************************************************************************** |
| lnadal | 0:2afedb12bdfd | 5 | AD5627. Dual 12-bit DAC with i2C interface and external reference pin. |
| lnadal | 0:2afedb12bdfd | 6 | (The AD56x7R have an internal reference). Power supply: 2.7V to 5.5V. |
| lnadal | 0:2afedb12bdfd | 7 | |
| lnadal | 0:2afedb12bdfd | 8 | If needed, the two DACs can be updated simultaneously by LDAC (pin 4)or by software. |
| lnadal | 0:2afedb12bdfd | 9 | |
| lnadal | 0:2afedb12bdfd | 10 | Wiring: |
| lnadal | 0:2afedb12bdfd | 11 | pin 3 (GND) to ground. pin 9 (Vdd) to 3.3V. |
| lnadal | 0:2afedb12bdfd | 12 | pin 10 (Vref) to 3.3V, pin 6 (ADDR) to 3.3V (A1=0, A0=0). |
| lnadal | 0:2afedb12bdfd | 13 | 4.7k pull-up resistors on pins 8 and 7 (SDA, SCL)(to mBed's pins 9 and 10). |
| lnadal | 0:2afedb12bdfd | 14 | pin 4 (LDAC) and pin 5 (CLR) to mBed's digital output pins 11 and 12. |
| lnadal | 0:2afedb12bdfd | 15 | |
| lnadal | 0:2afedb12bdfd | 16 | Attach voltmeter to ground and Vout A (pin 1) or Vout B (pin 2). |
| lnadal | 0:2afedb12bdfd | 17 | |
| lnadal | 0:2afedb12bdfd | 18 | Command byte: 0 S C2 C1 C0 A2 A1 A0. s=1: multiple block write, s=0: one block write. |
| lnadal | 0:2afedb12bdfd | 19 | |
| lnadal | 0:2afedb12bdfd | 20 | Commands C2 C1 C0: |
| lnadal | 0:2afedb12bdfd | 21 | 000: Write to input register. |
| lnadal | 0:2afedb12bdfd | 22 | 001: Update DAC register. |
| lnadal | 0:2afedb12bdfd | 23 | 010: Write to input register n, update all (software LDAC). |
| lnadal | 0:2afedb12bdfd | 24 | 011: Write and update DAC channel n. |
| lnadal | 0:2afedb12bdfd | 25 | 100: Power up / power down. |
| lnadal | 0:2afedb12bdfd | 26 | 101: Reset. |
| lnadal | 0:2afedb12bdfd | 27 | 110: LDAC register setup. |
| lnadal | 0:2afedb12bdfd | 28 | 111: Internal reference setup (on/off). |
| lnadal | 0:2afedb12bdfd | 29 | |
| lnadal | 0:2afedb12bdfd | 30 | DAC address command A2 A1 A0: |
| lnadal | 0:2afedb12bdfd | 31 | 000: DAC A. |
| lnadal | 0:2afedb12bdfd | 32 | 001: DAC B. |
| lnadal | 0:2afedb12bdfd | 33 | 111: Both DACs. |
| lnadal | 0:2afedb12bdfd | 34 | |
| lnadal | 0:2afedb12bdfd | 35 | |
| lnadal | 0:2afedb12bdfd | 36 | Author: Lluis Nadal. August 2011. |
| lnadal | 0:2afedb12bdfd | 37 | ************************************************************************************** |
| lnadal | 0:2afedb12bdfd | 38 | */ |
| lnadal | 0:2afedb12bdfd | 39 | |
| lnadal | 0:2afedb12bdfd | 40 | I2C i2c(p9, p10); // SDA, SCL |
| lnadal | 0:2afedb12bdfd | 41 | Serial pc(USBTX, USBRX); |
| lnadal | 0:2afedb12bdfd | 42 | DigitalOut LDAC (p11); |
| lnadal | 0:2afedb12bdfd | 43 | DigitalOut CLR (p12); |
| lnadal | 0:2afedb12bdfd | 44 | |
| lnadal | 0:2afedb12bdfd | 45 | DigitalOut L1(LED1); |
| lnadal | 0:2afedb12bdfd | 46 | DigitalOut L2(LED2); |
| lnadal | 0:2afedb12bdfd | 47 | DigitalOut L3(LED3); |
| lnadal | 0:2afedb12bdfd | 48 | DigitalOut L4(LED4); |
| lnadal | 0:2afedb12bdfd | 49 | |
| lnadal | 0:2afedb12bdfd | 50 | const int addr_R = 0x19; // Address to read |
| lnadal | 0:2afedb12bdfd | 51 | const int addr_W = 0x18; // Address to write |
| lnadal | 0:2afedb12bdfd | 52 | |
| lnadal | 0:2afedb12bdfd | 53 | const int CA1 = 0x18; // Command: DAC A one block write |
| lnadal | 0:2afedb12bdfd | 54 | const int CB1 = 0x19; // Command: DAC B one block write |
| lnadal | 0:2afedb12bdfd | 55 | const int CA2 = 0x58; // Command: DAC A multiple block write |
| lnadal | 0:2afedb12bdfd | 56 | const int CB2 = 0x59; // Command: DAC B multiple block write |
| lnadal | 0:2afedb12bdfd | 57 | const int CA3 = 0x00; // Command: DAC A using LDAC to update. |
| lnadal | 0:2afedb12bdfd | 58 | const int CB3 = 0x01; // Command: DAC B using LDAC to update. |
| lnadal | 0:2afedb12bdfd | 59 | |
| lnadal | 0:2afedb12bdfd | 60 | |
| lnadal | 0:2afedb12bdfd | 61 | void write_A(float v) { // 0 < v < 3.3 V |
| lnadal | 0:2afedb12bdfd | 62 | char H; // High byte |
| lnadal | 0:2afedb12bdfd | 63 | char L; // Low byte |
| lnadal | 0:2afedb12bdfd | 64 | int n; |
| lnadal | 0:2afedb12bdfd | 65 | n = (int)(v*4096/3.3); |
| lnadal | 0:2afedb12bdfd | 66 | pc.printf(" n= %d\r\n", n); |
| lnadal | 0:2afedb12bdfd | 67 | L = n<<4 & 0xF0; |
| lnadal | 0:2afedb12bdfd | 68 | H = n>>4; |
| lnadal | 0:2afedb12bdfd | 69 | pc.printf(" (H, L)=(%d, %d)\r\n", H, L); |
| lnadal | 0:2afedb12bdfd | 70 | pc.printf("\r\n"); |
| lnadal | 0:2afedb12bdfd | 71 | i2c.start(); |
| lnadal | 0:2afedb12bdfd | 72 | i2c.write(addr_W); // Write address to write |
| lnadal | 0:2afedb12bdfd | 73 | i2c.write(CA1); // Write command |
| lnadal | 0:2afedb12bdfd | 74 | i2c.write(H); // Write high byte |
| lnadal | 0:2afedb12bdfd | 75 | i2c.write(L); // Write low byte |
| lnadal | 0:2afedb12bdfd | 76 | i2c.stop(); |
| lnadal | 0:2afedb12bdfd | 77 | } |
| lnadal | 0:2afedb12bdfd | 78 | |
| lnadal | 0:2afedb12bdfd | 79 | |
| lnadal | 0:2afedb12bdfd | 80 | void write_B(float v) { // 0 < v < 3.3 V |
| lnadal | 0:2afedb12bdfd | 81 | char H; // High byte |
| lnadal | 0:2afedb12bdfd | 82 | char L; // Low byte |
| lnadal | 0:2afedb12bdfd | 83 | int n; |
| lnadal | 0:2afedb12bdfd | 84 | n = (int)(v*4096/3.3); |
| lnadal | 0:2afedb12bdfd | 85 | pc.printf(" n= %d\r\n", n); |
| lnadal | 0:2afedb12bdfd | 86 | L = n<<4 & 0xF0; |
| lnadal | 0:2afedb12bdfd | 87 | H = n>>4; |
| lnadal | 0:2afedb12bdfd | 88 | pc.printf(" (H, L)=(%d, %d)\r\n", H, L); |
| lnadal | 0:2afedb12bdfd | 89 | pc.printf("\r\n"); |
| lnadal | 0:2afedb12bdfd | 90 | i2c.start(); |
| lnadal | 0:2afedb12bdfd | 91 | i2c.write(addr_W); // Write address to write |
| lnadal | 0:2afedb12bdfd | 92 | i2c.write(CB1); // Write command |
| lnadal | 0:2afedb12bdfd | 93 | i2c.write(H); // Write high byte |
| lnadal | 0:2afedb12bdfd | 94 | i2c.write(L); // Write low byte |
| lnadal | 0:2afedb12bdfd | 95 | i2c.stop(); |
| lnadal | 0:2afedb12bdfd | 96 | } |
| lnadal | 0:2afedb12bdfd | 97 | |
| lnadal | 0:2afedb12bdfd | 98 | void write_A_LDAC(float v) { // 0 < v < 3.3 V |
| lnadal | 0:2afedb12bdfd | 99 | char H; // High byte |
| lnadal | 0:2afedb12bdfd | 100 | char L; // Low byte |
| lnadal | 0:2afedb12bdfd | 101 | int n; |
| lnadal | 0:2afedb12bdfd | 102 | n = (int)(v*4096/3.3); |
| lnadal | 0:2afedb12bdfd | 103 | pc.printf(" n= %d\r\n", n); |
| lnadal | 0:2afedb12bdfd | 104 | L = n<<4 & 0xF0; |
| lnadal | 0:2afedb12bdfd | 105 | H = n>>4; |
| lnadal | 0:2afedb12bdfd | 106 | pc.printf(" (H, L)=(%d, %d)\r\n", H, L); |
| lnadal | 0:2afedb12bdfd | 107 | pc.printf("\r\n"); |
| lnadal | 0:2afedb12bdfd | 108 | i2c.start(); |
| lnadal | 0:2afedb12bdfd | 109 | i2c.write(addr_W); // Write address to write |
| lnadal | 0:2afedb12bdfd | 110 | i2c.write(CA3); // Write command |
| lnadal | 0:2afedb12bdfd | 111 | i2c.write(H); // Write high byte |
| lnadal | 0:2afedb12bdfd | 112 | i2c.write(L); // Write low byte |
| lnadal | 0:2afedb12bdfd | 113 | i2c.stop(); |
| lnadal | 0:2afedb12bdfd | 114 | } |
| lnadal | 0:2afedb12bdfd | 115 | |
| lnadal | 0:2afedb12bdfd | 116 | void write_B_LDAC(float v) { // 0 < v < 3.3 V |
| lnadal | 0:2afedb12bdfd | 117 | char H; // High byte |
| lnadal | 0:2afedb12bdfd | 118 | char L; // Low byte |
| lnadal | 0:2afedb12bdfd | 119 | int n; |
| lnadal | 0:2afedb12bdfd | 120 | n = (int)(v*4096/3.3); |
| lnadal | 0:2afedb12bdfd | 121 | pc.printf(" n= %d\r\n", n); |
| lnadal | 0:2afedb12bdfd | 122 | L = n<<4 & 0xF0; |
| lnadal | 0:2afedb12bdfd | 123 | H = n>>4; |
| lnadal | 0:2afedb12bdfd | 124 | pc.printf(" (H, L)=(%d, %d)\r\n", H, L); |
| lnadal | 0:2afedb12bdfd | 125 | pc.printf("\r\n"); |
| lnadal | 0:2afedb12bdfd | 126 | i2c.start(); |
| lnadal | 0:2afedb12bdfd | 127 | i2c.write(addr_W); // Write address to write |
| lnadal | 0:2afedb12bdfd | 128 | i2c.write(CB3); // Write command |
| lnadal | 0:2afedb12bdfd | 129 | i2c.write(H); // Write high byte |
| lnadal | 0:2afedb12bdfd | 130 | i2c.write(L); // Write low byte |
| lnadal | 0:2afedb12bdfd | 131 | i2c.stop(); |
| lnadal | 0:2afedb12bdfd | 132 | } |
| lnadal | 0:2afedb12bdfd | 133 | |
| lnadal | 0:2afedb12bdfd | 134 | |
| lnadal | 0:2afedb12bdfd | 135 | int main() { |
| lnadal | 0:2afedb12bdfd | 136 | L1 = 0; |
| lnadal | 0:2afedb12bdfd | 137 | i2c.frequency(100000); |
| lnadal | 0:2afedb12bdfd | 138 | |
| lnadal | 0:2afedb12bdfd | 139 | // Pulsing this pin low allows any or all DAC registers to be updated if they have new data. |
| lnadal | 0:2afedb12bdfd | 140 | LDAC = 0; |
| lnadal | 0:2afedb12bdfd | 141 | |
| lnadal | 0:2afedb12bdfd | 142 | CLR = 0; // Outputs the two DACs to 0V. |
| lnadal | 0:2afedb12bdfd | 143 | wait(5); |
| lnadal | 0:2afedb12bdfd | 144 | CLR = 1; |
| lnadal | 0:2afedb12bdfd | 145 | L1 = 1; |
| lnadal | 0:2afedb12bdfd | 146 | |
| lnadal | 0:2afedb12bdfd | 147 | // DAC A one block write |
| lnadal | 0:2afedb12bdfd | 148 | write_A(2.537); |
| lnadal | 0:2afedb12bdfd | 149 | wait(5); |
| lnadal | 0:2afedb12bdfd | 150 | |
| lnadal | 0:2afedb12bdfd | 151 | // DAC A one block write |
| lnadal | 0:2afedb12bdfd | 152 | write_A(1.777); |
| lnadal | 0:2afedb12bdfd | 153 | L2 = 1; |
| lnadal | 0:2afedb12bdfd | 154 | wait(5); |
| lnadal | 0:2afedb12bdfd | 155 | |
| lnadal | 0:2afedb12bdfd | 156 | // DAC B one block write |
| lnadal | 0:2afedb12bdfd | 157 | write_B(0.666); |
| lnadal | 0:2afedb12bdfd | 158 | wait(5); |
| lnadal | 0:2afedb12bdfd | 159 | |
| lnadal | 0:2afedb12bdfd | 160 | // DAC B one block write |
| lnadal | 0:2afedb12bdfd | 161 | write_B(3.000); |
| lnadal | 0:2afedb12bdfd | 162 | wait(5); |
| lnadal | 0:2afedb12bdfd | 163 | |
| lnadal | 0:2afedb12bdfd | 164 | |
| lnadal | 0:2afedb12bdfd | 165 | // Using LDAC pin |
| lnadal | 0:2afedb12bdfd | 166 | LDAC = 1; |
| lnadal | 0:2afedb12bdfd | 167 | write_A_LDAC(1.000); // DAC register A is not updated |
| lnadal | 0:2afedb12bdfd | 168 | write_B_LDAC(1.500); // DAC register B is not updated |
| lnadal | 0:2afedb12bdfd | 169 | L3 = 1; |
| lnadal | 0:2afedb12bdfd | 170 | wait(5); |
| lnadal | 0:2afedb12bdfd | 171 | |
| lnadal | 0:2afedb12bdfd | 172 | LDAC = 0; // DAC registers A and B are updated simultaneously |
| lnadal | 0:2afedb12bdfd | 173 | L4 = 1; |
| lnadal | 0:2afedb12bdfd | 174 | |
| lnadal | 0:2afedb12bdfd | 175 | } |