Jeroen Hilgers / MRF24J40

This library lets you connect an MRF24J40 tranceiver to your mbed. The MRF24J40 is intended for use as a zigbee tranceiver. However, it can also be used to simply send data from one tranceiver to another. The tranceiver is also available as a module on a small PCB with antenna etc. It requires no other components and can be connected to the mbed using 5 pins.

Dependents:   mrf24jclient_vest1

MRF24J40.cpp@1:55d2672c4708, 2011-02-16 (annotated)

Committer:
hilgo
Date:
Wed Feb 16 07:53:48 2011 +0000
Revision:
1:55d2672c4708
Parent:
0:0630ffe718d3 
Fixed @code tag in documentation.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hilgo 0:0630ffe718d3 1 /* mbed MRF24J40 (IEEE 802.15.4 tranceiver) Library
hilgo 0:0630ffe718d3 2 * Copyright (c) 2011 Jeroen Hilgers
hilgo 0:0630ffe718d3 3 *
hilgo 0:0630ffe718d3 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
hilgo 0:0630ffe718d3 5 * of this software and associated documentation files (the "Software"), to deal
hilgo 0:0630ffe718d3 6 * in the Software without restriction, including without limitation the rights
hilgo 0:0630ffe718d3 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
hilgo 0:0630ffe718d3 8 * copies of the Software, and to permit persons to whom the Software is
hilgo 0:0630ffe718d3 9 * furnished to do so, subject to the following conditions:
hilgo 0:0630ffe718d3 10 *
hilgo 0:0630ffe718d3 11 * The above copyright notice and this permission notice shall be included in
hilgo 0:0630ffe718d3 12 * all copies or substantial portions of the Software.
hilgo 0:0630ffe718d3 13 *
hilgo 0:0630ffe718d3 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
hilgo 0:0630ffe718d3 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
hilgo 0:0630ffe718d3 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
hilgo 0:0630ffe718d3 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
hilgo 0:0630ffe718d3 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
hilgo 0:0630ffe718d3 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
hilgo 0:0630ffe718d3 20 * THE SOFTWARE.
hilgo 0:0630ffe718d3 21 */
hilgo 0:0630ffe718d3 22
hilgo 0:0630ffe718d3 23 #include "MRF24J40.h"
hilgo 0:0630ffe718d3 24
hilgo 0:0630ffe718d3 25 // MRF20J40 Short address control register mapping.
hilgo 0:0630ffe718d3 26 #define RXMCR 0x00
hilgo 0:0630ffe718d3 27 #define PANIDL 0x01
hilgo 0:0630ffe718d3 28 #define PANIDH 0x02
hilgo 0:0630ffe718d3 29 #define SADRL 0x03
hilgo 0:0630ffe718d3 30 #define SADRH 0x04
hilgo 0:0630ffe718d3 31 #define EADR0 0x05
hilgo 0:0630ffe718d3 32 #define EADR1 0x06
hilgo 0:0630ffe718d3 33 #define EADR2 0x07
hilgo 0:0630ffe718d3 34 #define EADR3 0x08
hilgo 0:0630ffe718d3 35 #define EADR4 0x09
hilgo 0:0630ffe718d3 36 #define EADR5 0x0a
hilgo 0:0630ffe718d3 37 #define EADR6 0x0b
hilgo 0:0630ffe718d3 38 #define EADR7 0x0c
hilgo 0:0630ffe718d3 39 #define RXFLUSH 0x0d
hilgo 0:0630ffe718d3 40
hilgo 0:0630ffe718d3 41 #define TXNMTRIG 0x1b
hilgo 0:0630ffe718d3 42 #define TXSR 0x24
hilgo 0:0630ffe718d3 43
hilgo 0:0630ffe718d3 44 #define ISRSTS 0x31
hilgo 0:0630ffe718d3 45 #define INTMSK 0x32
hilgo 0:0630ffe718d3 46 #define GPIO 0x33
hilgo 0:0630ffe718d3 47 #define TRISGPIO 0x34
hilgo 0:0630ffe718d3 48
hilgo 0:0630ffe718d3 49 #define RFCTL 0x36
hilgo 0:0630ffe718d3 50
hilgo 0:0630ffe718d3 51 #define BBREG2 0x3A
hilgo 0:0630ffe718d3 52
hilgo 0:0630ffe718d3 53 #define BBREG6 0x3E
hilgo 0:0630ffe718d3 54 #define RSSITHCCA 0x3F
hilgo 0:0630ffe718d3 55
hilgo 0:0630ffe718d3 56 // MRF20J40 Long address control register mapping.
hilgo 0:0630ffe718d3 57 #define RFCTRL0 0x200
hilgo 0:0630ffe718d3 58
hilgo 0:0630ffe718d3 59 #define RFCTRL2 0x202
hilgo 0:0630ffe718d3 60 #define RFCTRL3 0x203
hilgo 0:0630ffe718d3 61
hilgo 0:0630ffe718d3 62 #define RFCTRL6 0x206
hilgo 0:0630ffe718d3 63 #define RFCTRL7 0x207
hilgo 0:0630ffe718d3 64 #define RFCTRL8 0x208
hilgo 0:0630ffe718d3 65
hilgo 0:0630ffe718d3 66 #define CLKINTCR 0x211
hilgo 0:0630ffe718d3 67 #define CLCCTRL 0x220
hilgo 0:0630ffe718d3 68
hilgo 0:0630ffe718d3 69 MRF24J40::MRF24J40(PinName mosi, PinName miso, PinName sck, PinName cs, PinName reset) ://, PinName irq, PinName wake) :
hilgo 0:0630ffe718d3 70 mSpi(mosi, miso, sck), // mosi, miso, sclk
hilgo 0:0630ffe718d3 71 mCs(cs),
hilgo 0:0630ffe718d3 72 mReset(reset)
hilgo 0:0630ffe718d3 73 // mIrq(irq),
hilgo 0:0630ffe718d3 74 // mWake(wake)
hilgo 0:0630ffe718d3 75 {
hilgo 0:0630ffe718d3 76 mSpi.format(8, 0); // 8 bits, cpol=0; cpha=0
hilgo 0:0630ffe718d3 77 mSpi.frequency(500000);
hilgo 0:0630ffe718d3 78 Reset();
hilgo 0:0630ffe718d3 79 }
hilgo 0:0630ffe718d3 80
hilgo 0:0630ffe718d3 81 /*
hilgo 0:0630ffe718d3 82 void MRF24J40::DebugDump(Serial &ser)
hilgo 0:0630ffe718d3 83 {
hilgo 0:0630ffe718d3 84 ser.printf("MRF24J40 registers:\r");
hilgo 0:0630ffe718d3 85 ser.printf("RXMCR=0x%X\r", MrfReadShort(RXMCR));
hilgo 0:0630ffe718d3 86 ser.printf("RXFLUSH=0x%X\r", MrfReadShort(RXFLUSH));
hilgo 0:0630ffe718d3 87 ser.printf("TXNMTRIG=0x%X\r", MrfReadShort(TXNMTRIG));
hilgo 0:0630ffe718d3 88 ser.printf("TXSR=0x%X\r", MrfReadShort(TXSR));
hilgo 0:0630ffe718d3 89 ser.printf("ISRSTS=0x%X\r", MrfReadShort(ISRSTS));
hilgo 0:0630ffe718d3 90 ser.printf("INTMSK=0x%X\r", MrfReadShort(INTMSK));
hilgo 0:0630ffe718d3 91 ser.printf("GPIO=0x%X\r", MrfReadShort(GPIO));
hilgo 0:0630ffe718d3 92 ser.printf("TRISGPIO=0x%X\r", MrfReadShort(TRISGPIO));
hilgo 0:0630ffe718d3 93 ser.printf("RFCTL=0x%X\r", MrfReadShort(RFCTL));
hilgo 0:0630ffe718d3 94 ser.printf("BBREG2=0x%X\r", MrfReadShort(BBREG2));
hilgo 0:0630ffe718d3 95 ser.printf("BBREG6=0x%X\r", MrfReadShort(BBREG6));
hilgo 0:0630ffe718d3 96 ser.printf("RSSITHCCA=0x%X\r", MrfReadShort(RSSITHCCA));
hilgo 0:0630ffe718d3 97
hilgo 0:0630ffe718d3 98
hilgo 0:0630ffe718d3 99 ser.printf("RFCTRL0=0x%X\r", MrfReadLong(RFCTRL0));
hilgo 0:0630ffe718d3 100 ser.printf("RFCTRL2=0x%X\r", MrfReadLong(RFCTRL2));
hilgo 0:0630ffe718d3 101 ser.printf("RFCTRL3=0x%X\r", MrfReadLong(RFCTRL3));
hilgo 0:0630ffe718d3 102 ser.printf("RFCTRL6=0x%X\r", MrfReadLong(RFCTRL6));
hilgo 0:0630ffe718d3 103 ser.printf("RFCTRL7=0x%X\r", MrfReadLong(RFCTRL7));
hilgo 0:0630ffe718d3 104 ser.printf("RFCTRL8=0x%X\r", MrfReadLong(RFCTRL8));
hilgo 0:0630ffe718d3 105 ser.printf("CLKINTCR=0x%X\r", MrfReadLong(CLKINTCR));
hilgo 0:0630ffe718d3 106 ser.printf("CLCCTRL=0x%X\r", MrfReadLong(CLCCTRL));
hilgo 0:0630ffe718d3 107 ser.printf("\r");
hilgo 0:0630ffe718d3 108 }
hilgo 0:0630ffe718d3 109 */
hilgo 0:0630ffe718d3 110
hilgo 0:0630ffe718d3 111 void MRF24J40::Reset(void)
hilgo 0:0630ffe718d3 112 {
hilgo 0:0630ffe718d3 113 mCs = 1;
hilgo 0:0630ffe718d3 114 // Pulse hardware reset.
hilgo 0:0630ffe718d3 115 mReset = 0;
hilgo 0:0630ffe718d3 116 wait_us(100);
hilgo 0:0630ffe718d3 117 mReset = 1;
hilgo 0:0630ffe718d3 118 wait_us(100);
hilgo 0:0630ffe718d3 119
hilgo 0:0630ffe718d3 120 // Reset RF module.
hilgo 0:0630ffe718d3 121 WriteShort(RFCTL, 0x04);
hilgo 0:0630ffe718d3 122 WriteShort(RFCTL, 0x00);
hilgo 0:0630ffe718d3 123
hilgo 0:0630ffe718d3 124 WriteShort(RFCTL, 0x00);
hilgo 0:0630ffe718d3 125
hilgo 0:0630ffe718d3 126 WriteShort(PANIDL, 0xAA);
hilgo 0:0630ffe718d3 127 WriteShort(PANIDH, 0xAA);
hilgo 0:0630ffe718d3 128 WriteShort(SADRL, 0xAA);
hilgo 0:0630ffe718d3 129 WriteShort(SADRH, 0xAA);
hilgo 0:0630ffe718d3 130
hilgo 0:0630ffe718d3 131 // Flush RX fifo.
hilgo 0:0630ffe718d3 132 WriteShort(RXFLUSH, 0x01);
hilgo 0:0630ffe718d3 133
hilgo 0:0630ffe718d3 134 // Write MAC addresses here. We don't care.
hilgo 0:0630ffe718d3 135
hilgo 0:0630ffe718d3 136 WriteLong(RFCTRL2, 0x80); // Enable RF PLL.
hilgo 0:0630ffe718d3 137
hilgo 0:0630ffe718d3 138 WriteLong(RFCTRL3, 0x00); // Full power.
hilgo 0:0630ffe718d3 139 WriteLong(RFCTRL6, 0x80); // Enable TX filter (recommended)
hilgo 0:0630ffe718d3 140 WriteLong(RFCTRL8, 0x10); // Enhanced VCO (recommended)
hilgo 0:0630ffe718d3 141
hilgo 0:0630ffe718d3 142 WriteShort(BBREG2,0x78); // Clear Channel Assesment use carrier sense.
hilgo 0:0630ffe718d3 143 WriteShort(BBREG6,0x40); // Calculate RSSI for Rx packet.
hilgo 0:0630ffe718d3 144 WriteShort(RSSITHCCA,0x00);// RSSI threshold for CCA.
hilgo 0:0630ffe718d3 145
hilgo 0:0630ffe718d3 146 WriteLong(RFCTRL0, 0x00); // Channel 11.
hilgo 0:0630ffe718d3 147
hilgo 0:0630ffe718d3 148 WriteShort(RXMCR, 0x01); // Don't check address upon reception.
hilgo 0:0630ffe718d3 149 // MrfWriteShort(RXMCR, 0x00); // Check address upon reception.
hilgo 0:0630ffe718d3 150
hilgo 0:0630ffe718d3 151 // Reset RF module with new settings.
hilgo 0:0630ffe718d3 152 WriteShort(RFCTL, 0x04);
hilgo 0:0630ffe718d3 153 WriteShort(RFCTL, 0x00);
hilgo 0:0630ffe718d3 154 }
hilgo 0:0630ffe718d3 155
hilgo 0:0630ffe718d3 156 void MRF24J40::Send(uint8_t *data, uint8_t length)
hilgo 0:0630ffe718d3 157 {
hilgo 0:0630ffe718d3 158 uint8_t i;
hilgo 0:0630ffe718d3 159
hilgo 0:0630ffe718d3 160 WriteLong(0x000, 0); // No addresses in header.
hilgo 0:0630ffe718d3 161 WriteLong(0x001, length); // 11 bytes
hilgo 0:0630ffe718d3 162 for(i=0; i<length; i++)
hilgo 0:0630ffe718d3 163 WriteLong(0x002+i, data[i]);
hilgo 0:0630ffe718d3 164
hilgo 0:0630ffe718d3 165 WriteShort(TXNMTRIG, 0x01);
hilgo 0:0630ffe718d3 166 }
hilgo 0:0630ffe718d3 167
hilgo 0:0630ffe718d3 168 uint8_t MRF24J40::Receive(uint8_t *data, uint8_t maxLength)
hilgo 0:0630ffe718d3 169 {
hilgo 0:0630ffe718d3 170 uint8_t i, length;
hilgo 0:0630ffe718d3 171 uint8_t lqi, rssi;
hilgo 0:0630ffe718d3 172
hilgo 0:0630ffe718d3 173 if(ReadShort(ISRSTS)& 0x08)
hilgo 0:0630ffe718d3 174 {
hilgo 0:0630ffe718d3 175 length = ReadLong(0x300);
hilgo 0:0630ffe718d3 176 lqi = ReadLong(0x301 + length);
hilgo 0:0630ffe718d3 177 rssi = ReadLong(0x302 + length);
hilgo 0:0630ffe718d3 178 for(i=0; i<length; i++)
hilgo 0:0630ffe718d3 179 if(i<maxLength)
hilgo 0:0630ffe718d3 180 *data++ = ReadLong(0x301 + (uint16_t)i);
hilgo 0:0630ffe718d3 181 else
hilgo 0:0630ffe718d3 182 ReadLong(0x301 + (uint16_t)i);
hilgo 0:0630ffe718d3 183 if(length < maxLength)
hilgo 0:0630ffe718d3 184 return length;
hilgo 0:0630ffe718d3 185 }
hilgo 0:0630ffe718d3 186 return 0;
hilgo 0:0630ffe718d3 187 }
hilgo 0:0630ffe718d3 188
hilgo 0:0630ffe718d3 189 uint8_t MRF24J40::ReadShort (uint8_t address)
hilgo 0:0630ffe718d3 190 {
hilgo 0:0630ffe718d3 191 uint8_t value;
hilgo 0:0630ffe718d3 192 mCs = 0;
hilgo 0:0630ffe718d3 193 wait_us(1);
hilgo 0:0630ffe718d3 194 mSpi.write((address<<1) & 0x7E);
hilgo 0:0630ffe718d3 195 wait_us(1);
hilgo 0:0630ffe718d3 196 value = mSpi.write(0xFF);
hilgo 0:0630ffe718d3 197 wait_us(1);
hilgo 0:0630ffe718d3 198 mCs = 1;
hilgo 0:0630ffe718d3 199 wait_us(1);
hilgo 0:0630ffe718d3 200 return value;
hilgo 0:0630ffe718d3 201 }
hilgo 0:0630ffe718d3 202
hilgo 0:0630ffe718d3 203 void MRF24J40::WriteShort (uint8_t address, uint8_t data)
hilgo 0:0630ffe718d3 204 {
hilgo 0:0630ffe718d3 205 mCs = 0;
hilgo 0:0630ffe718d3 206 wait_us(1);
hilgo 0:0630ffe718d3 207 mSpi.write(((address<<1) & 0x7E) | 0x01);
hilgo 0:0630ffe718d3 208 wait_us(1);
hilgo 0:0630ffe718d3 209 mSpi.write(data);
hilgo 0:0630ffe718d3 210 wait_us(1);
hilgo 0:0630ffe718d3 211 mCs = 1;
hilgo 0:0630ffe718d3 212 wait_us(1);
hilgo 0:0630ffe718d3 213 }
hilgo 0:0630ffe718d3 214
hilgo 0:0630ffe718d3 215 uint8_t MRF24J40::ReadLong (uint16_t address)
hilgo 0:0630ffe718d3 216 {
hilgo 0:0630ffe718d3 217 uint8_t value;
hilgo 0:0630ffe718d3 218 mCs = 0;
hilgo 0:0630ffe718d3 219 wait_us(1);
hilgo 0:0630ffe718d3 220 mSpi.write((address>>3) | 0x80);
hilgo 0:0630ffe718d3 221 wait_us(1);
hilgo 0:0630ffe718d3 222 mSpi.write((address<<5) & 0xE0);
hilgo 0:0630ffe718d3 223 wait_us(1);
hilgo 0:0630ffe718d3 224 value = mSpi.write(0xFF);
hilgo 0:0630ffe718d3 225 wait_us(1);
hilgo 0:0630ffe718d3 226 mCs = 1;
hilgo 0:0630ffe718d3 227 wait_us(1);
hilgo 0:0630ffe718d3 228 return value;
hilgo 0:0630ffe718d3 229 }
hilgo 0:0630ffe718d3 230
hilgo 0:0630ffe718d3 231 void MRF24J40::WriteLong (uint16_t address, uint8_t data)
hilgo 0:0630ffe718d3 232 {
hilgo 0:0630ffe718d3 233 mCs = 0;
hilgo 0:0630ffe718d3 234 wait_us(1);
hilgo 0:0630ffe718d3 235 mSpi.write((address>>3) | 0x80);
hilgo 0:0630ffe718d3 236 wait_us(1);
hilgo 0:0630ffe718d3 237 mSpi.write(((address<<5) & 0xE0) | 0x10);
hilgo 0:0630ffe718d3 238 wait_us(1);
hilgo 0:0630ffe718d3 239 mSpi.write(data);
hilgo 0:0630ffe718d3 240 wait_us(1);
hilgo 0:0630ffe718d3 241 mCs = 1;
hilgo 0:0630ffe718d3 242 wait_us(1);
hilgo 0:0630ffe718d3 243 }