Retro Invaders a space invaders clone by Chris Favreau. Written for the RetroMbuino development board from outrageouscircuits.com for the game programming contest.

Dependencies:   mbed

This is a space invaders clone written for the Retro Mbuino from outrageous circuits.

Development board: http://www.outrageouscircuits.com/shop/product/15 ).

The game itself is basic space invaders. Shoot them before they get to the bottom of the screen. It has a UFO saucer which you can shoot for extra points. You get 4 shields and each shield can be hit up to 4 times before it is gone. Hmm... as each level increases the speed of the invaders shots goes up. The invaders only speed up when there is less of them. You complete the level when you shoot all the invaders. The game ends when a) you run out of lives (you start with 3) or the invaders get to the bottom.

The LEDs turned out to be a pretty cool addition to the game. I wrote a class that blinks them and turns them on for a specified amount of time. They add a nice extra to the game. I use them on the intro screen and when the UFO is present.

The sound turned out to be really difficult for a few reasons. The biggest was that I had never written a sound engine before. The interrupt service routine working off the timer was the easier part. I also had a lot of trouble because there is no filter to filter out the PWM frequency to the speaker... so I had to run the PWM frequency way up there 30 kHz.

The graphics turned out to be a bit of a bear too. Thanks to Chris Taylor for his really great LCD API. I picked up a couple of frames per second from that. I had modified the DisplayN18 class for blitting a single line buffer to the LCD panel however his is a little faster for some reason? I used a different approach to doing the graphics (as I have very little experience with anything other than double buffered displays). I have a tile map and a list of sprites. Each tile/sprite is 1 bit 8x8. They could be bigger. I ran out of time. That much is not special. What is different from what I can tell is that I use a 1 line buffer that is 160 shorts long. The render function first adds the tile map data into the line buffer first. Then the sprites are added over the existing data. You can have a great deal of different sprites and maps going to the screen and just have to rewrite the LCD memory once per frame. After each line is composited, the line is then drawn to the LCD. Kind of like an Atari 2600. Each sprite/tile has a foreground and background color and can be different from the other tiles/sprites. There is one color reserved for Transparency.

There are 16 colors to choose from. I chose a palette based on the Macintosh OS 4.1 palette I found on WikiPedia. It is a very nice mix of colors.

I found a sprite editor called SpriteX ( https://code.google.com/p/spritesx-ed/ )... it works nicely except that the 16x16 sprites are in a weird format. Time limited me to 8x8 sprites. Oh well.

I used nokring to make the music. It makes RTTTL formatted ring tones which my sound api can play. Here is a useful site that has lots of arcade/video game ring tones with a link to nokring in the utilities page. http://arcadetones.emuunlim.com/files.htm

Other than all that stuff I used state machines to do most of the game logic. Please excuse the horrible coding as I tried to comment a lot of it however it is not very nice to look at. Lots of long functions...

Committer:
cfavreau
Date:
Tue Mar 03 04:26:01 2015 +0000
Revision:
0:c79e1f29f029
Retro Invaders by Chris Favreau for the RetroMbuino Platform - outrageouscircuits.com game programming contest.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
cfavreau 0:c79e1f29f029 1 // lpc111x.h
cfavreau 0:c79e1f29f029 2 // LPC low level all-in-one header file for lpc111x devices
cfavreau 0:c79e1f29f029 3 // principally targeted at lpc1114fn28 (DIP28 package)
cfavreau 0:c79e1f29f029 4 // Written by Frank Duignan
cfavreau 0:c79e1f29f029 5 // Latest version available at http://eleceng.dit.ie/frank/arm/cortex/lpc111x.h
cfavreau 0:c79e1f29f029 6 // Derived from UM10398 user manual from NXP semiconductors
cfavreau 0:c79e1f29f029 7 // Naming convention: Register names are as described in UM10398
cfavreau 0:c79e1f29f029 8 // No claims are made for the suitability, accuracy or otherwise of this file
cfavreau 0:c79e1f29f029 9 // for any application
cfavreau 0:c79e1f29f029 10 // Define some bitmasks
cfavreau 0:c79e1f29f029 11 #define BIT0 (1 << 0)
cfavreau 0:c79e1f29f029 12 #define BIT1 (1 << 1)
cfavreau 0:c79e1f29f029 13 #define BIT2 (1 << 2)
cfavreau 0:c79e1f29f029 14 #define BIT3 (1 << 3)
cfavreau 0:c79e1f29f029 15 #define BIT4 (1 << 4)
cfavreau 0:c79e1f29f029 16 #define BIT5 (1 << 5)
cfavreau 0:c79e1f29f029 17 #define BIT6 (1 << 6)
cfavreau 0:c79e1f29f029 18 #define BIT7 (1 << 7)
cfavreau 0:c79e1f29f029 19 #define BIT8 (1 << 8)
cfavreau 0:c79e1f29f029 20 #define BIT9 (1 << 9)
cfavreau 0:c79e1f29f029 21 #define BIT10 (1 << 10)
cfavreau 0:c79e1f29f029 22 #define BIT11 (1 << 11)
cfavreau 0:c79e1f29f029 23 #define BIT12 (1 << 12)
cfavreau 0:c79e1f29f029 24 #define BIT13 (1 << 13)
cfavreau 0:c79e1f29f029 25 #define BIT14 (1 << 14)
cfavreau 0:c79e1f29f029 26 #define BIT15 (1 << 15)
cfavreau 0:c79e1f29f029 27 #define BIT16 (1 << 16)
cfavreau 0:c79e1f29f029 28 #define BIT17 (1 << 17)
cfavreau 0:c79e1f29f029 29 #define BIT18 (1 << 18)
cfavreau 0:c79e1f29f029 30 #define BIT19 (1 << 19)
cfavreau 0:c79e1f29f029 31 #define BIT20 (1 << 20)
cfavreau 0:c79e1f29f029 32 #define BIT21 (1 << 21)
cfavreau 0:c79e1f29f029 33 #define BIT22 (1 << 22)
cfavreau 0:c79e1f29f029 34 #define BIT23 (1 << 23)
cfavreau 0:c79e1f29f029 35 #define BIT24 (1 << 24)
cfavreau 0:c79e1f29f029 36 #define BIT25 (1 << 25)
cfavreau 0:c79e1f29f029 37 #define BIT26 (1 << 26)
cfavreau 0:c79e1f29f029 38 #define BIT27 (1 << 27)
cfavreau 0:c79e1f29f029 39 #define BIT28 (1 << 28)
cfavreau 0:c79e1f29f029 40 #define BIT29 (1 << 29)
cfavreau 0:c79e1f29f029 41 #define BIT30 (1 << 30)
cfavreau 0:c79e1f29f029 42 #define BIT31 (1 << 31)
cfavreau 0:c79e1f29f029 43
cfavreau 0:c79e1f29f029 44 // Macros to reduce typing later on
cfavreau 0:c79e1f29f029 45 #define REGISTER_32(ADDRESS) (*((volatile unsigned int *)(ADDRESS)))
cfavreau 0:c79e1f29f029 46 #define REGISTER_16(ADDRESS) (*((volatile unsigned int *)(ADDRESS)))
cfavreau 0:c79e1f29f029 47 // Macros to enable/disable global interrupts
cfavreau 0:c79e1f29f029 48 #define enable_interrupts() asm(" cpsie i ")
cfavreau 0:c79e1f29f029 49 #define disable_interrupts() asm(" cpsid i ")
cfavreau 0:c79e1f29f029 50
cfavreau 0:c79e1f29f029 51 // APB Peripherals
cfavreau 0:c79e1f29f029 52 #define I2C_BASE 0x40000000
cfavreau 0:c79e1f29f029 53 #define WDT_BASE 0x40004000
cfavreau 0:c79e1f29f029 54 #define UART_BASE 0x40008000
cfavreau 0:c79e1f29f029 55 #define TMR16B0_BASE 0x4000c000
cfavreau 0:c79e1f29f029 56 #define TMR16B1_BASE 0x40010000
cfavreau 0:c79e1f29f029 57 #define TMR32B0_BASE 0x40014000
cfavreau 0:c79e1f29f029 58 #define TMR32B1_BASE 0x40018000
cfavreau 0:c79e1f29f029 59 #define ADC_BASE 0x4001c000
cfavreau 0:c79e1f29f029 60 #define PMU_BASE 0x40038000
cfavreau 0:c79e1f29f029 61 #define FLASH_CTRL_BASE 0x4003c000
cfavreau 0:c79e1f29f029 62 #define SSP0_BASE 0x40040000
cfavreau 0:c79e1f29f029 63 #define IOCONFIG_BASE 0x40044000
cfavreau 0:c79e1f29f029 64 #define SYSCON_BASE 0x40048000
cfavreau 0:c79e1f29f029 65 #define C_CAN_BASE 0x40050000
cfavreau 0:c79e1f29f029 66 #define SSP1_BASE 0x40058000
cfavreau 0:c79e1f29f029 67
cfavreau 0:c79e1f29f029 68 // I2C
cfavreau 0:c79e1f29f029 69 #define I2C0CONSET REGISTER_32(I2C_BASE + 0x000)
cfavreau 0:c79e1f29f029 70 #define I2C0STAT REGISTER_32(I2C_BASE + 0x004)
cfavreau 0:c79e1f29f029 71 #define I2C0DAT REGISTER_32(I2C_BASE + 0x008)
cfavreau 0:c79e1f29f029 72 #define I2C0ADR0 REGISTER_32(I2C_BASE + 0x00c)
cfavreau 0:c79e1f29f029 73 #define I2C0SCLH REGISTER_32(I2C_BASE + 0x010)
cfavreau 0:c79e1f29f029 74 #define I2C0SCLL REGISTER_32(I2C_BASE + 0x014)
cfavreau 0:c79e1f29f029 75 #define I2C0CONCLR REGISTER_32(I2C_BASE + 0x018)
cfavreau 0:c79e1f29f029 76 #define I2C0COMMCTRL REGISTER_32(I2C_BASE + 0x01c)
cfavreau 0:c79e1f29f029 77 #define I2C0ADR1 REGISTER_32(I2C_BASE + 0x020)
cfavreau 0:c79e1f29f029 78 #define I2C0ADR2 REGISTER_32(I2C_BASE + 0x024)
cfavreau 0:c79e1f29f029 79 #define I2C0ADR3 REGISTER_32(I2C_BASE + 0x028)
cfavreau 0:c79e1f29f029 80 #define I2C0DATA_BUFFER REGISTER_32(I2C_BASE + 0x02c)
cfavreau 0:c79e1f29f029 81 #define I2C0MASK0 REGISTER_32(I2C_BASE + 0x030)
cfavreau 0:c79e1f29f029 82 #define I2C0MASK1 REGISTER_32(I2C_BASE + 0x034)
cfavreau 0:c79e1f29f029 83 #define I2C0MASK2 REGISTER_32(I2C_BASE + 0x038)
cfavreau 0:c79e1f29f029 84 #define I2C0MASK3 REGISTER_32(I2C_BASE + 0x03c)
cfavreau 0:c79e1f29f029 85 // WDT
cfavreau 0:c79e1f29f029 86 #define WDMOD REGISTER_32(WDT_BASE + 0x000)
cfavreau 0:c79e1f29f029 87 #define WDTC REGISTER_32(WDT_BASE + 0x004)
cfavreau 0:c79e1f29f029 88 #define WDFEED REGISTER_32(WDT_BASE + 0x008)
cfavreau 0:c79e1f29f029 89 #define WDTV REGISTER_32(WDT_BASE + 0x00c)
cfavreau 0:c79e1f29f029 90 #define WDWARNINT REGISTER_32(WDT_BASE + 0x014)
cfavreau 0:c79e1f29f029 91 #define WDWINDOW REGISTER_32(WDT_BASE + 0x018)
cfavreau 0:c79e1f29f029 92
cfavreau 0:c79e1f29f029 93 // UART
cfavreau 0:c79e1f29f029 94 // registers appear to share addresses here. Depending
cfavreau 0:c79e1f29f029 95 // on the state of DLAB different registers are active.
cfavreau 0:c79e1f29f029 96 // Also some registers are read-only, some write-only
cfavreau 0:c79e1f29f029 97 #define U0RBR REGISTER_32(UART_BASE + 0x000)
cfavreau 0:c79e1f29f029 98 #define U0THR REGISTER_32(UART_BASE + 0x000)
cfavreau 0:c79e1f29f029 99 #define U0DLL REGISTER_32(UART_BASE + 0x000)
cfavreau 0:c79e1f29f029 100 #define U0DLM REGISTER_32(UART_BASE + 0x004)
cfavreau 0:c79e1f29f029 101 #define U0IER REGISTER_32(UART_BASE + 0x004)
cfavreau 0:c79e1f29f029 102 #define U0IIR REGISTER_32(UART_BASE + 0x008)
cfavreau 0:c79e1f29f029 103 #define U0FCR REGISTER_32(UART_BASE + 0x008)
cfavreau 0:c79e1f29f029 104 #define U0LCR REGISTER_32(UART_BASE + 0x00c)
cfavreau 0:c79e1f29f029 105 #define U0MCR REGISTER_32(UART_BASE + 0x010)
cfavreau 0:c79e1f29f029 106 #define U0LSR REGISTER_32(UART_BASE + 0x014)
cfavreau 0:c79e1f29f029 107 #define U0MSR REGISTER_32(UART_BASE + 0x018)
cfavreau 0:c79e1f29f029 108 #define U0SCR REGISTER_32(UART_BASE + 0x01c)
cfavreau 0:c79e1f29f029 109 #define U0ACR REGISTER_32(UART_BASE + 0x020)
cfavreau 0:c79e1f29f029 110 #define U0FDR REGISTER_32(UART_BASE + 0x028)
cfavreau 0:c79e1f29f029 111 #define U0TER REGISTER_32(UART_BASE + 0x030)
cfavreau 0:c79e1f29f029 112 #define U0RS485CTRL REGISTER_32(UART_BASE + 0x04c)
cfavreau 0:c79e1f29f029 113 #define U0RS485ADRMATCH REGISTER_32(UART_BASE + 0x050)
cfavreau 0:c79e1f29f029 114 #define U0RS485DLY REGISTER_32(UART_BASE + 0x054)
cfavreau 0:c79e1f29f029 115
cfavreau 0:c79e1f29f029 116
cfavreau 0:c79e1f29f029 117
cfavreau 0:c79e1f29f029 118 // TMR16B0
cfavreau 0:c79e1f29f029 119 #define TMR16B0IR REGISTER_32(TMR16B0_BASE + 0x000)
cfavreau 0:c79e1f29f029 120 #define TMR16B0TCR REGISTER_32(TMR16B0_BASE + 0x004)
cfavreau 0:c79e1f29f029 121 #define TMR16B0TC REGISTER_32(TMR16B0_BASE + 0x008)
cfavreau 0:c79e1f29f029 122 #define TMR16B0PR REGISTER_32(TMR16B0_BASE + 0x00c)
cfavreau 0:c79e1f29f029 123 #define TMR16B0PC REGISTER_32(TMR16B0_BASE + 0x010)
cfavreau 0:c79e1f29f029 124 #define TMR16B0MCR REGISTER_32(TMR16B0_BASE + 0x014)
cfavreau 0:c79e1f29f029 125 #define TMR16B0MR0 REGISTER_32(TMR16B0_BASE + 0x018)
cfavreau 0:c79e1f29f029 126 #define TMR16B0MR1 REGISTER_32(TMR16B0_BASE + 0x01c)
cfavreau 0:c79e1f29f029 127 #define TMR16B0MR2 REGISTER_32(TMR16B0_BASE + 0x020)
cfavreau 0:c79e1f29f029 128 #define TMR16B0MR3 REGISTER_32(TMR16B0_BASE + 0x024)
cfavreau 0:c79e1f29f029 129 #define TMR16B0CCR REGISTER_32(TMR16B0_BASE + 0x028)
cfavreau 0:c79e1f29f029 130 #define TMR16B0CR0 REGISTER_32(TMR16B0_BASE + 0x02c)
cfavreau 0:c79e1f29f029 131 #define TMR16B0CR1 REGISTER_32(TMR16B0_BASE + 0x030)
cfavreau 0:c79e1f29f029 132 #define TMR16B0EMR REGISTER_32(TMR16B0_BASE + 0x03c)
cfavreau 0:c79e1f29f029 133 #define TMR16B0CTCR REGISTER_32(TMR16B0_BASE + 0x070)
cfavreau 0:c79e1f29f029 134 #define TMR16B0PWMC REGISTER_32(TMR16B0_BASE + 0x074)
cfavreau 0:c79e1f29f029 135 // TMR16B1
cfavreau 0:c79e1f29f029 136 #define TMR16B1IR REGISTER_32(TMR16B1_BASE + 0x000)
cfavreau 0:c79e1f29f029 137 #define TMR16B1TCR REGISTER_32(TMR16B1_BASE + 0x004)
cfavreau 0:c79e1f29f029 138 #define TMR16B1TC REGISTER_32(TMR16B1_BASE + 0x008)
cfavreau 0:c79e1f29f029 139 #define TMR16B1PR REGISTER_32(TMR16B1_BASE + 0x00c)
cfavreau 0:c79e1f29f029 140 #define TMR16B1PC REGISTER_32(TMR16B1_BASE + 0x010)
cfavreau 0:c79e1f29f029 141 #define TMR16B1MCR REGISTER_32(TMR16B1_BASE + 0x014)
cfavreau 0:c79e1f29f029 142 #define TMR16B1MR0 REGISTER_32(TMR16B1_BASE + 0x018)
cfavreau 0:c79e1f29f029 143 #define TMR16B1MR1 REGISTER_32(TMR16B1_BASE + 0x01c)
cfavreau 0:c79e1f29f029 144 #define TMR16B1MR2 REGISTER_32(TMR16B1_BASE + 0x020)
cfavreau 0:c79e1f29f029 145 #define TMR16B1MR3 REGISTER_32(TMR16B1_BASE + 0x024)
cfavreau 0:c79e1f29f029 146 #define TMR16B1CCR REGISTER_32(TMR16B1_BASE + 0x028)
cfavreau 0:c79e1f29f029 147 #define TMR16B1CR0 REGISTER_32(TMR16B1_BASE + 0x02c)
cfavreau 0:c79e1f29f029 148 #define TMR16B1CR1 REGISTER_32(TMR16B1_BASE + 0x030)
cfavreau 0:c79e1f29f029 149 #define TMR16B1EMR REGISTER_32(TMR16B1_BASE + 0x03c)
cfavreau 0:c79e1f29f029 150 #define TMR16B1CTCR REGISTER_32(TMR16B1_BASE + 0x070)
cfavreau 0:c79e1f29f029 151 #define TMR16B1PWMC REGISTER_32(TMR16B1_BASE + 0x074)
cfavreau 0:c79e1f29f029 152
cfavreau 0:c79e1f29f029 153
cfavreau 0:c79e1f29f029 154
cfavreau 0:c79e1f29f029 155 // TMR32B0
cfavreau 0:c79e1f29f029 156 #define TMR32B0IR REGISTER_32(TMR32B0_BASE + 0x000)
cfavreau 0:c79e1f29f029 157 #define TMR32B0TCR REGISTER_32(TMR32B0_BASE + 0x004)
cfavreau 0:c79e1f29f029 158 #define TMR32B0TC REGISTER_32(TMR32B0_BASE + 0x008)
cfavreau 0:c79e1f29f029 159 #define TMR32B0PR REGISTER_32(TMR32B0_BASE + 0x00c)
cfavreau 0:c79e1f29f029 160 #define TMR32B0PC REGISTER_32(TMR32B0_BASE + 0x010)
cfavreau 0:c79e1f29f029 161 #define TMR32B0MCR REGISTER_32(TMR32B0_BASE + 0x014)
cfavreau 0:c79e1f29f029 162 #define TMR32B0MR0 REGISTER_32(TMR32B0_BASE + 0x018)
cfavreau 0:c79e1f29f029 163 #define TMR32B0MR1 REGISTER_32(TMR32B0_BASE + 0x01c)
cfavreau 0:c79e1f29f029 164 #define TMR32B0MR2 REGISTER_32(TMR32B0_BASE + 0x020)
cfavreau 0:c79e1f29f029 165 #define TMR32B0MR3 REGISTER_32(TMR32B0_BASE + 0x024)
cfavreau 0:c79e1f29f029 166 #define TMR32B0CCR REGISTER_32(TMR32B0_BASE + 0x028)
cfavreau 0:c79e1f29f029 167 #define TMR32B0CR0 REGISTER_32(TMR32B0_BASE + 0x02c)
cfavreau 0:c79e1f29f029 168 #define TMR32B0CR1 REGISTER_32(TMR32B0_BASE + 0x030)
cfavreau 0:c79e1f29f029 169 #define TMR32B0EMR REGISTER_32(TMR32B0_BASE + 0x03c)
cfavreau 0:c79e1f29f029 170 #define TMR32B0CTCR REGISTER_32(TMR32B0_BASE + 0x070)
cfavreau 0:c79e1f29f029 171 #define TMR32B0PWMC REGISTER_32(TMR32B0_BASE + 0x074)
cfavreau 0:c79e1f29f029 172 // TMR32B1
cfavreau 0:c79e1f29f029 173 #define TMR32B1IR REGISTER_32(TMR32B1_BASE + 0x000)
cfavreau 0:c79e1f29f029 174 #define TMR32B1TCR REGISTER_32(TMR32B1_BASE + 0x004)
cfavreau 0:c79e1f29f029 175 #define TMR32B1TC REGISTER_32(TMR32B1_BASE + 0x008)
cfavreau 0:c79e1f29f029 176 #define TMR32B1PR REGISTER_32(TMR32B1_BASE + 0x00c)
cfavreau 0:c79e1f29f029 177 #define TMR32B1PC REGISTER_32(TMR32B1_BASE + 0x010)
cfavreau 0:c79e1f29f029 178 #define TMR32B1MCR REGISTER_32(TMR32B1_BASE + 0x014)
cfavreau 0:c79e1f29f029 179 #define TMR32B1MR0 REGISTER_32(TMR32B1_BASE + 0x018)
cfavreau 0:c79e1f29f029 180 #define TMR32B1MR1 REGISTER_32(TMR32B1_BASE + 0x01c)
cfavreau 0:c79e1f29f029 181 #define TMR32B1MR2 REGISTER_32(TMR32B1_BASE + 0x020)
cfavreau 0:c79e1f29f029 182 #define TMR32B1MR3 REGISTER_32(TMR32B1_BASE + 0x024)
cfavreau 0:c79e1f29f029 183 #define TMR32B1CCR REGISTER_32(TMR32B1_BASE + 0x028)
cfavreau 0:c79e1f29f029 184 #define TMR32B1CR0 REGISTER_32(TMR32B1_BASE + 0x02c)
cfavreau 0:c79e1f29f029 185 #define TMR32B1CR1 REGISTER_32(TMR32B1_BASE + 0x030)
cfavreau 0:c79e1f29f029 186 #define TMR32B1EMR REGISTER_32(TMR32B1_BASE + 0x03c)
cfavreau 0:c79e1f29f029 187 #define TMR32B1CTCR REGISTER_32(TMR32B1_BASE + 0x070)
cfavreau 0:c79e1f29f029 188 #define TMR32B1PWMC REGISTER_32(TMR32B1_BASE + 0x074)
cfavreau 0:c79e1f29f029 189
cfavreau 0:c79e1f29f029 190
cfavreau 0:c79e1f29f029 191
cfavreau 0:c79e1f29f029 192 // ADC
cfavreau 0:c79e1f29f029 193 #define AD0CR REGISTER_32(ADC_BASE + 0x000)
cfavreau 0:c79e1f29f029 194 #define AD0GDR REGISTER_32(ADC_BASE + 0x004)
cfavreau 0:c79e1f29f029 195 #define AD0INTEN REGISTER_32(ADC_BASE + 0x00c)
cfavreau 0:c79e1f29f029 196 #define AD0DR0 REGISTER_32(ADC_BASE + 0x010)
cfavreau 0:c79e1f29f029 197 #define AD0DR1 REGISTER_32(ADC_BASE + 0x014)
cfavreau 0:c79e1f29f029 198 #define AD0DR2 REGISTER_32(ADC_BASE + 0x018)
cfavreau 0:c79e1f29f029 199 #define AD0DR3 REGISTER_32(ADC_BASE + 0x01c)
cfavreau 0:c79e1f29f029 200 #define AD0DR4 REGISTER_32(ADC_BASE + 0x020)
cfavreau 0:c79e1f29f029 201 #define AD0DR5 REGISTER_32(ADC_BASE + 0x024)
cfavreau 0:c79e1f29f029 202 #define AD0DR6 REGISTER_32(ADC_BASE + 0x028)
cfavreau 0:c79e1f29f029 203 #define AD0DR7 REGISTER_32(ADC_BASE + 0x02c)
cfavreau 0:c79e1f29f029 204 #define AD0STAT REGISTER_32(ADC_BASE + 0x030)
cfavreau 0:c79e1f29f029 205
cfavreau 0:c79e1f29f029 206 // PMU
cfavreau 0:c79e1f29f029 207 #define PCON REGISTER_32(PMU_BASE + 0x000)
cfavreau 0:c79e1f29f029 208 #define GPREG0 REGISTER_32(PMU_BASE + 0x004)
cfavreau 0:c79e1f29f029 209 #define GPREG1 REGISTER_32(PMU_BASE + 0x008)
cfavreau 0:c79e1f29f029 210 #define GPREG2 REGISTER_32(PMU_BASE + 0x00c)
cfavreau 0:c79e1f29f029 211 #define GPREG3 REGISTER_32(PMU_BASE + 0x010)
cfavreau 0:c79e1f29f029 212 #define GPREG4 REGISTER_32(PMU_BASE + 0x014)
cfavreau 0:c79e1f29f029 213
cfavreau 0:c79e1f29f029 214 // FLASH CONTROLLER
cfavreau 0:c79e1f29f029 215 #define FLASHCFG REGISTER_32(FLASH_CTRL_BASE + 0x010)
cfavreau 0:c79e1f29f029 216 #define FMSSTART REGISTER_32(FLASH_CTRL_BASE + 0x020)
cfavreau 0:c79e1f29f029 217 #define FMSSTOP REGISTER_32(FLASH_CTRL_BASE + 0x024)
cfavreau 0:c79e1f29f029 218 #define FMSW0 REGISTER_32(FLASH_CTRL_BASE + 0x02c)
cfavreau 0:c79e1f29f029 219 #define FMSW1 REGISTER_32(FLASH_CTRL_BASE + 0x030)
cfavreau 0:c79e1f29f029 220 #define FMSW2 REGISTER_32(FLASH_CTRL_BASE + 0x034)
cfavreau 0:c79e1f29f029 221 #define FMSW3 REGISTER_32(FLASH_CTRL_BASE + 0x038)
cfavreau 0:c79e1f29f029 222 #define FMSTAT REGISTER_32(FLASH_CTRL_BASE + 0xfe0)
cfavreau 0:c79e1f29f029 223 #define FMSTATCLR REGISTER_32(FLASH_CTRL_BASE + 0xfe8)
cfavreau 0:c79e1f29f029 224 // IOCONFIG
cfavreau 0:c79e1f29f029 225 #define IOCON_PIO2_6 REGISTER_32(IOCONFIG_BASE + 0x000)
cfavreau 0:c79e1f29f029 226 #define IOCON_PIO2_0 REGISTER_32(IOCONFIG_BASE + 0x008)
cfavreau 0:c79e1f29f029 227 #define IOCON_RESET_PIO0_0 REGISTER_32(IOCONFIG_BASE + 0x00c)
cfavreau 0:c79e1f29f029 228 #define IOCON_PIO0_1 REGISTER_32(IOCONFIG_BASE + 0x010)
cfavreau 0:c79e1f29f029 229 #define IOCON_PIO1_8 REGISTER_32(IOCONFIG_BASE + 0x014)
cfavreau 0:c79e1f29f029 230 #define IOCON_SSEL1_LOC REGISTER_32(IOCONFIG_BASE + 0x018)
cfavreau 0:c79e1f29f029 231 #define IOCON_PIO0_2 REGISTER_32(IOCONFIG_BASE + 0x01c)
cfavreau 0:c79e1f29f029 232 #define IOCON_PIO2_7 REGISTER_32(IOCONFIG_BASE + 0x020)
cfavreau 0:c79e1f29f029 233 #define IOCON_PIO2_8 REGISTER_32(IOCONFIG_BASE + 0x024)
cfavreau 0:c79e1f29f029 234 #define IOCON_PIO2_1 REGISTER_32(IOCONFIG_BASE + 0x028)
cfavreau 0:c79e1f29f029 235 #define IOCON_PIO0_3 REGISTER_32(IOCONFIG_BASE + 0x02c)
cfavreau 0:c79e1f29f029 236 #define IOCON_PIO0_4 REGISTER_32(IOCONFIG_BASE + 0x030)
cfavreau 0:c79e1f29f029 237 #define IOCON_PIO0_5 REGISTER_32(IOCONFIG_BASE + 0x034)
cfavreau 0:c79e1f29f029 238 #define IOCON_PIO1_9 REGISTER_32(IOCONFIG_BASE + 0x038)
cfavreau 0:c79e1f29f029 239 #define IOCON_PIO3_4 REGISTER_32(IOCONFIG_BASE + 0x03c)
cfavreau 0:c79e1f29f029 240 #define IOCON_PIO2_4 REGISTER_32(IOCONFIG_BASE + 0x040)
cfavreau 0:c79e1f29f029 241 #define IOCON_PIO2_5 REGISTER_32(IOCONFIG_BASE + 0x044)
cfavreau 0:c79e1f29f029 242 #define IOCON_PIO3_5 REGISTER_32(IOCONFIG_BASE + 0x048)
cfavreau 0:c79e1f29f029 243 #define IOCON_PIO0_6 REGISTER_32(IOCONFIG_BASE + 0x04c)
cfavreau 0:c79e1f29f029 244 #define IOCON_PIO0_7 REGISTER_32(IOCONFIG_BASE + 0x050)
cfavreau 0:c79e1f29f029 245 #define IOCON_PIO2_9 REGISTER_32(IOCONFIG_BASE + 0x054)
cfavreau 0:c79e1f29f029 246 #define IOCON_PIO2_10 REGISTER_32(IOCONFIG_BASE + 0x058)
cfavreau 0:c79e1f29f029 247 #define IOCON_PIO2_2 REGISTER_32(IOCONFIG_BASE + 0x05c)
cfavreau 0:c79e1f29f029 248 #define IOCON_PIO0_8 REGISTER_32(IOCONFIG_BASE + 0x060)
cfavreau 0:c79e1f29f029 249 #define IOCON_PIO0_9 REGISTER_32(IOCONFIG_BASE + 0x064)
cfavreau 0:c79e1f29f029 250 #define IOCON_PIO0_18 REGISTER_32(IOCONFIG_BASE + 0x048)
cfavreau 0:c79e1f29f029 251 #define IOCON_SWCLK_PIO0_10 REGISTER_32(IOCONFIG_BASE + 0x068)
cfavreau 0:c79e1f29f029 252 #define IOCON_PIO1_10 REGISTER_32(IOCONFIG_BASE + 0x06c)
cfavreau 0:c79e1f29f029 253 #define IOCON_PIO2_11 REGISTER_32(IOCONFIG_BASE + 0x070)
cfavreau 0:c79e1f29f029 254 #define IOCON_R_PIO0_11 REGISTER_32(IOCONFIG_BASE + 0x074)
cfavreau 0:c79e1f29f029 255 #define IOCON_R_PIO1_0 REGISTER_32(IOCONFIG_BASE + 0x078)
cfavreau 0:c79e1f29f029 256 #define IOCON_R_PIO1_1 REGISTER_32(IOCONFIG_BASE + 0x07c)
cfavreau 0:c79e1f29f029 257 #define IOCON_R_PIO1_2 REGISTER_32(IOCONFIG_BASE + 0x080)
cfavreau 0:c79e1f29f029 258 #define IOCON_PIO3_0 REGISTER_32(IOCONFIG_BASE + 0x084)
cfavreau 0:c79e1f29f029 259 #define IOCON_PIO3_1 REGISTER_32(IOCONFIG_BASE + 0x088)
cfavreau 0:c79e1f29f029 260 #define IOCON_PIO2_3 REGISTER_32(IOCONFIG_BASE + 0x08c)
cfavreau 0:c79e1f29f029 261 #define IOCON_SWDIO_PIO1_3 REGISTER_32(IOCONFIG_BASE + 0x090)
cfavreau 0:c79e1f29f029 262 #define IOCON_PIO1_4 REGISTER_32(IOCONFIG_BASE + 0x094)
cfavreau 0:c79e1f29f029 263 #define IOCON_PIO1_11 REGISTER_32(IOCONFIG_BASE + 0x098)
cfavreau 0:c79e1f29f029 264 #define IOCON_PIO3_2 REGISTER_32(IOCONFIG_BASE + 0x09c)
cfavreau 0:c79e1f29f029 265 #define IOCON_PIO1_5 REGISTER_32(IOCONFIG_BASE + 0x0a0)
cfavreau 0:c79e1f29f029 266 #define IOCON_PIO1_6 REGISTER_32(IOCONFIG_BASE + 0x0a4)
cfavreau 0:c79e1f29f029 267 #define IOCON_PIO1_7 REGISTER_32(IOCONFIG_BASE + 0x0a8)
cfavreau 0:c79e1f29f029 268 #define IOCON_PIO3_3 REGISTER_32(IOCONFIG_BASE + 0x0ac)
cfavreau 0:c79e1f29f029 269 #define IOCON_SCK0_LOC REGISTER_32(IOCONFIG_BASE + 0x0b0)
cfavreau 0:c79e1f29f029 270 #define IOCON_DSR_LOC REGISTER_32(IOCONFIG_BASE + 0x0b4)
cfavreau 0:c79e1f29f029 271 #define IOCON_DCD_LOC REGISTER_32(IOCONFIG_BASE + 0x0b8)
cfavreau 0:c79e1f29f029 272 #define IOCON_RI_LOC REGISTER_32(IOCONFIG_BASE + 0x0bc)
cfavreau 0:c79e1f29f029 273 #define IOCON_CT16B0_CAP0_LOC REGISTER_32(IOCONFIG_BASE + 0x0c0)
cfavreau 0:c79e1f29f029 274 #define IOCON_SCK1_LOC REGISTER_32(IOCONFIG_BASE + 0x0c4)
cfavreau 0:c79e1f29f029 275 #define IOCON_MISO1_LOC REGISTER_32(IOCONFIG_BASE + 0x0c8)
cfavreau 0:c79e1f29f029 276 #define IOCON_MOSI1_LOC REGISTER_32(IOCONFIG_BASE + 0x0cc)
cfavreau 0:c79e1f29f029 277 #define IOCON_CT32B0_CAP0_LOC REGISTER_32(IOCONFIG_BASE + 0x0d0)
cfavreau 0:c79e1f29f029 278 #define IOCON_RXD_LOC REGISTER_32(IOCONFIG_BASE + 0x0d4)
cfavreau 0:c79e1f29f029 279
cfavreau 0:c79e1f29f029 280
cfavreau 0:c79e1f29f029 281
cfavreau 0:c79e1f29f029 282
cfavreau 0:c79e1f29f029 283
cfavreau 0:c79e1f29f029 284 // SYSCON
cfavreau 0:c79e1f29f029 285 #define SYSMEMREMAP REGISTER_32(SYSCON_BASE + 0x000)
cfavreau 0:c79e1f29f029 286 #define PRESETCTRL REGISTER_32(SYSCON_BASE + 0x004)
cfavreau 0:c79e1f29f029 287 #define SYSPLLCTRL REGISTER_32(SYSCON_BASE + 0x008)
cfavreau 0:c79e1f29f029 288 #define SYSPLLSTAT REGISTER_32(SYSCON_BASE + 0x00c)
cfavreau 0:c79e1f29f029 289 #define SYSOSCCTRL REGISTER_32(SYSCON_BASE + 0x020)
cfavreau 0:c79e1f29f029 290 #define WDTOSCCTRL REGISTER_32(SYSCON_BASE + 0x024)
cfavreau 0:c79e1f29f029 291 #define IRCCTL REGISTER_32(SYSCON_BASE + 0x028)
cfavreau 0:c79e1f29f029 292 #define SYSRSTSTAT REGISTER_32(SYSCON_BASE + 0x030)
cfavreau 0:c79e1f29f029 293 #define SYSPLLCLKSEL REGISTER_32(SYSCON_BASE + 0x040)
cfavreau 0:c79e1f29f029 294 #define SYSPLLCLKUEN REGISTER_32(SYSCON_BASE + 0x044)
cfavreau 0:c79e1f29f029 295 #define MAINCLKSEL REGISTER_32(SYSCON_BASE + 0x070)
cfavreau 0:c79e1f29f029 296 #define MAINCLKUEN REGISTER_32(SYSCON_BASE + 0x074)
cfavreau 0:c79e1f29f029 297 #define SYSAHBCLKDIV REGISTER_32(SYSCON_BASE + 0x078)
cfavreau 0:c79e1f29f029 298 #define SYSAHBCLKCTRL REGISTER_32(SYSCON_BASE + 0x080)
cfavreau 0:c79e1f29f029 299 #define SSP0CLKDIV REGISTER_32(SYSCON_BASE + 0x094)
cfavreau 0:c79e1f29f029 300 #define UARTCLKDIV REGISTER_32(SYSCON_BASE + 0x098)
cfavreau 0:c79e1f29f029 301 #define SSP1CLKDIV REGISTER_32(SYSCON_BASE + 0x09c)
cfavreau 0:c79e1f29f029 302 #define WDTCLKSEL REGISTER_32(SYSCON_BASE + 0x0d0)
cfavreau 0:c79e1f29f029 303 #define WDTCLKUEN REGISTER_32(SYSCON_BASE + 0x0d4)
cfavreau 0:c79e1f29f029 304 #define WDTCLKDIV REGISTER_32(SYSCON_BASE + 0x0d8)
cfavreau 0:c79e1f29f029 305 #define CLKOUTCLKSEL REGISTER_32(SYSCON_BASE + 0x0e0)
cfavreau 0:c79e1f29f029 306 #define CLKOUTUEN REGISTER_32(SYSCON_BASE + 0x0e4)
cfavreau 0:c79e1f29f029 307 #define CLKOUTCLKDIV REGISTER_32(SYSCON_BASE + 0x0e8)
cfavreau 0:c79e1f29f029 308 #define PIOPORCAP0 REGISTER_32(SYSCON_BASE + 0x100)
cfavreau 0:c79e1f29f029 309 #define PIOPORCAP1 REGISTER_32(SYSCON_BASE + 0x104)
cfavreau 0:c79e1f29f029 310 #define BODCTRL REGISTER_32(SYSCON_BASE + 0x150)
cfavreau 0:c79e1f29f029 311 #define SYSTCKCAL REGISTER_32(SYSCON_BASE + 0x154)
cfavreau 0:c79e1f29f029 312 #define NMISRC REGISTER_32(SYSCON_BASE + 0x174)
cfavreau 0:c79e1f29f029 313 #define STARTAPRP0 REGISTER_32(SYSCON_BASE + 0x200)
cfavreau 0:c79e1f29f029 314 #define STARTERP0 REGISTER_32(SYSCON_BASE + 0x204)
cfavreau 0:c79e1f29f029 315 #define STARTRSRP0CLR REGISTER_32(SYSCON_BASE + 0x208)
cfavreau 0:c79e1f29f029 316 #define STARTSRP0 REGISTER_32(SYSCON_BASE + 0x20c)
cfavreau 0:c79e1f29f029 317 #define PDSLEEPCFG REGISTER_32(SYSCON_BASE + 0x230)
cfavreau 0:c79e1f29f029 318 #define PDAWAKECFG REGISTER_32(SYSCON_BASE + 0x234)
cfavreau 0:c79e1f29f029 319 #define PDRUNCFG REGISTER_32(SYSCON_BASE + 0x238)
cfavreau 0:c79e1f29f029 320 #define DEVICE_ID REGISTER_32(SYSCON_BASE + 0x3f4)
cfavreau 0:c79e1f29f029 321
cfavreau 0:c79e1f29f029 322
cfavreau 0:c79e1f29f029 323 // CAN
cfavreau 0:c79e1f29f029 324 #define CANCNTL REGISTER_32(C_CAN_BASE + 0x000)
cfavreau 0:c79e1f29f029 325 #define CANSTAT REGISTER_32(C_CAN_BASE + 0x004)
cfavreau 0:c79e1f29f029 326 #define CANEC REGISTER_32(C_CAN_BASE + 0x008)
cfavreau 0:c79e1f29f029 327 #define CANBT REGISTER_32(C_CAN_BASE + 0x00c)
cfavreau 0:c79e1f29f029 328 #define CANINT REGISTER_32(C_CAN_BASE + 0x010)
cfavreau 0:c79e1f29f029 329 #define CANTEST REGISTER_32(C_CAN_BASE + 0x014)
cfavreau 0:c79e1f29f029 330 #define CANBRPE REGISTER_32(C_CAN_BASE + 0x018)
cfavreau 0:c79e1f29f029 331 #define CANIF1_CMDREQ REGISTER_32(C_CAN_BASE + 0x020)
cfavreau 0:c79e1f29f029 332 #define CANIF1_CMDMSK_W REGISTER_32(C_CAN_BASE + 0x024)
cfavreau 0:c79e1f29f029 333 #define CANIF1_CMDMSK_R REGISTER_32(C_CAN_BASE + 0x024)
cfavreau 0:c79e1f29f029 334 #define CANIF1_MSK1 REGISTER_32(C_CAN_BASE + 0x028)
cfavreau 0:c79e1f29f029 335 #define CANIF1_MSK2 REGISTER_32(C_CAN_BASE + 0x02c)
cfavreau 0:c79e1f29f029 336 #define CANIF1_ARB1 REGISTER_32(C_CAN_BASE + 0x030)
cfavreau 0:c79e1f29f029 337 #define CANIF1_ARB2 REGISTER_32(C_CAN_BASE + 0x034)
cfavreau 0:c79e1f29f029 338 #define CANIF1_MCTRL REGISTER_32(C_CAN_BASE + 0x038)
cfavreau 0:c79e1f29f029 339 #define CANIF1_DA1 REGISTER_32(C_CAN_BASE + 0x03c)
cfavreau 0:c79e1f29f029 340 #define CANIF1_DA2 REGISTER_32(C_CAN_BASE + 0x040)
cfavreau 0:c79e1f29f029 341 #define CANIF1_DB1 REGISTER_32(C_CAN_BASE + 0x044)
cfavreau 0:c79e1f29f029 342 #define CANIF1_DB2 REGISTER_32(C_CAN_BASE + 0x048)
cfavreau 0:c79e1f29f029 343 #define CANIF2_CMDREQ REGISTER_32(C_CAN_BASE + 0x080)
cfavreau 0:c79e1f29f029 344 #define CANIF2_CMDMSK_W REGISTER_32(C_CAN_BASE + 0x084)
cfavreau 0:c79e1f29f029 345 #define CANIF2_CMDMSK_R REGISTER_32(C_CAN_BASE + 0x084)
cfavreau 0:c79e1f29f029 346 #define CANIF2_MSK1 REGISTER_32(C_CAN_BASE + 0x088)
cfavreau 0:c79e1f29f029 347 #define CANIF2_MSK2 REGISTER_32(C_CAN_BASE + 0x08c)
cfavreau 0:c79e1f29f029 348 #define CANIF2_ARB1 REGISTER_32(C_CAN_BASE + 0x090)
cfavreau 0:c79e1f29f029 349 #define CANIF2_ARB2 REGISTER_32(C_CAN_BASE + 0x094)
cfavreau 0:c79e1f29f029 350 #define CANIF2_MCTRL REGISTER_32(C_CAN_BASE + 0x098)
cfavreau 0:c79e1f29f029 351 #define CANIF2_DA1 REGISTER_32(C_CAN_BASE + 0x09c)
cfavreau 0:c79e1f29f029 352 #define CANIF2_DA2 REGISTER_32(C_CAN_BASE + 0x0a0)
cfavreau 0:c79e1f29f029 353 #define CANIF2_DB1 REGISTER_32(C_CAN_BASE + 0x0a4)
cfavreau 0:c79e1f29f029 354 #define CANIF2_DB2 REGISTER_32(C_CAN_BASE + 0x0a8)
cfavreau 0:c79e1f29f029 355 #define CANTXREQ1 REGISTER_32(C_CAN_BASE + 0x100)
cfavreau 0:c79e1f29f029 356 #define CANTXREQ2 REGISTER_32(C_CAN_BASE + 0x104)
cfavreau 0:c79e1f29f029 357 #define CANND1 REGISTER_32(C_CAN_BASE + 0x120)
cfavreau 0:c79e1f29f029 358 #define CANND2 REGISTER_32(C_CAN_BASE + 0x124)
cfavreau 0:c79e1f29f029 359 #define CANIR1 REGISTER_32(C_CAN_BASE + 0x140)
cfavreau 0:c79e1f29f029 360 #define CANIR2 REGISTER_32(C_CAN_BASE + 0x144)
cfavreau 0:c79e1f29f029 361 #define CANMSGV1 REGISTER_32(C_CAN_BASE + 0x160)
cfavreau 0:c79e1f29f029 362 #define CANNSGV2 REGISTER_32(C_CAN_BASE + 0x164)
cfavreau 0:c79e1f29f029 363 #define CANCLKDIV REGISTER_32(C_CAN_BASE + 0x180)
cfavreau 0:c79e1f29f029 364
cfavreau 0:c79e1f29f029 365
cfavreau 0:c79e1f29f029 366 // SSP0
cfavreau 0:c79e1f29f029 367 #define SSP0CR0 REGISTER_32(SSP0_BASE + 0x000)
cfavreau 0:c79e1f29f029 368 #define SSP0CR1 REGISTER_32(SSP0_BASE + 0x004)
cfavreau 0:c79e1f29f029 369 #define SSP0DR REGISTER_32(SSP0_BASE + 0x008)
cfavreau 0:c79e1f29f029 370 #define SSP0SR REGISTER_32(SSP0_BASE + 0x00c)
cfavreau 0:c79e1f29f029 371 #define SSP0CPSR REGISTER_32(SSP0_BASE + 0x010)
cfavreau 0:c79e1f29f029 372 #define SSP0IMSC REGISTER_32(SSP0_BASE + 0x014)
cfavreau 0:c79e1f29f029 373 #define SSP0RIS REGISTER_32(SSP0_BASE + 0x018)
cfavreau 0:c79e1f29f029 374 #define SSP0MIS REGISTER_32(SSP0_BASE + 0x01c)
cfavreau 0:c79e1f29f029 375 #define SSP0ICR REGISTER_32(SSP0_BASE + 0x020)
cfavreau 0:c79e1f29f029 376
cfavreau 0:c79e1f29f029 377 // SSP1
cfavreau 0:c79e1f29f029 378 #define SSP1CR0 REGISTER_32(SSP1_BASE + 0x000)
cfavreau 0:c79e1f29f029 379 #define SSP1CR1 REGISTER_32(SSP1_BASE + 0x004)
cfavreau 0:c79e1f29f029 380 #define SSP1DR REGISTER_32(SSP1_BASE + 0x008)
cfavreau 0:c79e1f29f029 381 #define SSP1SR REGISTER_32(SSP1_BASE + 0x00c)
cfavreau 0:c79e1f29f029 382 #define SSP1CPSR REGISTER_32(SSP1_BASE + 0x010)
cfavreau 0:c79e1f29f029 383 #define SSP1IMSC REGISTER_32(SSP1_BASE + 0x014)
cfavreau 0:c79e1f29f029 384 #define SSP1RIS REGISTER_32(SSP1_BASE + 0x018)
cfavreau 0:c79e1f29f029 385 #define SSP1MIS REGISTER_32(SSP1_BASE + 0x01c)
cfavreau 0:c79e1f29f029 386 #define SSP1ICR REGISTER_32(SSP1_BASE + 0x020)
cfavreau 0:c79e1f29f029 387
cfavreau 0:c79e1f29f029 388 // AHB Peripherals
cfavreau 0:c79e1f29f029 389 #define GPIO0_BASE 0x50000000
cfavreau 0:c79e1f29f029 390 #define GPIO1_BASE 0x50010000
cfavreau 0:c79e1f29f029 391 #define GPIO2_BASE 0x50020000
cfavreau 0:c79e1f29f029 392 #define GPIO3_BASE 0x50030000
cfavreau 0:c79e1f29f029 393
cfavreau 0:c79e1f29f029 394 // not dealing with mask registers here
cfavreau 0:c79e1f29f029 395 #define GPIO0DATA REGISTER_32(GPIO0_BASE + 0x3ffc)
cfavreau 0:c79e1f29f029 396 #define GPIO0DIR REGISTER_32(GPIO0_BASE + 0x8000)
cfavreau 0:c79e1f29f029 397 #define GPIO0IS REGISTER_32(GPIO0_BASE + 0x8004)
cfavreau 0:c79e1f29f029 398 #define GPIO0IBE REGISTER_32(GPIO0_BASE + 0x8008)
cfavreau 0:c79e1f29f029 399 #define GPIO0IEV REGISTER_32(GPIO0_BASE + 0x800c)
cfavreau 0:c79e1f29f029 400 #define GPIO0IE REGISTER_32(GPIO0_BASE + 0x8010)
cfavreau 0:c79e1f29f029 401 #define GPIO0RIS REGISTER_32(GPIO0_BASE + 0x8014)
cfavreau 0:c79e1f29f029 402 #define GPIO0MIS REGISTER_32(GPIO0_BASE + 0x8018)
cfavreau 0:c79e1f29f029 403 #define GPIO0IC REGISTER_32(GPIO0_BASE + 0x801c)
cfavreau 0:c79e1f29f029 404
cfavreau 0:c79e1f29f029 405 // not dealing with mask registers here
cfavreau 0:c79e1f29f029 406 #define GPIO1DATA REGISTER_32(GPIO1_BASE + 0x3ffc)
cfavreau 0:c79e1f29f029 407 #define GPIO1DIR REGISTER_32(GPIO1_BASE + 0x8000)
cfavreau 0:c79e1f29f029 408 #define GPIO1IS REGISTER_32(GPIO1_BASE + 0x8004)
cfavreau 0:c79e1f29f029 409 #define GPIO1IBE REGISTER_32(GPIO1_BASE + 0x8008)
cfavreau 0:c79e1f29f029 410 #define GPIO1IEV REGISTER_32(GPIO1_BASE + 0x800c)
cfavreau 0:c79e1f29f029 411 #define GPIO1IE REGISTER_32(GPIO1_BASE + 0x8010)
cfavreau 0:c79e1f29f029 412 #define GPIO1RIS REGISTER_32(GPIO1_BASE + 0x8014)
cfavreau 0:c79e1f29f029 413 #define GPIO1MIS REGISTER_32(GPIO1_BASE + 0x8018)
cfavreau 0:c79e1f29f029 414 #define GPIO1IC REGISTER_32(GPIO1_BASE + 0x801c)
cfavreau 0:c79e1f29f029 415
cfavreau 0:c79e1f29f029 416 // not dealing with mask registers here
cfavreau 0:c79e1f29f029 417 #define GPIO2DATA REGISTER_32(GPIO2_BASE + 0x3ffc)
cfavreau 0:c79e1f29f029 418 #define GPIO2DIR REGISTER_32(GPIO2_BASE + 0x8000)
cfavreau 0:c79e1f29f029 419 #define GPIO2IS REGISTER_32(GPIO2_BASE + 0x8004)
cfavreau 0:c79e1f29f029 420 #define GPIO2IBE REGISTER_32(GPIO2_BASE + 0x8008)
cfavreau 0:c79e1f29f029 421 #define GPIO2IEV REGISTER_32(GPIO2_BASE + 0x800c)
cfavreau 0:c79e1f29f029 422 #define GPIO2IE REGISTER_32(GPIO2_BASE + 0x8010)
cfavreau 0:c79e1f29f029 423 #define GPIO2RIS REGISTER_32(GPIO2_BASE + 0x8014)
cfavreau 0:c79e1f29f029 424 #define GPIO2MIS REGISTER_32(GPIO2_BASE + 0x8018)
cfavreau 0:c79e1f29f029 425 #define GPIO2IC REGISTER_32(GPIO2_BASE + 0x801c)
cfavreau 0:c79e1f29f029 426
cfavreau 0:c79e1f29f029 427 // Core peripherals
cfavreau 0:c79e1f29f029 428 #define STK_BASE 0xe000e010
cfavreau 0:c79e1f29f029 429 #define SCB_BASE 0xe000ed00
cfavreau 0:c79e1f29f029 430 #define NVIC_BASE 0xe000e100
cfavreau 0:c79e1f29f029 431 // Seems base addresses are split for some core peripherals
cfavreau 0:c79e1f29f029 432 #define SCB_BASE2 0xe000e008
cfavreau 0:c79e1f29f029 433 #define NVIC_BASE2 0xe000ef00
cfavreau 0:c79e1f29f029 434
cfavreau 0:c79e1f29f029 435 // NVIC
cfavreau 0:c79e1f29f029 436 #define ISER REGISTER_32(NVIC_BASE + 0)
cfavreau 0:c79e1f29f029 437 #define ICER REGISTER_32(NVIC_BASE + 0x80)
cfavreau 0:c79e1f29f029 438 #define ISPR REGISTER_32(NVIC_BASE + 0x100)
cfavreau 0:c79e1f29f029 439 #define ICPR REGISTER_32(NVIC_BASE + 0x180)
cfavreau 0:c79e1f29f029 440 #define IPR0 REGISTER_32(NVIC_BASE + 0x300)
cfavreau 0:c79e1f29f029 441 #define IPR1 REGISTER_32(NVIC_BASE + 0x304)
cfavreau 0:c79e1f29f029 442 #define IPR2 REGISTER_32(NVIC_BASE + 0x308)
cfavreau 0:c79e1f29f029 443 #define IPR3 REGISTER_32(NVIC_BASE + 0x30c)
cfavreau 0:c79e1f29f029 444 #define IPR4 REGISTER_32(NVIC_BASE + 0x310)
cfavreau 0:c79e1f29f029 445 #define IPR5 REGISTER_32(NVIC_BASE + 0x314)
cfavreau 0:c79e1f29f029 446 #define IPR6 REGISTER_32(NVIC_BASE + 0x318)
cfavreau 0:c79e1f29f029 447 #define IPR7 REGISTER_32(NVIC_BASE + 0x31c)
cfavreau 0:c79e1f29f029 448
cfavreau 0:c79e1f29f029 449 // STK
cfavreau 0:c79e1f29f029 450 #define SYST_CSR REGISTER_32(STK_BASE + 0)
cfavreau 0:c79e1f29f029 451 #define SYST_RVR REGISTER_32(STK_BASE + 4)
cfavreau 0:c79e1f29f029 452 #define SYST_CVR REGISTER_32(STK_BASE + 8)
cfavreau 0:c79e1f29f029 453 #define SYST_CALIB REGISTER_32(STK_BASE + 0x0c)
cfavreau 0:c79e1f29f029 454
cfavreau 0:c79e1f29f029 455 // SCB_BASE
cfavreau 0:c79e1f29f029 456 #define CPUID REGISTER_32(SCB_BASE + 0)
cfavreau 0:c79e1f29f029 457 #define ICSR REGISTER_32(SCB_BASE + 4)
cfavreau 0:c79e1f29f029 458 #define AIRCR REGISTER_32(SCB_BASE + 0x0c)
cfavreau 0:c79e1f29f029 459 #define SCR REGISTER_32(SCB_BASE + 0x10)
cfavreau 0:c79e1f29f029 460 #define CCR REGISTER_32(SCB_BASE + 0x14)
cfavreau 0:c79e1f29f029 461 #define SHPR2 REGISTER_32(SCB_BASE + 0x1c)
cfavreau 0:c79e1f29f029 462 #define SHPR3 REGISTER_32(SCB_BASE + 0x20)