GHI Electronics / Mbed 2 deprecated Official_mBot

The preloaded firmware shipped on the mBot.

Dependencies:   mbed

Fork of Official_mBot by Fred Parker

USBDevice/USBDevice/USBRegs_STM32.h@1:ffd9a51e7d35, 2014-11-25 (annotated)

Committer:
jeffknaggs
Date:
Tue Nov 25 14:49:40 2014 +0000
Revision:
1:ffd9a51e7d35
Parent:
0:865d42c46692 
Initial commit.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jeffknaggs 0:865d42c46692 1 /**
jeffknaggs 0:865d42c46692 2 ******************************************************************************
jeffknaggs 0:865d42c46692 3 * @file usb_regs.h
jeffknaggs 0:865d42c46692 4 * @author MCD Application Team
jeffknaggs 0:865d42c46692 5 * @version V2.1.0
jeffknaggs 0:865d42c46692 6 * @date 19-March-2012
jeffknaggs 0:865d42c46692 7 * @brief hardware registers
jeffknaggs 0:865d42c46692 8 ******************************************************************************
jeffknaggs 0:865d42c46692 9 * @attention
jeffknaggs 0:865d42c46692 10 *
jeffknaggs 0:865d42c46692 11 * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
jeffknaggs 0:865d42c46692 12 *
jeffknaggs 0:865d42c46692 13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
jeffknaggs 0:865d42c46692 14 * You may not use this file except in compliance with the License.
jeffknaggs 0:865d42c46692 15 * You may obtain a copy of the License at:
jeffknaggs 0:865d42c46692 16 *
jeffknaggs 0:865d42c46692 17 * http://www.st.com/software_license_agreement_liberty_v2
jeffknaggs 0:865d42c46692 18 *
jeffknaggs 0:865d42c46692 19 * Unless required by applicable law or agreed to in writing, software
jeffknaggs 0:865d42c46692 20 * distributed under the License is distributed on an "AS IS" BASIS,
jeffknaggs 0:865d42c46692 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
jeffknaggs 0:865d42c46692 22 * See the License for the specific language governing permissions and
jeffknaggs 0:865d42c46692 23 * limitations under the License.
jeffknaggs 0:865d42c46692 24 *
jeffknaggs 0:865d42c46692 25 ******************************************************************************
jeffknaggs 0:865d42c46692 26 */
jeffknaggs 0:865d42c46692 27
jeffknaggs 0:865d42c46692 28 #ifndef __USB_OTG_REGS_H__
jeffknaggs 0:865d42c46692 29 #define __USB_OTG_REGS_H__
jeffknaggs 0:865d42c46692 30
jeffknaggs 0:865d42c46692 31 typedef struct //000h
jeffknaggs 0:865d42c46692 32 {
jeffknaggs 0:865d42c46692 33 __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
jeffknaggs 0:865d42c46692 34 __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
jeffknaggs 0:865d42c46692 35 __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
jeffknaggs 0:865d42c46692 36 __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
jeffknaggs 0:865d42c46692 37 __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
jeffknaggs 0:865d42c46692 38 __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
jeffknaggs 0:865d42c46692 39 __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
jeffknaggs 0:865d42c46692 40 __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
jeffknaggs 0:865d42c46692 41 __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
jeffknaggs 0:865d42c46692 42 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
jeffknaggs 0:865d42c46692 43 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
jeffknaggs 0:865d42c46692 44 __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
jeffknaggs 0:865d42c46692 45 uint32_t Reserved30[2]; /* Reserved 030h*/
jeffknaggs 0:865d42c46692 46 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
jeffknaggs 0:865d42c46692 47 __IO uint32_t CID; /* User ID Register 03Ch*/
jeffknaggs 0:865d42c46692 48 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
jeffknaggs 0:865d42c46692 49 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
jeffknaggs 0:865d42c46692 50 __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
jeffknaggs 0:865d42c46692 51 }
jeffknaggs 0:865d42c46692 52 USB_OTG_GREGS;
jeffknaggs 0:865d42c46692 53
jeffknaggs 0:865d42c46692 54 typedef struct // 800h
jeffknaggs 0:865d42c46692 55 {
jeffknaggs 0:865d42c46692 56 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
jeffknaggs 0:865d42c46692 57 __IO uint32_t DCTL; /* dev Control Register 804h*/
jeffknaggs 0:865d42c46692 58 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
jeffknaggs 0:865d42c46692 59 uint32_t Reserved0C; /* Reserved 80Ch*/
jeffknaggs 0:865d42c46692 60 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
jeffknaggs 0:865d42c46692 61 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
jeffknaggs 0:865d42c46692 62 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
jeffknaggs 0:865d42c46692 63 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
jeffknaggs 0:865d42c46692 64 uint32_t Reserved20; /* Reserved 820h*/
jeffknaggs 0:865d42c46692 65 uint32_t Reserved9; /* Reserved 824h*/
jeffknaggs 0:865d42c46692 66 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
jeffknaggs 0:865d42c46692 67 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
jeffknaggs 0:865d42c46692 68 __IO uint32_t DTHRCTL; /* dev thr 830h*/
jeffknaggs 0:865d42c46692 69 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
jeffknaggs 0:865d42c46692 70 }
jeffknaggs 0:865d42c46692 71 USB_OTG_DREGS;
jeffknaggs 0:865d42c46692 72
jeffknaggs 0:865d42c46692 73 typedef struct
jeffknaggs 0:865d42c46692 74 {
jeffknaggs 0:865d42c46692 75 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
jeffknaggs 0:865d42c46692 76 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
jeffknaggs 0:865d42c46692 77 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
jeffknaggs 0:865d42c46692 78 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
jeffknaggs 0:865d42c46692 79 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
jeffknaggs 0:865d42c46692 80 uint32_t Reserved14;
jeffknaggs 0:865d42c46692 81 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
jeffknaggs 0:865d42c46692 82 uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
jeffknaggs 0:865d42c46692 83 }
jeffknaggs 0:865d42c46692 84 USB_OTG_INEPREGS;
jeffknaggs 0:865d42c46692 85
jeffknaggs 0:865d42c46692 86 typedef struct
jeffknaggs 0:865d42c46692 87 {
jeffknaggs 0:865d42c46692 88 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
jeffknaggs 0:865d42c46692 89 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
jeffknaggs 0:865d42c46692 90 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
jeffknaggs 0:865d42c46692 91 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
jeffknaggs 0:865d42c46692 92 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
jeffknaggs 0:865d42c46692 93 uint32_t Reserved14[3];
jeffknaggs 0:865d42c46692 94 }
jeffknaggs 0:865d42c46692 95 USB_OTG_OUTEPREGS;
jeffknaggs 0:865d42c46692 96
jeffknaggs 0:865d42c46692 97 typedef struct
jeffknaggs 0:865d42c46692 98 {
jeffknaggs 0:865d42c46692 99 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
jeffknaggs 0:865d42c46692 100 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
jeffknaggs 0:865d42c46692 101 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
jeffknaggs 0:865d42c46692 102 uint32_t Reserved40C; /* Reserved 40Ch*/
jeffknaggs 0:865d42c46692 103 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
jeffknaggs 0:865d42c46692 104 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
jeffknaggs 0:865d42c46692 105 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
jeffknaggs 0:865d42c46692 106 }
jeffknaggs 0:865d42c46692 107 USB_OTG_HREGS;
jeffknaggs 0:865d42c46692 108
jeffknaggs 0:865d42c46692 109 typedef struct
jeffknaggs 0:865d42c46692 110 {
jeffknaggs 0:865d42c46692 111 __IO uint32_t HCCHAR;
jeffknaggs 0:865d42c46692 112 __IO uint32_t HCSPLT;
jeffknaggs 0:865d42c46692 113 __IO uint32_t HCINT;
jeffknaggs 0:865d42c46692 114 __IO uint32_t HCINTMSK;
jeffknaggs 0:865d42c46692 115 __IO uint32_t HCTSIZ;
jeffknaggs 0:865d42c46692 116 uint32_t Reserved[3];
jeffknaggs 0:865d42c46692 117 }
jeffknaggs 0:865d42c46692 118 USB_OTG_HC_REGS;
jeffknaggs 0:865d42c46692 119
jeffknaggs 0:865d42c46692 120 typedef struct
jeffknaggs 0:865d42c46692 121 {
jeffknaggs 0:865d42c46692 122 USB_OTG_GREGS GREGS;
jeffknaggs 0:865d42c46692 123 uint32_t RESERVED0[188];
jeffknaggs 0:865d42c46692 124 USB_OTG_HREGS HREGS;
jeffknaggs 0:865d42c46692 125 uint32_t RESERVED1[9];
jeffknaggs 0:865d42c46692 126 __IO uint32_t HPRT;
jeffknaggs 0:865d42c46692 127 uint32_t RESERVED2[47];
jeffknaggs 0:865d42c46692 128 USB_OTG_HC_REGS HC_REGS[8];
jeffknaggs 0:865d42c46692 129 uint32_t RESERVED3[128];
jeffknaggs 0:865d42c46692 130 USB_OTG_DREGS DREGS;
jeffknaggs 0:865d42c46692 131 uint32_t RESERVED4[50];
jeffknaggs 0:865d42c46692 132 USB_OTG_INEPREGS INEP_REGS[4];
jeffknaggs 0:865d42c46692 133 uint32_t RESERVED5[96];
jeffknaggs 0:865d42c46692 134 USB_OTG_OUTEPREGS OUTEP_REGS[4];
jeffknaggs 0:865d42c46692 135 uint32_t RESERVED6[160];
jeffknaggs 0:865d42c46692 136 __IO uint32_t PCGCCTL;
jeffknaggs 0:865d42c46692 137 uint32_t RESERVED7[127];
jeffknaggs 0:865d42c46692 138 __IO uint32_t FIFO[4][1024];
jeffknaggs 0:865d42c46692 139 }
jeffknaggs 0:865d42c46692 140 USB_OTG_CORE_REGS;
jeffknaggs 0:865d42c46692 141
jeffknaggs 0:865d42c46692 142
jeffknaggs 0:865d42c46692 143 #define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
jeffknaggs 0:865d42c46692 144 #define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
jeffknaggs 0:865d42c46692 145
jeffknaggs 0:865d42c46692 146 #endif //__USB_OTG_REGS_H__
jeffknaggs 0:865d42c46692 147
jeffknaggs 0:865d42c46692 148 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
jeffknaggs 0:865d42c46692 149