GHI Electronics / Mbed 2 deprecated Official_mBot

The preloaded firmware shipped on the mBot.

Dependencies:   mbed

Fork of Official_mBot by Fred Parker

USBDevice/USBDevice/USBHAL_STM32F4.cpp@1:ffd9a51e7d35, 2014-11-25 (annotated)

Committer:
jeffknaggs
Date:
Tue Nov 25 14:49:40 2014 +0000
Revision:
1:ffd9a51e7d35
Parent:
0:865d42c46692 
Initial commit.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jeffknaggs 0:865d42c46692 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
jeffknaggs 0:865d42c46692 2 *
jeffknaggs 0:865d42c46692 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
jeffknaggs 0:865d42c46692 4 * and associated documentation files (the "Software"), to deal in the Software without
jeffknaggs 0:865d42c46692 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
jeffknaggs 0:865d42c46692 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
jeffknaggs 0:865d42c46692 7 * Software is furnished to do so, subject to the following conditions:
jeffknaggs 0:865d42c46692 8 *
jeffknaggs 0:865d42c46692 9 * The above copyright notice and this permission notice shall be included in all copies or
jeffknaggs 0:865d42c46692 10 * substantial portions of the Software.
jeffknaggs 0:865d42c46692 11 *
jeffknaggs 0:865d42c46692 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
jeffknaggs 0:865d42c46692 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
jeffknaggs 0:865d42c46692 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
jeffknaggs 0:865d42c46692 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
jeffknaggs 0:865d42c46692 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
jeffknaggs 0:865d42c46692 17 */
jeffknaggs 0:865d42c46692 18
jeffknaggs 0:865d42c46692 19 #if defined(TARGET_STM32F4)
jeffknaggs 0:865d42c46692 20
jeffknaggs 0:865d42c46692 21 #include "USBHAL.h"
jeffknaggs 0:865d42c46692 22 #include "USBRegs_STM32.h"
jeffknaggs 0:865d42c46692 23 #include "pinmap.h"
jeffknaggs 0:865d42c46692 24
jeffknaggs 0:865d42c46692 25 USBHAL * USBHAL::instance;
jeffknaggs 0:865d42c46692 26
jeffknaggs 0:865d42c46692 27 static volatile int epComplete = 0;
jeffknaggs 0:865d42c46692 28
jeffknaggs 0:865d42c46692 29 static uint32_t bufferEnd = 0;
jeffknaggs 0:865d42c46692 30 static const uint32_t rxFifoSize = 512;
jeffknaggs 0:865d42c46692 31 static uint32_t rxFifoCount = 0;
jeffknaggs 0:865d42c46692 32
jeffknaggs 0:865d42c46692 33 static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
jeffknaggs 0:865d42c46692 34
jeffknaggs 0:865d42c46692 35 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
jeffknaggs 0:865d42c46692 36 return 0;
jeffknaggs 0:865d42c46692 37 }
jeffknaggs 0:865d42c46692 38
jeffknaggs 0:865d42c46692 39 USBHAL::USBHAL(void) {
jeffknaggs 0:865d42c46692 40 NVIC_DisableIRQ(OTG_FS_IRQn);
jeffknaggs 0:865d42c46692 41 epCallback[0] = &USBHAL::EP1_OUT_callback;
jeffknaggs 0:865d42c46692 42 epCallback[1] = &USBHAL::EP1_IN_callback;
jeffknaggs 0:865d42c46692 43 epCallback[2] = &USBHAL::EP2_OUT_callback;
jeffknaggs 0:865d42c46692 44 epCallback[3] = &USBHAL::EP2_IN_callback;
jeffknaggs 0:865d42c46692 45 epCallback[4] = &USBHAL::EP3_OUT_callback;
jeffknaggs 0:865d42c46692 46 epCallback[5] = &USBHAL::EP3_IN_callback;
jeffknaggs 0:865d42c46692 47
jeffknaggs 0:865d42c46692 48 // Enable power and clocking
jeffknaggs 0:865d42c46692 49 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
jeffknaggs 0:865d42c46692 50
jeffknaggs 0:865d42c46692 51 #if defined(TARGET_STM32F407VG)
jeffknaggs 0:865d42c46692 52 pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
jeffknaggs 0:865d42c46692 53 pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS));
jeffknaggs 0:865d42c46692 54 pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS));
jeffknaggs 0:865d42c46692 55 pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
jeffknaggs 0:865d42c46692 56 pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
jeffknaggs 0:865d42c46692 57 #else
jeffknaggs 0:865d42c46692 58 pin_function(PA_8, STM_PIN_DATA(2, 10));
jeffknaggs 0:865d42c46692 59 pin_function(PA_9, STM_PIN_DATA(0, 0));
jeffknaggs 0:865d42c46692 60 pin_function(PA_10, STM_PIN_DATA(2, 10));
jeffknaggs 0:865d42c46692 61 pin_function(PA_11, STM_PIN_DATA(2, 10));
jeffknaggs 0:865d42c46692 62 pin_function(PA_12, STM_PIN_DATA(2, 10));
jeffknaggs 0:865d42c46692 63
jeffknaggs 0:865d42c46692 64 // Set ID pin to open drain with pull-up resistor
jeffknaggs 0:865d42c46692 65 pin_mode(PA_10, OpenDrain);
jeffknaggs 0:865d42c46692 66 GPIOA->PUPDR &= ~(0x3 << 20);
jeffknaggs 0:865d42c46692 67 GPIOA->PUPDR |= 1 << 20;
jeffknaggs 0:865d42c46692 68
jeffknaggs 0:865d42c46692 69 // Set VBUS pin to open drain
jeffknaggs 0:865d42c46692 70 pin_mode(PA_9, OpenDrain);
jeffknaggs 0:865d42c46692 71 #endif
jeffknaggs 0:865d42c46692 72
jeffknaggs 0:865d42c46692 73 RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
jeffknaggs 0:865d42c46692 74
jeffknaggs 0:865d42c46692 75 // Enable interrupts
jeffknaggs 0:865d42c46692 76 OTG_FS->GREGS.GAHBCFG |= (1 << 0);
jeffknaggs 0:865d42c46692 77
jeffknaggs 0:865d42c46692 78 // Turnaround time to maximum value - too small causes packet loss
jeffknaggs 0:865d42c46692 79 OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
jeffknaggs 0:865d42c46692 80
jeffknaggs 0:865d42c46692 81 // Unmask global interrupts
jeffknaggs 0:865d42c46692 82 OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
jeffknaggs 0:865d42c46692 83 (1 << 4) | // RX FIFO not empty
jeffknaggs 0:865d42c46692 84 (1 << 12); // USB reset
jeffknaggs 0:865d42c46692 85
jeffknaggs 0:865d42c46692 86 OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
jeffknaggs 0:865d42c46692 87 (1 << 2); // Non-zero-length status OUT handshake
jeffknaggs 0:865d42c46692 88
jeffknaggs 0:865d42c46692 89 OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
jeffknaggs 0:865d42c46692 90 (1 << 16); // Power Up
jeffknaggs 0:865d42c46692 91
jeffknaggs 0:865d42c46692 92 instance = this;
jeffknaggs 0:865d42c46692 93 NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
jeffknaggs 0:865d42c46692 94 NVIC_SetPriority(OTG_FS_IRQn, 1);
jeffknaggs 0:865d42c46692 95 }
jeffknaggs 0:865d42c46692 96
jeffknaggs 0:865d42c46692 97 USBHAL::~USBHAL(void) {
jeffknaggs 0:865d42c46692 98 }
jeffknaggs 0:865d42c46692 99
jeffknaggs 0:865d42c46692 100 void USBHAL::connect(void) {
jeffknaggs 0:865d42c46692 101 NVIC_EnableIRQ(OTG_FS_IRQn);
jeffknaggs 0:865d42c46692 102 }
jeffknaggs 0:865d42c46692 103
jeffknaggs 0:865d42c46692 104 void USBHAL::disconnect(void) {
jeffknaggs 0:865d42c46692 105 NVIC_DisableIRQ(OTG_FS_IRQn);
jeffknaggs 0:865d42c46692 106 }
jeffknaggs 0:865d42c46692 107
jeffknaggs 0:865d42c46692 108 void USBHAL::configureDevice(void) {
jeffknaggs 0:865d42c46692 109 // Not needed
jeffknaggs 0:865d42c46692 110 }
jeffknaggs 0:865d42c46692 111
jeffknaggs 0:865d42c46692 112 void USBHAL::unconfigureDevice(void) {
jeffknaggs 0:865d42c46692 113 // Not needed
jeffknaggs 0:865d42c46692 114 }
jeffknaggs 0:865d42c46692 115
jeffknaggs 0:865d42c46692 116 void USBHAL::setAddress(uint8_t address) {
jeffknaggs 0:865d42c46692 117 OTG_FS->DREGS.DCFG |= (address << 4);
jeffknaggs 0:865d42c46692 118 EP0write(0, 0);
jeffknaggs 0:865d42c46692 119 }
jeffknaggs 0:865d42c46692 120
jeffknaggs 0:865d42c46692 121 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
jeffknaggs 0:865d42c46692 122 uint32_t flags) {
jeffknaggs 0:865d42c46692 123 uint32_t epIndex = endpoint >> 1;
jeffknaggs 0:865d42c46692 124
jeffknaggs 0:865d42c46692 125 uint32_t type;
jeffknaggs 0:865d42c46692 126 switch (endpoint) {
jeffknaggs 0:865d42c46692 127 case EP0IN:
jeffknaggs 0:865d42c46692 128 case EP0OUT:
jeffknaggs 0:865d42c46692 129 type = 0;
jeffknaggs 0:865d42c46692 130 break;
jeffknaggs 0:865d42c46692 131 case EPISO_IN:
jeffknaggs 0:865d42c46692 132 case EPISO_OUT:
jeffknaggs 0:865d42c46692 133 type = 1;
jeffknaggs 0:865d42c46692 134 case EPBULK_IN:
jeffknaggs 0:865d42c46692 135 case EPBULK_OUT:
jeffknaggs 0:865d42c46692 136 type = 2;
jeffknaggs 0:865d42c46692 137 break;
jeffknaggs 0:865d42c46692 138 case EPINT_IN:
jeffknaggs 0:865d42c46692 139 case EPINT_OUT:
jeffknaggs 0:865d42c46692 140 type = 3;
jeffknaggs 0:865d42c46692 141 break;
jeffknaggs 0:865d42c46692 142 }
jeffknaggs 0:865d42c46692 143
jeffknaggs 0:865d42c46692 144 // Generic in or out EP controls
jeffknaggs 0:865d42c46692 145 uint32_t control = (maxPacket << 0) | // Packet size
jeffknaggs 0:865d42c46692 146 (1 << 15) | // Active endpoint
jeffknaggs 0:865d42c46692 147 (type << 18); // Endpoint type
jeffknaggs 0:865d42c46692 148
jeffknaggs 0:865d42c46692 149 if (endpoint & 0x1) { // In Endpoint
jeffknaggs 0:865d42c46692 150 // Set up the Tx FIFO
jeffknaggs 0:865d42c46692 151 if (endpoint == EP0IN) {
jeffknaggs 0:865d42c46692 152 OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
jeffknaggs 0:865d42c46692 153 (bufferEnd << 0);
jeffknaggs 0:865d42c46692 154 }
jeffknaggs 0:865d42c46692 155 else {
jeffknaggs 0:865d42c46692 156 OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
jeffknaggs 0:865d42c46692 157 (bufferEnd << 0);
jeffknaggs 0:865d42c46692 158 }
jeffknaggs 0:865d42c46692 159 bufferEnd += maxPacket >> 2;
jeffknaggs 0:865d42c46692 160
jeffknaggs 0:865d42c46692 161 // Set the In EP specific control settings
jeffknaggs 0:865d42c46692 162 if (endpoint != EP0IN) {
jeffknaggs 0:865d42c46692 163 control |= (1 << 28); // SD0PID
jeffknaggs 0:865d42c46692 164 }
jeffknaggs 0:865d42c46692 165
jeffknaggs 0:865d42c46692 166 control |= (epIndex << 22) | // TxFIFO index
jeffknaggs 0:865d42c46692 167 (1 << 27); // SNAK
jeffknaggs 0:865d42c46692 168 OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
jeffknaggs 0:865d42c46692 169
jeffknaggs 0:865d42c46692 170 // Unmask the interrupt
jeffknaggs 0:865d42c46692 171 OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
jeffknaggs 0:865d42c46692 172 }
jeffknaggs 0:865d42c46692 173 else { // Out endpoint
jeffknaggs 0:865d42c46692 174 // Set the out EP specific control settings
jeffknaggs 0:865d42c46692 175 control |= (1 << 26); // CNAK
jeffknaggs 0:865d42c46692 176 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
jeffknaggs 0:865d42c46692 177
jeffknaggs 0:865d42c46692 178 // Unmask the interrupt
jeffknaggs 0:865d42c46692 179 OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
jeffknaggs 0:865d42c46692 180 }
jeffknaggs 0:865d42c46692 181 return true;
jeffknaggs 0:865d42c46692 182 }
jeffknaggs 0:865d42c46692 183
jeffknaggs 0:865d42c46692 184 // read setup packet
jeffknaggs 0:865d42c46692 185 void USBHAL::EP0setup(uint8_t *buffer) {
jeffknaggs 0:865d42c46692 186 memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
jeffknaggs 0:865d42c46692 187 }
jeffknaggs 0:865d42c46692 188
jeffknaggs 0:865d42c46692 189 void USBHAL::EP0readStage(void) {
jeffknaggs 0:865d42c46692 190 }
jeffknaggs 0:865d42c46692 191
jeffknaggs 0:865d42c46692 192 void USBHAL::EP0read(void) {
jeffknaggs 0:865d42c46692 193 }
jeffknaggs 0:865d42c46692 194
jeffknaggs 0:865d42c46692 195 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
jeffknaggs 0:865d42c46692 196 uint32_t* buffer32 = (uint32_t *) buffer;
jeffknaggs 0:865d42c46692 197 uint32_t length = rxFifoCount;
jeffknaggs 0:865d42c46692 198 for (uint32_t i = 0; i < length; i += 4) {
jeffknaggs 0:865d42c46692 199 buffer32[i >> 2] = OTG_FS->FIFO[0][0];
jeffknaggs 0:865d42c46692 200 }
jeffknaggs 0:865d42c46692 201
jeffknaggs 0:865d42c46692 202 rxFifoCount = 0;
jeffknaggs 0:865d42c46692 203 return length;
jeffknaggs 0:865d42c46692 204 }
jeffknaggs 0:865d42c46692 205
jeffknaggs 0:865d42c46692 206 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
jeffknaggs 0:865d42c46692 207 endpointWrite(0, buffer, size);
jeffknaggs 0:865d42c46692 208 }
jeffknaggs 0:865d42c46692 209
jeffknaggs 0:865d42c46692 210 void USBHAL::EP0getWriteResult(void) {
jeffknaggs 0:865d42c46692 211 }
jeffknaggs 0:865d42c46692 212
jeffknaggs 0:865d42c46692 213 void USBHAL::EP0stall(void) {
jeffknaggs 0:865d42c46692 214 // If we stall the out endpoint here then we have problems transferring
jeffknaggs 0:865d42c46692 215 // and setup requests after the (stalled) get device qualifier requests.
jeffknaggs 0:865d42c46692 216 // TODO: Find out if this is correct behavior, or whether we are doing
jeffknaggs 0:865d42c46692 217 // something else wrong
jeffknaggs 0:865d42c46692 218 stallEndpoint(EP0IN);
jeffknaggs 0:865d42c46692 219 // stallEndpoint(EP0OUT);
jeffknaggs 0:865d42c46692 220 }
jeffknaggs 0:865d42c46692 221
jeffknaggs 0:865d42c46692 222 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
jeffknaggs 0:865d42c46692 223 uint32_t epIndex = endpoint >> 1;
jeffknaggs 0:865d42c46692 224 uint32_t size = (1 << 19) | // 1 packet
jeffknaggs 0:865d42c46692 225 (maximumSize << 0); // Packet size
jeffknaggs 0:865d42c46692 226 // if (endpoint == EP0OUT) {
jeffknaggs 0:865d42c46692 227 size |= (1 << 29); // 1 setup packet
jeffknaggs 0:865d42c46692 228 // }
jeffknaggs 0:865d42c46692 229 OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
jeffknaggs 0:865d42c46692 230 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
jeffknaggs 0:865d42c46692 231 (1 << 26); // Clear NAK
jeffknaggs 0:865d42c46692 232
jeffknaggs 0:865d42c46692 233 epComplete &= ~(1 << endpoint);
jeffknaggs 0:865d42c46692 234 return EP_PENDING;
jeffknaggs 0:865d42c46692 235 }
jeffknaggs 0:865d42c46692 236
jeffknaggs 0:865d42c46692 237 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
jeffknaggs 0:865d42c46692 238 if (!(epComplete & (1 << endpoint))) {
jeffknaggs 0:865d42c46692 239 return EP_PENDING;
jeffknaggs 0:865d42c46692 240 }
jeffknaggs 0:865d42c46692 241
jeffknaggs 0:865d42c46692 242 uint32_t* buffer32 = (uint32_t *) buffer;
jeffknaggs 0:865d42c46692 243 uint32_t length = rxFifoCount;
jeffknaggs 0:865d42c46692 244 for (uint32_t i = 0; i < length; i += 4) {
jeffknaggs 0:865d42c46692 245 buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
jeffknaggs 0:865d42c46692 246 }
jeffknaggs 0:865d42c46692 247 rxFifoCount = 0;
jeffknaggs 0:865d42c46692 248 *bytesRead = length;
jeffknaggs 0:865d42c46692 249 return EP_COMPLETED;
jeffknaggs 0:865d42c46692 250 }
jeffknaggs 0:865d42c46692 251
jeffknaggs 0:865d42c46692 252 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
jeffknaggs 0:865d42c46692 253 uint32_t epIndex = endpoint >> 1;
jeffknaggs 0:865d42c46692 254 OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
jeffknaggs 0:865d42c46692 255 (size << 0); // Size of packet
jeffknaggs 0:865d42c46692 256 OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
jeffknaggs 0:865d42c46692 257 (1 << 26); // CNAK
jeffknaggs 0:865d42c46692 258 OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
jeffknaggs 0:865d42c46692 259
jeffknaggs 0:865d42c46692 260 while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
jeffknaggs 0:865d42c46692 261
jeffknaggs 0:865d42c46692 262 for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
jeffknaggs 0:865d42c46692 263 OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
jeffknaggs 0:865d42c46692 264 }
jeffknaggs 0:865d42c46692 265
jeffknaggs 0:865d42c46692 266 epComplete &= ~(1 << endpoint);
jeffknaggs 0:865d42c46692 267
jeffknaggs 0:865d42c46692 268 return EP_PENDING;
jeffknaggs 0:865d42c46692 269 }
jeffknaggs 0:865d42c46692 270
jeffknaggs 0:865d42c46692 271 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
jeffknaggs 0:865d42c46692 272 if (epComplete & (1 << endpoint)) {
jeffknaggs 0:865d42c46692 273 epComplete &= ~(1 << endpoint);
jeffknaggs 0:865d42c46692 274 return EP_COMPLETED;
jeffknaggs 0:865d42c46692 275 }
jeffknaggs 0:865d42c46692 276
jeffknaggs 0:865d42c46692 277 return EP_PENDING;
jeffknaggs 0:865d42c46692 278 }
jeffknaggs 0:865d42c46692 279
jeffknaggs 0:865d42c46692 280 void USBHAL::stallEndpoint(uint8_t endpoint) {
jeffknaggs 0:865d42c46692 281 if (endpoint & 0x1) { // In EP
jeffknaggs 0:865d42c46692 282 OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
jeffknaggs 0:865d42c46692 283 (1 << 21); // Stall
jeffknaggs 0:865d42c46692 284 }
jeffknaggs 0:865d42c46692 285 else { // Out EP
jeffknaggs 0:865d42c46692 286 OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
jeffknaggs 0:865d42c46692 287 OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
jeffknaggs 0:865d42c46692 288 (1 << 21); // Stall
jeffknaggs 0:865d42c46692 289 }
jeffknaggs 0:865d42c46692 290 }
jeffknaggs 0:865d42c46692 291
jeffknaggs 0:865d42c46692 292 void USBHAL::unstallEndpoint(uint8_t endpoint) {
jeffknaggs 0:865d42c46692 293
jeffknaggs 0:865d42c46692 294 }
jeffknaggs 0:865d42c46692 295
jeffknaggs 0:865d42c46692 296 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
jeffknaggs 0:865d42c46692 297 return false;
jeffknaggs 0:865d42c46692 298 }
jeffknaggs 0:865d42c46692 299
jeffknaggs 0:865d42c46692 300 void USBHAL::remoteWakeup(void) {
jeffknaggs 0:865d42c46692 301 }
jeffknaggs 0:865d42c46692 302
jeffknaggs 0:865d42c46692 303
jeffknaggs 0:865d42c46692 304 void USBHAL::_usbisr(void) {
jeffknaggs 0:865d42c46692 305 instance->usbisr();
jeffknaggs 0:865d42c46692 306 }
jeffknaggs 0:865d42c46692 307
jeffknaggs 0:865d42c46692 308
jeffknaggs 0:865d42c46692 309 void USBHAL::usbisr(void) {
jeffknaggs 0:865d42c46692 310 if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
jeffknaggs 0:865d42c46692 311 // Set SNAK bits
jeffknaggs 0:865d42c46692 312 OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
jeffknaggs 0:865d42c46692 313 OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
jeffknaggs 0:865d42c46692 314 OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
jeffknaggs 0:865d42c46692 315 OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
jeffknaggs 0:865d42c46692 316
jeffknaggs 0:865d42c46692 317 OTG_FS->DREGS.DIEPMSK = (1 << 0);
jeffknaggs 0:865d42c46692 318
jeffknaggs 0:865d42c46692 319 bufferEnd = 0;
jeffknaggs 0:865d42c46692 320
jeffknaggs 0:865d42c46692 321 // Set the receive FIFO size
jeffknaggs 0:865d42c46692 322 OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
jeffknaggs 0:865d42c46692 323 bufferEnd += rxFifoSize >> 2;
jeffknaggs 0:865d42c46692 324
jeffknaggs 0:865d42c46692 325 // Create the endpoints, and wait for setup packets on out EP0
jeffknaggs 0:865d42c46692 326 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
jeffknaggs 0:865d42c46692 327 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
jeffknaggs 0:865d42c46692 328 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
jeffknaggs 0:865d42c46692 329
jeffknaggs 0:865d42c46692 330 OTG_FS->GREGS.GINTSTS = (1 << 12);
jeffknaggs 0:865d42c46692 331 }
jeffknaggs 0:865d42c46692 332
jeffknaggs 0:865d42c46692 333 if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
jeffknaggs 0:865d42c46692 334 uint32_t status = OTG_FS->GREGS.GRXSTSP;
jeffknaggs 0:865d42c46692 335
jeffknaggs 0:865d42c46692 336 uint32_t endpoint = (status & 0xF) << 1;
jeffknaggs 0:865d42c46692 337 uint32_t length = (status >> 4) & 0x7FF;
jeffknaggs 0:865d42c46692 338 uint32_t type = (status >> 17) & 0xF;
jeffknaggs 0:865d42c46692 339
jeffknaggs 0:865d42c46692 340 rxFifoCount = length;
jeffknaggs 0:865d42c46692 341
jeffknaggs 0:865d42c46692 342 if (type == 0x6) {
jeffknaggs 0:865d42c46692 343 // Setup packet
jeffknaggs 0:865d42c46692 344 for (uint32_t i=0; i<length; i+=4) {
jeffknaggs 0:865d42c46692 345 setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
jeffknaggs 0:865d42c46692 346 }
jeffknaggs 0:865d42c46692 347 rxFifoCount = 0;
jeffknaggs 0:865d42c46692 348 }
jeffknaggs 0:865d42c46692 349
jeffknaggs 0:865d42c46692 350 if (type == 0x4) {
jeffknaggs 0:865d42c46692 351 // Setup complete
jeffknaggs 0:865d42c46692 352 EP0setupCallback();
jeffknaggs 0:865d42c46692 353 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
jeffknaggs 0:865d42c46692 354 }
jeffknaggs 0:865d42c46692 355
jeffknaggs 0:865d42c46692 356 if (type == 0x2) {
jeffknaggs 0:865d42c46692 357 // Out packet
jeffknaggs 0:865d42c46692 358 if (endpoint == EP0OUT) {
jeffknaggs 0:865d42c46692 359 EP0out();
jeffknaggs 0:865d42c46692 360 }
jeffknaggs 0:865d42c46692 361 else {
jeffknaggs 0:865d42c46692 362 epComplete |= (1 << endpoint);
jeffknaggs 0:865d42c46692 363 if ((instance->*(epCallback[endpoint - 2]))()) {
jeffknaggs 0:865d42c46692 364 epComplete &= (1 << endpoint);
jeffknaggs 0:865d42c46692 365 }
jeffknaggs 0:865d42c46692 366 }
jeffknaggs 0:865d42c46692 367 }
jeffknaggs 0:865d42c46692 368
jeffknaggs 0:865d42c46692 369 for (uint32_t i=0; i<rxFifoCount; i+=4) {
jeffknaggs 0:865d42c46692 370 (void) OTG_FS->FIFO[0][0];
jeffknaggs 0:865d42c46692 371 }
jeffknaggs 0:865d42c46692 372 OTG_FS->GREGS.GINTSTS = (1 << 4);
jeffknaggs 0:865d42c46692 373 }
jeffknaggs 0:865d42c46692 374
jeffknaggs 0:865d42c46692 375 if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
jeffknaggs 0:865d42c46692 376 // Loop through the in endpoints
jeffknaggs 0:865d42c46692 377 for (uint32_t i=0; i<4; i++) {
jeffknaggs 0:865d42c46692 378 if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
jeffknaggs 0:865d42c46692 379
jeffknaggs 0:865d42c46692 380 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
jeffknaggs 0:865d42c46692 381 // If the Tx FIFO is empty on EP0 we need to send a further
jeffknaggs 0:865d42c46692 382 // packet, so call EP0in()
jeffknaggs 0:865d42c46692 383 if (i == 0) {
jeffknaggs 0:865d42c46692 384 EP0in();
jeffknaggs 0:865d42c46692 385 }
jeffknaggs 0:865d42c46692 386 // Clear the interrupt
jeffknaggs 0:865d42c46692 387 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
jeffknaggs 0:865d42c46692 388 // Stop firing Tx empty interrupts
jeffknaggs 0:865d42c46692 389 // Will get turned on again if another write is called
jeffknaggs 0:865d42c46692 390 OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
jeffknaggs 0:865d42c46692 391 }
jeffknaggs 0:865d42c46692 392
jeffknaggs 0:865d42c46692 393 // If the transfer is complete
jeffknaggs 0:865d42c46692 394 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
jeffknaggs 0:865d42c46692 395 epComplete |= (1 << (1 + (i << 1)));
jeffknaggs 0:865d42c46692 396 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
jeffknaggs 0:865d42c46692 397 }
jeffknaggs 0:865d42c46692 398 }
jeffknaggs 0:865d42c46692 399 }
jeffknaggs 0:865d42c46692 400 OTG_FS->GREGS.GINTSTS = (1 << 18);
jeffknaggs 0:865d42c46692 401 }
jeffknaggs 0:865d42c46692 402
jeffknaggs 0:865d42c46692 403 if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
jeffknaggs 0:865d42c46692 404 SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
jeffknaggs 0:865d42c46692 405 OTG_FS->GREGS.GINTSTS = (1 << 3);
jeffknaggs 0:865d42c46692 406 }
jeffknaggs 0:865d42c46692 407 }
jeffknaggs 0:865d42c46692 408
jeffknaggs 0:865d42c46692 409
jeffknaggs 0:865d42c46692 410 #endif