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core_cm3.h

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00001 /**************************************************************************//**
00002  * @file     core_cm3.h
00003  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
00004  * @version  V3.01
00005  * @date     06. March 2012
00006  *
00007  * @note
00008  * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
00009  *
00010  * @par
00011  * ARM Limited (ARM) is supplying this software for use with Cortex-M
00012  * processor based microcontrollers.  This file can be freely distributed
00013  * within development tools that are supporting such ARM based processors.
00014  *
00015  * @par
00016  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
00017  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
00018  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
00019  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
00020  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
00021  *
00022  ******************************************************************************/
00023 #if defined ( __ICCARM__ )
00024  #pragma system_include  /* treat file as system include file for MISRA check */
00025 #endif
00026 
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030 
00031 #ifndef __CORE_CM3_H_GENERIC
00032 #define __CORE_CM3_H_GENERIC
00033 
00034 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
00035   CMSIS violates the following MISRA-C:2004 rules:
00036 
00037    \li Required Rule 8.5, object/function definition in header file.<br>
00038      Function definitions in header files are used to allow 'inlining'.
00039 
00040    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
00041      Unions are used for effective representation of core registers.
00042 
00043    \li Advisory Rule 19.7, Function-like macro defined.<br>
00044      Function-like macros are used to allow more efficient code.
00045  */
00046 
00047 
00048 /*******************************************************************************
00049  *                 CMSIS definitions
00050  ******************************************************************************/
00051 /** \ingroup Cortex_M3
00052   @{
00053  */
00054 
00055 /*  CMSIS CM3 definitions */
00056 #define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
00057 #define __CM3_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
00058 #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
00059                                     __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
00060 
00061 #define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
00062 
00063 
00064 #if   defined ( __CC_ARM )
00065   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
00066   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
00067   #define __STATIC_INLINE  static __inline
00068 
00069 #elif defined ( __ICCARM__ )
00070   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
00071   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
00072   #define __STATIC_INLINE  static inline
00073 
00074 #elif defined ( __TMS470__ )
00075   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
00076   #define __STATIC_INLINE  static inline
00077 
00078 #elif defined ( __GNUC__ )
00079   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
00080   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
00081   #define __STATIC_INLINE  static inline
00082 
00083 #elif defined ( __TASKING__ )
00084   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
00085   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
00086   #define __STATIC_INLINE  static inline
00087 
00088 #endif
00089 
00090 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
00091 */
00092 #define __FPU_USED       0
00093 
00094 #if defined ( __CC_ARM )
00095   #if defined __TARGET_FPU_VFP
00096     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00097   #endif
00098 
00099 #elif defined ( __ICCARM__ )
00100   #if defined __ARMVFP__
00101     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00102   #endif
00103 
00104 #elif defined ( __TMS470__ )
00105   #if defined __TI__VFP_SUPPORT____
00106     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00107   #endif
00108 
00109 #elif defined ( __GNUC__ )
00110   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
00111     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00112   #endif
00113 
00114 #elif defined ( __TASKING__ )
00115     /* add preprocessor checks */
00116 #endif
00117 
00118 #include <stdint.h>                      /* standard types definitions                      */
00119 #include <core_cmInstr.h>                /* Core Instruction Access                         */
00120 #include <core_cmFunc.h>                 /* Core Function Access                            */
00121 
00122 #endif /* __CORE_CM3_H_GENERIC */
00123 
00124 #ifndef __CMSIS_GENERIC
00125 
00126 #ifndef __CORE_CM3_H_DEPENDANT
00127 #define __CORE_CM3_H_DEPENDANT
00128 
00129 /* check device defines and use defaults */
00130 #if defined __CHECK_DEVICE_DEFINES
00131   #ifndef __CM3_REV
00132     #define __CM3_REV               0x0200
00133     #warning "__CM3_REV not defined in device header file; using default!"
00134   #endif
00135 
00136   #ifndef __MPU_PRESENT
00137     #define __MPU_PRESENT             0
00138     #warning "__MPU_PRESENT not defined in device header file; using default!"
00139   #endif
00140 
00141   #ifndef __NVIC_PRIO_BITS
00142     #define __NVIC_PRIO_BITS          4
00143     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
00144   #endif
00145 
00146   #ifndef __Vendor_SysTickConfig
00147     #define __Vendor_SysTickConfig    0
00148     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
00149   #endif
00150 #endif
00151 
00152 /* IO definitions (access restrictions to peripheral registers) */
00153 /**
00154     \defgroup CMSIS_glob_defs CMSIS Global Defines
00155 
00156     <strong>IO Type Qualifiers</strong> are used
00157     \li to specify the access to peripheral variables.
00158     \li for automatic generation of peripheral register debug information.
00159 */
00160 #ifdef __cplusplus
00161   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
00162 #else
00163   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
00164 #endif
00165 #define     __O     volatile             /*!< Defines 'write only' permissions                */
00166 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
00167 
00168 /*@} end of group Cortex_M3 */
00169 
00170 
00171 
00172 /*******************************************************************************
00173  *                 Register Abstraction
00174   Core Register contain:
00175   - Core Register
00176   - Core NVIC Register
00177   - Core SCB Register
00178   - Core SysTick Register
00179   - Core Debug Register
00180   - Core MPU Register
00181  ******************************************************************************/
00182 /** \defgroup CMSIS_core_register Defines and Type Definitions
00183     \brief Type definitions and defines for Cortex-M processor based devices.
00184 */
00185 
00186 /** \ingroup    CMSIS_core_register
00187     \defgroup   CMSIS_CORE  Status and Control Registers
00188     \brief  Core Register type definitions.
00189   @{
00190  */
00191 
00192 /** \brief  Union type to access the Application Program Status Register (APSR).
00193  */
00194 typedef union
00195 {
00196   struct
00197   {
00198 #if (__CORTEX_M != 0x04)
00199     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
00200 #else
00201     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
00202     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00203     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
00204 #endif
00205     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00206     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00207     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00208     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00209     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00210   } b;                                   /*!< Structure used for bit  access                  */
00211   uint32_t w;                            /*!< Type      used for word access                  */
00212 } APSR_Type;
00213 
00214 
00215 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
00216  */
00217 typedef union
00218 {
00219   struct
00220   {
00221     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00222     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
00223   } b;                                   /*!< Structure used for bit  access                  */
00224   uint32_t w;                            /*!< Type      used for word access                  */
00225 } IPSR_Type;
00226 
00227 
00228 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
00229  */
00230 typedef union
00231 {
00232   struct
00233   {
00234     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00235 #if (__CORTEX_M != 0x04)
00236     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
00237 #else
00238     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
00239     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00240     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
00241 #endif
00242     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
00243     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
00244     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00245     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00246     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00247     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00248     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00249   } b;                                   /*!< Structure used for bit  access                  */
00250   uint32_t w;                            /*!< Type      used for word access                  */
00251 } xPSR_Type;
00252 
00253 
00254 /** \brief  Union type to access the Control Registers (CONTROL).
00255  */
00256 typedef union
00257 {
00258   struct
00259   {
00260     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
00261     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
00262     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
00263     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
00264   } b;                                   /*!< Structure used for bit  access                  */
00265   uint32_t w;                            /*!< Type      used for word access                  */
00266 } CONTROL_Type;
00267 
00268 /*@} end of group CMSIS_CORE */
00269 
00270 
00271 /** \ingroup    CMSIS_core_register
00272     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
00273     \brief      Type definitions for the NVIC Registers
00274   @{
00275  */
00276 
00277 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
00278  */
00279 typedef struct
00280 {
00281   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
00282        uint32_t RESERVED0[24];
00283   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
00284        uint32_t RSERVED1[24];
00285   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
00286        uint32_t RESERVED2[24];
00287   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
00288        uint32_t RESERVED3[24];
00289   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
00290        uint32_t RESERVED4[56];
00291   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
00292        uint32_t RESERVED5[644];
00293   __O  uint32_t STIR ;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
00294 }  NVIC_Type;
00295 
00296 /* Software Triggered Interrupt Register Definitions */
00297 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
00298 #define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
00299 
00300 /*@} end of group CMSIS_NVIC */
00301 
00302 
00303 /** \ingroup  CMSIS_core_register
00304     \defgroup CMSIS_SCB     System Control Block (SCB)
00305     \brief      Type definitions for the System Control Block Registers
00306   @{
00307  */
00308 
00309 /** \brief  Structure type to access the System Control Block (SCB).
00310  */
00311 typedef struct
00312 {
00313   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
00314   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
00315   __IO uint32_t VTOR ;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
00316   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
00317   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
00318   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
00319   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
00320   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
00321   __IO uint32_t CFSR ;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
00322   __IO uint32_t HFSR ;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
00323   __IO uint32_t DFSR ;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
00324   __IO uint32_t MMFAR ;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
00325   __IO uint32_t BFAR ;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
00326   __IO uint32_t AFSR ;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
00327   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
00328   __I  uint32_t DFR ;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
00329   __I  uint32_t ADR ;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
00330   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
00331   __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
00332        uint32_t RESERVED0[5];
00333   __IO uint32_t CPACR ;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
00334 } SCB_Type;
00335 
00336 /* SCB CPUID Register Definitions */
00337 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
00338 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
00339 
00340 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
00341 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
00342 
00343 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
00344 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
00345 
00346 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
00347 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
00348 
00349 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
00350 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
00351 
00352 /* SCB Interrupt Control State Register Definitions */
00353 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
00354 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
00355 
00356 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
00357 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
00358 
00359 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
00360 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
00361 
00362 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
00363 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
00364 
00365 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
00366 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
00367 
00368 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
00369 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
00370 
00371 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
00372 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
00373 
00374 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
00375 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
00376 
00377 #define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
00378 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
00379 
00380 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
00381 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
00382 
00383 /* SCB Vector Table Offset Register Definitions */
00384 #if (__CM3_REV < 0x0201)                   /* core r2p1 */
00385 #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
00386 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
00387 
00388 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
00389 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
00390 #else
00391 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
00392 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
00393 #endif
00394 
00395 /* SCB Application Interrupt and Reset Control Register Definitions */
00396 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
00397 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
00398 
00399 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
00400 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
00401 
00402 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
00403 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
00404 
00405 #define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
00406 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
00407 
00408 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
00409 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
00410 
00411 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
00412 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
00413 
00414 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
00415 #define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
00416 
00417 /* SCB System Control Register Definitions */
00418 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
00419 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
00420 
00421 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
00422 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
00423 
00424 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
00425 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
00426 
00427 /* SCB Configuration Control Register Definitions */
00428 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
00429 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
00430 
00431 #define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
00432 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
00433 
00434 #define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
00435 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
00436 
00437 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
00438 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
00439 
00440 #define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
00441 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
00442 
00443 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
00444 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
00445 
00446 /* SCB System Handler Control and State Register Definitions */
00447 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
00448 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
00449 
00450 #define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
00451 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
00452 
00453 #define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
00454 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
00455 
00456 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
00457 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
00458 
00459 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
00460 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
00461 
00462 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
00463 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
00464 
00465 #define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
00466 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
00467 
00468 #define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
00469 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
00470 
00471 #define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
00472 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
00473 
00474 #define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
00475 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
00476 
00477 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
00478 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
00479 
00480 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
00481 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
00482 
00483 #define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
00484 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
00485 
00486 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
00487 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
00488 
00489 /* SCB Configurable Fault Status Registers Definitions */
00490 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
00491 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
00492 
00493 #define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
00494 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
00495 
00496 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
00497 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
00498 
00499 /* SCB Hard Fault Status Registers Definitions */
00500 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
00501 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
00502 
00503 #define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
00504 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
00505 
00506 #define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
00507 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
00508 
00509 /* SCB Debug Fault Status Register Definitions */
00510 #define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
00511 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
00512 
00513 #define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
00514 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
00515 
00516 #define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
00517 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
00518 
00519 #define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
00520 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
00521 
00522 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
00523 #define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
00524 
00525 /*@} end of group CMSIS_SCB */
00526 
00527 
00528 /** \ingroup  CMSIS_core_register
00529     \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
00530     \brief      Type definitions for the System Control and ID Register not in the SCB
00531   @{
00532  */
00533 
00534 /** \brief  Structure type to access the System Control and ID Register not in the SCB.
00535  */
00536 typedef struct
00537 {
00538        uint32_t RESERVED0[1];
00539   __I  uint32_t ICTR ;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
00540 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
00541   __IO uint32_t ACTLR ;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
00542 #else
00543        uint32_t RESERVED1[1];
00544 #endif
00545 } SCnSCB_Type;
00546 
00547 /* Interrupt Controller Type Register Definitions */
00548 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
00549 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
00550 
00551 /* Auxiliary Control Register Definitions */
00552 
00553 #define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
00554 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
00555 
00556 #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
00557 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
00558 
00559 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
00560 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
00561 
00562 /*@} end of group CMSIS_SCnotSCB */
00563 
00564 
00565 /** \ingroup  CMSIS_core_register
00566     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
00567     \brief      Type definitions for the System Timer Registers.
00568   @{
00569  */
00570 
00571 /** \brief  Structure type to access the System Timer (SysTick).
00572  */
00573 typedef struct
00574 {
00575   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
00576   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
00577   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
00578   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
00579 } SysTick_Type;
00580 
00581 /* SysTick Control / Status Register Definitions */
00582 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
00583 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
00584 
00585 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
00586 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
00587 
00588 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
00589 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
00590 
00591 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
00592 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
00593 
00594 /* SysTick Reload Register Definitions */
00595 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
00596 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
00597 
00598 /* SysTick Current Register Definitions */
00599 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
00600 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
00601 
00602 /* SysTick Calibration Register Definitions */
00603 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
00604 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
00605 
00606 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
00607 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
00608 
00609 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
00610 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
00611 
00612 /*@} end of group CMSIS_SysTick */
00613 
00614 
00615 /** \ingroup  CMSIS_core_register
00616     \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
00617     \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
00618   @{
00619  */
00620 
00621 /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
00622  */
00623 typedef struct
00624 {
00625   __O  union
00626   {
00627     __O  uint8_t    u8 ;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
00628     __O  uint16_t   u16 ;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
00629     __O  uint32_t   u32 ;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
00630   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
00631        uint32_t RESERVED0[864];
00632   __IO uint32_t TER ;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
00633        uint32_t RESERVED1[15];
00634   __IO uint32_t TPR ;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
00635        uint32_t RESERVED2[15];
00636   __IO uint32_t TCR ;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
00637 } ITM_Type;
00638 
00639 /* ITM Trace Privilege Register Definitions */
00640 #define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
00641 #define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
00642 
00643 /* ITM Trace Control Register Definitions */
00644 #define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
00645 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
00646 
00647 #define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
00648 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
00649 
00650 #define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
00651 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
00652 
00653 #define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
00654 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
00655 
00656 #define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
00657 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
00658 
00659 #define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
00660 #define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
00661 
00662 #define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
00663 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
00664 
00665 #define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
00666 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
00667 
00668 #define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
00669 #define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
00670 
00671 /*@}*/ /* end of group CMSIS_ITM */
00672 
00673 
00674 /** \ingroup  CMSIS_core_register
00675     \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
00676     \brief      Type definitions for the Data Watchpoint and Trace (DWT)
00677   @{
00678  */
00679 
00680 /** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
00681  */
00682 typedef struct
00683 {
00684   __IO uint32_t CTRL ;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
00685   __IO uint32_t CYCCNT ;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
00686   __IO uint32_t CPICNT ;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
00687   __IO uint32_t EXCCNT ;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
00688   __IO uint32_t SLEEPCNT ;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
00689   __IO uint32_t LSUCNT ;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
00690   __IO uint32_t FOLDCNT ;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
00691   __I  uint32_t PCSR ;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
00692   __IO uint32_t COMP0 ;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
00693   __IO uint32_t MASK0 ;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
00694   __IO uint32_t FUNCTION0 ;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
00695        uint32_t RESERVED0[1];
00696   __IO uint32_t COMP1 ;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
00697   __IO uint32_t MASK1 ;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
00698   __IO uint32_t FUNCTION1 ;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
00699        uint32_t RESERVED1[1];
00700   __IO uint32_t COMP2 ;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
00701   __IO uint32_t MASK2 ;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
00702   __IO uint32_t FUNCTION2 ;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
00703        uint32_t RESERVED2[1];
00704   __IO uint32_t COMP3 ;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
00705   __IO uint32_t MASK3 ;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
00706   __IO uint32_t FUNCTION3 ;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
00707 } DWT_Type;
00708 
00709 /* DWT Control Register Definitions */
00710 #define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
00711 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
00712 
00713 #define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
00714 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
00715 
00716 #define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
00717 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
00718 
00719 #define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
00720 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
00721 
00722 #define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
00723 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
00724 
00725 #define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
00726 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
00727 
00728 #define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
00729 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
00730 
00731 #define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
00732 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
00733 
00734 #define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
00735 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
00736 
00737 #define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
00738 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
00739 
00740 #define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
00741 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
00742 
00743 #define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
00744 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
00745 
00746 #define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
00747 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
00748 
00749 #define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
00750 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
00751 
00752 #define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
00753 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
00754 
00755 #define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
00756 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
00757 
00758 #define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
00759 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
00760 
00761 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
00762 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
00763 
00764 /* DWT CPI Count Register Definitions */
00765 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
00766 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
00767 
00768 /* DWT Exception Overhead Count Register Definitions */
00769 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
00770 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
00771 
00772 /* DWT Sleep Count Register Definitions */
00773 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
00774 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
00775 
00776 /* DWT LSU Count Register Definitions */
00777 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
00778 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
00779 
00780 /* DWT Folded-instruction Count Register Definitions */
00781 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
00782 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
00783 
00784 /* DWT Comparator Mask Register Definitions */
00785 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
00786 #define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
00787 
00788 /* DWT Comparator Function Register Definitions */
00789 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
00790 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
00791 
00792 #define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
00793 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
00794 
00795 #define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
00796 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
00797 
00798 #define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
00799 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
00800 
00801 #define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
00802 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
00803 
00804 #define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
00805 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
00806 
00807 #define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
00808 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
00809 
00810 #define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
00811 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
00812 
00813 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
00814 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
00815 
00816 /*@}*/ /* end of group CMSIS_DWT */
00817 
00818 
00819 /** \ingroup  CMSIS_core_register
00820     \defgroup CMSIS_TPI     Trace Port Interface (TPI)
00821     \brief      Type definitions for the Trace Port Interface (TPI)
00822   @{
00823  */
00824 
00825 /** \brief  Structure type to access the Trace Port Interface Register (TPI).
00826  */
00827 typedef struct
00828 {
00829   __IO uint32_t SSPSR ;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
00830   __IO uint32_t CSPSR ;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
00831        uint32_t RESERVED0[2];
00832   __IO uint32_t ACPR ;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
00833        uint32_t RESERVED1[55];
00834   __IO uint32_t SPPR ;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
00835        uint32_t RESERVED2[131];
00836   __I  uint32_t FFSR ;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
00837   __IO uint32_t FFCR ;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
00838   __I  uint32_t FSCR ;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
00839        uint32_t RESERVED3[759];
00840   __I  uint32_t TRIGGER ;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
00841   __I  uint32_t FIFO0 ;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
00842   __I  uint32_t ITATBCTR2 ;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
00843        uint32_t RESERVED4[1];
00844   __I  uint32_t ITATBCTR0 ;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
00845   __I  uint32_t FIFO1 ;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
00846   __IO uint32_t ITCTRL ;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
00847        uint32_t RESERVED5[39];
00848   __IO uint32_t CLAIMSET ;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
00849   __IO uint32_t CLAIMCLR ;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
00850        uint32_t RESERVED7[8];
00851   __I  uint32_t DEVID ;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
00852   __I  uint32_t DEVTYPE ;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
00853 } TPI_Type;
00854 
00855 /* TPI Asynchronous Clock Prescaler Register Definitions */
00856 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
00857 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
00858 
00859 /* TPI Selected Pin Protocol Register Definitions */
00860 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
00861 #define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
00862 
00863 /* TPI Formatter and Flush Status Register Definitions */
00864 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
00865 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
00866 
00867 #define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
00868 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
00869 
00870 #define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
00871 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
00872 
00873 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
00874 #define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
00875 
00876 /* TPI Formatter and Flush Control Register Definitions */
00877 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
00878 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
00879 
00880 #define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
00881 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
00882 
00883 /* TPI TRIGGER Register Definitions */
00884 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
00885 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
00886 
00887 /* TPI Integration ETM Data Register Definitions (FIFO0) */
00888 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
00889 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
00890 
00891 #define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
00892 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
00893 
00894 #define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
00895 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
00896 
00897 #define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
00898 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
00899 
00900 #define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
00901 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
00902 
00903 #define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
00904 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
00905 
00906 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
00907 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
00908 
00909 /* TPI ITATBCTR2 Register Definitions */
00910 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
00911 #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
00912 
00913 /* TPI Integration ITM Data Register Definitions (FIFO1) */
00914 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
00915 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
00916 
00917 #define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
00918 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
00919 
00920 #define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
00921 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
00922 
00923 #define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
00924 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
00925 
00926 #define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
00927 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
00928 
00929 #define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
00930 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
00931 
00932 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
00933 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
00934 
00935 /* TPI ITATBCTR0 Register Definitions */
00936 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
00937 #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
00938 
00939 /* TPI Integration Mode Control Register Definitions */
00940 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
00941 #define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
00942 
00943 /* TPI DEVID Register Definitions */
00944 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
00945 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
00946 
00947 #define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
00948 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
00949 
00950 #define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
00951 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
00952 
00953 #define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
00954 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
00955 
00956 #define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
00957 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
00958 
00959 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
00960 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
00961 
00962 /* TPI DEVTYPE Register Definitions */
00963 #define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
00964 #define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
00965 
00966 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
00967 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
00968 
00969 /*@}*/ /* end of group CMSIS_TPI */
00970 
00971 
00972 #if (__MPU_PRESENT == 1)
00973 /** \ingroup  CMSIS_core_register
00974     \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
00975     \brief      Type definitions for the Memory Protection Unit (MPU)
00976   @{
00977  */
00978 
00979 /** \brief  Structure type to access the Memory Protection Unit (MPU).
00980  */
00981 typedef struct
00982 {
00983   __I  uint32_t TYPE ;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
00984   __IO uint32_t CTRL ;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
00985   __IO uint32_t RNR ;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
00986   __IO uint32_t RBAR ;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
00987   __IO uint32_t RASR ;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
00988   __IO uint32_t RBAR_A1 ;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
00989   __IO uint32_t RASR_A1 ;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
00990   __IO uint32_t RBAR_A2 ;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
00991   __IO uint32_t RASR_A2 ;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
00992   __IO uint32_t RBAR_A3 ;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
00993   __IO uint32_t RASR_A3 ;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
00994 } MPU_Type;
00995 
00996 /* MPU Type Register */
00997 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
00998 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
00999 
01000 #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
01001 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
01002 
01003 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
01004 #define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
01005 
01006 /* MPU Control Register */
01007 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
01008 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
01009 
01010 #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
01011 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
01012 
01013 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
01014 #define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
01015 
01016 /* MPU Region Number Register */
01017 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
01018 #define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
01019 
01020 /* MPU Region Base Address Register */
01021 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
01022 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
01023 
01024 #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
01025 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
01026 
01027 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
01028 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
01029 
01030 /* MPU Region Attribute and Size Register */
01031 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
01032 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
01033 
01034 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
01035 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
01036 
01037 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
01038 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
01039 
01040 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
01041 #define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
01042 
01043 /*@} end of group CMSIS_MPU */
01044 #endif
01045 
01046 
01047 /** \ingroup  CMSIS_core_register
01048     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
01049     \brief      Type definitions for the Core Debug Registers
01050   @{
01051  */
01052 
01053 /** \brief  Structure type to access the Core Debug Register (CoreDebug).
01054  */
01055 typedef struct
01056 {
01057   __IO uint32_t DHCSR ;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
01058   __O  uint32_t DCRSR ;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
01059   __IO uint32_t DCRDR ;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
01060   __IO uint32_t DEMCR ;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
01061 } CoreDebug_Type;
01062 
01063 /* Debug Halting Control and Status Register */
01064 #define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
01065 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
01066 
01067 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
01068 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
01069 
01070 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
01071 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
01072 
01073 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
01074 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
01075 
01076 #define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
01077 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
01078 
01079 #define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
01080 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
01081 
01082 #define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
01083 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
01084 
01085 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
01086 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
01087 
01088 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
01089 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
01090 
01091 #define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
01092 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
01093 
01094 #define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
01095 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
01096 
01097 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
01098 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
01099 
01100 /* Debug Core Register Selector Register */
01101 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
01102 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
01103 
01104 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
01105 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
01106 
01107 /* Debug Exception and Monitor Control Register */
01108 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
01109 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
01110 
01111 #define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
01112 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
01113 
01114 #define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
01115 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
01116 
01117 #define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
01118 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
01119 
01120 #define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
01121 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
01122 
01123 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
01124 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
01125 
01126 #define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
01127 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
01128 
01129 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
01130 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
01131 
01132 #define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
01133 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
01134 
01135 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
01136 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
01137 
01138 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
01139 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
01140 
01141 #define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
01142 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
01143 
01144 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
01145 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
01146 
01147 /*@} end of group CMSIS_CoreDebug */
01148 
01149 
01150 /** \ingroup    CMSIS_core_register
01151     \defgroup   CMSIS_core_base     Core Definitions
01152     \brief      Definitions for base addresses, unions, and structures.
01153   @{
01154  */
01155 
01156 /* Memory mapping of Cortex-M3 Hardware */
01157 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
01158 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
01159 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
01160 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
01161 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
01162 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
01163 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
01164 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
01165 
01166 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
01167 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
01168 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
01169 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
01170 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
01171 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
01172 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
01173 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
01174 
01175 #if (__MPU_PRESENT == 1)
01176   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
01177   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
01178 #endif
01179 
01180 /*@} */
01181 
01182 
01183 
01184 /*******************************************************************************
01185  *                Hardware Abstraction Layer
01186   Core Function Interface contains:
01187   - Core NVIC Functions
01188   - Core SysTick Functions
01189   - Core Debug Functions
01190   - Core Register Access Functions
01191  ******************************************************************************/
01192 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
01193 */
01194 
01195 
01196 
01197 /* ##########################   NVIC functions  #################################### */
01198 /** \ingroup  CMSIS_Core_FunctionInterface
01199     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
01200     \brief      Functions that manage interrupts and exceptions via the NVIC.
01201     @{
01202  */
01203 
01204 /** \brief  Set Priority Grouping
01205 
01206   The function sets the priority grouping field using the required unlock sequence.
01207   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
01208   Only values from 0..7 are used.
01209   In case of a conflict between priority grouping and available
01210   priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01211 
01212     \param [in]      PriorityGroup  Priority grouping field.
01213  */
01214 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
01215 {
01216   uint32_t reg_value;
01217   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
01218 
01219   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
01220   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
01221   reg_value  =  (reg_value                                 |
01222                 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
01223                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
01224   SCB->AIRCR =  reg_value;
01225 }
01226 
01227 
01228 /** \brief  Get Priority Grouping
01229 
01230   The function reads the priority grouping field from the NVIC Interrupt Controller.
01231 
01232     \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
01233  */
01234 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
01235 {
01236   return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
01237 }
01238 
01239 
01240 /** \brief  Enable External Interrupt
01241 
01242     The function enables a device-specific interrupt in the NVIC interrupt controller.
01243 
01244     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01245  */
01246 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type  IRQn )
01247 {
01248   NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn ) & 0x1F)); /* enable interrupt */
01249 }
01250 
01251 
01252 /** \brief  Disable External Interrupt
01253 
01254     The function disables a device-specific interrupt in the NVIC interrupt controller.
01255 
01256     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01257  */
01258 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type  IRQn)
01259 {
01260   NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn ) & 0x1F)); /* disable interrupt */
01261 }
01262 
01263 
01264 /** \brief  Get Pending Interrupt
01265 
01266     The function reads the pending register in the NVIC and returns the pending bit
01267     for the specified interrupt.
01268 
01269     \param [in]      IRQn  Interrupt number.
01270 
01271     \return             0  Interrupt status is not pending.
01272     \return             1  Interrupt status is pending.
01273  */
01274 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type  IRQn)
01275 {
01276   return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
01277 }
01278 
01279 
01280 /** \brief  Set Pending Interrupt
01281 
01282     The function sets the pending bit of an external interrupt.
01283 
01284     \param [in]      IRQn  Interrupt number. Value cannot be negative.
01285  */
01286 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type  IRQn)
01287 {
01288   NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn ) & 0x1F)); /* set interrupt pending */
01289 }
01290 
01291 
01292 /** \brief  Clear Pending Interrupt
01293 
01294     The function clears the pending bit of an external interrupt.
01295 
01296     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01297  */
01298 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type  IRQn)
01299 {
01300   NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn ) & 0x1F)); /* Clear pending interrupt */
01301 }
01302 
01303 
01304 /** \brief  Get Active Interrupt
01305 
01306     The function reads the active register in NVIC and returns the active bit.
01307 
01308     \param [in]      IRQn  Interrupt number.
01309 
01310     \return             0  Interrupt status is not active.
01311     \return             1  Interrupt status is active.
01312  */
01313 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type  IRQn)
01314 {
01315   return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
01316 }
01317 
01318 
01319 /** \brief  Set Interrupt Priority
01320 
01321     The function sets the priority of an interrupt.
01322 
01323     \note The priority cannot be set for every core interrupt.
01324 
01325     \param [in]      IRQn  Interrupt number.
01326     \param [in]  priority  Priority to set.
01327  */
01328 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type  IRQn, uint32_t priority)
01329 {
01330   if(IRQn < 0) {
01331     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
01332   else {
01333     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
01334 }
01335 
01336 
01337 /** \brief  Get Interrupt Priority
01338 
01339     The function reads the priority of an interrupt. The interrupt
01340     number can be positive to specify an external (device specific)
01341     interrupt, or negative to specify an internal (core) interrupt.
01342 
01343 
01344     \param [in]   IRQn  Interrupt number.
01345     \return             Interrupt Priority. Value is aligned automatically to the implemented
01346                         priority bits of the microcontroller.
01347  */
01348 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type  IRQn)
01349 {
01350 
01351   if(IRQn < 0) {
01352     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
01353   else {
01354     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
01355 }
01356 
01357 
01358 /** \brief  Encode Priority
01359 
01360     The function encodes the priority for an interrupt with the given priority group,
01361     preemptive priority value, and subpriority value.
01362     In case of a conflict between priority grouping and available
01363     priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
01364 
01365     \param [in]     PriorityGroup  Used priority group.
01366     \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
01367     \param [in]       SubPriority  Subpriority value (starting from 0).
01368     \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
01369  */
01370 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
01371 {
01372   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
01373   uint32_t PreemptPriorityBits;
01374   uint32_t SubPriorityBits;
01375 
01376   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
01377   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
01378 
01379   return (
01380            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
01381            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
01382          );
01383 }
01384 
01385 
01386 /** \brief  Decode Priority
01387 
01388     The function decodes an interrupt priority value with a given priority group to
01389     preemptive priority value and subpriority value.
01390     In case of a conflict between priority grouping and available
01391     priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
01392 
01393     \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
01394     \param [in]     PriorityGroup  Used priority group.
01395     \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
01396     \param [out]     pSubPriority  Subpriority value (starting from 0).
01397  */
01398 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
01399 {
01400   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
01401   uint32_t PreemptPriorityBits;
01402   uint32_t SubPriorityBits;
01403 
01404   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
01405   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
01406 
01407   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
01408   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
01409 }
01410 
01411 
01412 /** \brief  System Reset
01413 
01414     The function initiates a system reset request to reset the MCU.
01415  */
01416 __STATIC_INLINE void NVIC_SystemReset(void)
01417 {
01418   __DSB();                                                     /* Ensure all outstanding memory accesses included
01419                                                                   buffered write are completed before reset */
01420   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
01421                  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
01422                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
01423   __DSB();                                                     /* Ensure completion of memory access */
01424   while(1);                                                    /* wait until reset */
01425 }
01426 
01427 /*@} end of CMSIS_Core_NVICFunctions */
01428 
01429 
01430 
01431 /* ##################################    SysTick function  ############################################ */
01432 /** \ingroup  CMSIS_Core_FunctionInterface
01433     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
01434     \brief      Functions that configure the System.
01435   @{
01436  */
01437 
01438 #if (__Vendor_SysTickConfig == 0)
01439 
01440 /** \brief  System Tick Configuration
01441 
01442     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
01443     Counter is in free running mode to generate periodic interrupts.
01444 
01445     \param [in]  ticks  Number of ticks between two interrupts.
01446 
01447     \return          0  Function succeeded.
01448     \return          1  Function failed.
01449 
01450     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
01451     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
01452     must contain a vendor-specific implementation of this function.
01453 
01454  */
01455 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
01456 {
01457   if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
01458 
01459   SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
01460   NVIC_SetPriority (SysTick_IRQn , (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
01461   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
01462   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
01463                    SysTick_CTRL_TICKINT_Msk   |
01464                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
01465   return (0);                                                  /* Function successful */
01466 }
01467 
01468 #endif
01469 
01470 /*@} end of CMSIS_Core_SysTickFunctions */
01471 
01472 
01473 
01474 /* ##################################### Debug In/Output function ########################################### */
01475 /** \ingroup  CMSIS_Core_FunctionInterface
01476     \defgroup CMSIS_core_DebugFunctions ITM Functions
01477     \brief   Functions that access the ITM debug interface.
01478   @{
01479  */
01480 
01481 extern volatile int32_t ITM_RxBuffer ;                    /*!< External variable to receive characters.                         */
01482 #define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
01483 
01484 
01485 /** \brief  ITM Send Character
01486 
01487     The function transmits a character via the ITM channel 0, and
01488     \li Just returns when no debugger is connected that has booked the output.
01489     \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
01490 
01491     \param [in]     ch  Character to transmit.
01492 
01493     \returns            Character to transmit.
01494  */
01495 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
01496 {
01497   if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
01498       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
01499   {
01500     while (ITM->PORT[0].u32 == 0);
01501     ITM->PORT[0].u8 = (uint8_t) ch;
01502   }
01503   return (ch);
01504 }
01505 
01506 
01507 /** \brief  ITM Receive Character
01508 
01509     The function inputs a character via the external variable \ref ITM_RxBuffer.
01510 
01511     \return             Received character.
01512     \return         -1  No character pending.
01513  */
01514 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
01515   int32_t ch = -1;                           /* no character available */
01516 
01517   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
01518     ch = ITM_RxBuffer ;
01519     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
01520   }
01521 
01522   return (ch);
01523 }
01524 
01525 
01526 /** \brief  ITM Check Character
01527 
01528     The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
01529 
01530     \return          0  No character available.
01531     \return          1  Character available.
01532  */
01533 __STATIC_INLINE int32_t ITM_CheckChar (void) {
01534 
01535   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
01536     return (0);                                 /* no character available */
01537   } else {
01538     return (1);                                 /*    character available */
01539   }
01540 }
01541 
01542 /*@} end of CMSIS_core_DebugFunctions */
01543 
01544 #endif /* __CORE_CM3_H_DEPENDANT */
01545 
01546 #endif /* __CMSIS_GENERIC */
01547 
01548 #ifdef __cplusplus
01549 }
01550 #endif