Chris Pepper / MPU9150_DMP

The MPU9150s biggest selling point was its internal Motion Processor to offload the sensor fusion from the host processor, this library uploads the firmware to generate quaternions from the sensors. The API needs work but as other libraries don't support the DMP supplying as is.

Dependents:   MPU9150_Example CANSAT_COMBINED MPU9150_Example mbed_rifletool

registers.h@2:e523a92390b6, 2014-09-01 (annotated)

Committer:
p3p
Date:
Mon Sep 01 14:25:06 2014 +0000
Revision:
2:e523a92390b6
Parent:
0:74f0ae286b03 
Fix Copyright

Who changed what in which revision?

UserRevisionLine numberNew contents of line
p3p 0:74f0ae286b03 1 //registers ripped from sparkfun github
p3p 0:74f0ae286b03 2
p3p 0:74f0ae286b03 3 /* ============================================
p3p 0:74f0ae286b03 4 I2Cdev device library code is placed under the MIT license
p3p 0:74f0ae286b03 5 Copyright (c) 2012 Jeff Rowberg
p3p 0:74f0ae286b03 6
p3p 0:74f0ae286b03 7 Permission is hereby granted, free of charge, to any person obtaining a copy
p3p 0:74f0ae286b03 8 of this software and associated documentation files (the "Software"), to deal
p3p 0:74f0ae286b03 9 in the Software without restriction, including without limitation the rights
p3p 0:74f0ae286b03 10 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
p3p 0:74f0ae286b03 11 copies of the Software, and to permit persons to whom the Software is
p3p 0:74f0ae286b03 12 furnished to do so, subject to the following conditions:
p3p 0:74f0ae286b03 13
p3p 0:74f0ae286b03 14 The above copyright notice and this permission notice shall be included in
p3p 0:74f0ae286b03 15 all copies or substantial portions of the Software.
p3p 0:74f0ae286b03 16
p3p 0:74f0ae286b03 17 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
p3p 0:74f0ae286b03 18 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
p3p 0:74f0ae286b03 19 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
p3p 0:74f0ae286b03 20 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
p3p 0:74f0ae286b03 21 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
p3p 0:74f0ae286b03 22 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
p3p 0:74f0ae286b03 23 THE SOFTWARE.
p3p 0:74f0ae286b03 24 ===============================================
p3p 0:74f0ae286b03 25 */
p3p 0:74f0ae286b03 26
p3p 0:74f0ae286b03 27 //Magnetometer Registers
p3p 0:74f0ae286b03 28 #define MPU9150_RA_MAG_ADDRESS 0x0C
p3p 0:74f0ae286b03 29 #define MPU9150_RA_MAG_XOUT_L 0x03
p3p 0:74f0ae286b03 30 #define MPU9150_RA_MAG_XOUT_H 0x04
p3p 0:74f0ae286b03 31 #define MPU9150_RA_MAG_YOUT_L 0x05
p3p 0:74f0ae286b03 32 #define MPU9150_RA_MAG_YOUT_H 0x06
p3p 0:74f0ae286b03 33 #define MPU9150_RA_MAG_ZOUT_L 0x07
p3p 0:74f0ae286b03 34 #define MPU9150_RA_MAG_ZOUT_H 0x08
p3p 0:74f0ae286b03 35 #define MPU9150_RA_MAG_CTRL 0x0A
p3p 0:74f0ae286b03 36
p3p 0:74f0ae286b03 37 #define MPU6050_ADDRESS_AD0_LOW 0x68 // address pin low (GND), default for InvenSense evaluation board
p3p 0:74f0ae286b03 38 #define MPU6050_ADDRESS_AD0_HIGH 0x69 // address pin high (VCC)
p3p 0:74f0ae286b03 39 #define MPU6050_DEFAULT_ADDRESS MPU6050_ADDRESS_AD0_LOW
p3p 0:74f0ae286b03 40
p3p 0:74f0ae286b03 41 #define MPU6050_RA_XG_OFFS_TC 0x00 //[7] PWR_MODE, [6:1] XG_OFFS_TC, [0] OTP_BNK_VLD
p3p 0:74f0ae286b03 42 #define MPU6050_RA_YG_OFFS_TC 0x01 //[7] PWR_MODE, [6:1] YG_OFFS_TC, [0] OTP_BNK_VLD
p3p 0:74f0ae286b03 43 #define MPU6050_RA_ZG_OFFS_TC 0x02 //[7] PWR_MODE, [6:1] ZG_OFFS_TC, [0] OTP_BNK_VLD
p3p 0:74f0ae286b03 44 #define MPU6050_RA_X_FINE_GAIN 0x03 //[7:0] X_FINE_GAIN
p3p 0:74f0ae286b03 45 #define MPU6050_RA_Y_FINE_GAIN 0x04 //[7:0] Y_FINE_GAIN
p3p 0:74f0ae286b03 46 #define MPU6050_RA_Z_FINE_GAIN 0x05 //[7:0] Z_FINE_GAIN
p3p 0:74f0ae286b03 47 #define MPU6050_RA_XA_OFFS_H 0x06 //[15:0] XA_OFFS
p3p 0:74f0ae286b03 48 #define MPU6050_RA_XA_OFFS_L_TC 0x07
p3p 0:74f0ae286b03 49 #define MPU6050_RA_YA_OFFS_H 0x08 //[15:0] YA_OFFS
p3p 0:74f0ae286b03 50 #define MPU6050_RA_YA_OFFS_L_TC 0x09
p3p 0:74f0ae286b03 51 #define MPU6050_RA_ZA_OFFS_H 0x0A //[15:0] ZA_OFFS
p3p 0:74f0ae286b03 52 #define MPU6050_RA_ZA_OFFS_L_TC 0x0B
p3p 0:74f0ae286b03 53 #define MPU6050_RA_XG_OFFS_USRH 0x13 //[15:0] XG_OFFS_USR
p3p 0:74f0ae286b03 54 #define MPU6050_RA_XG_OFFS_USRL 0x14
p3p 0:74f0ae286b03 55 #define MPU6050_RA_YG_OFFS_USRH 0x15 //[15:0] YG_OFFS_USR
p3p 0:74f0ae286b03 56 #define MPU6050_RA_YG_OFFS_USRL 0x16
p3p 0:74f0ae286b03 57 #define MPU6050_RA_ZG_OFFS_USRH 0x17 //[15:0] ZG_OFFS_USR
p3p 0:74f0ae286b03 58 #define MPU6050_RA_ZG_OFFS_USRL 0x18
p3p 0:74f0ae286b03 59 #define MPU6050_RA_SMPLRT_DIV 0x19
p3p 0:74f0ae286b03 60 #define MPU6050_RA_CONFIG 0x1A
p3p 0:74f0ae286b03 61 #define MPU6050_RA_GYRO_CONFIG 0x1B
p3p 0:74f0ae286b03 62 #define MPU6050_RA_ACCEL_CONFIG 0x1C
p3p 0:74f0ae286b03 63 #define MPU6050_RA_FF_THR 0x1D
p3p 0:74f0ae286b03 64 #define MPU6050_RA_FF_DUR 0x1E
p3p 0:74f0ae286b03 65 #define MPU6050_RA_MOT_THR 0x1F
p3p 0:74f0ae286b03 66 #define MPU6050_RA_MOT_DUR 0x20
p3p 0:74f0ae286b03 67 #define MPU6050_RA_ZRMOT_THR 0x21
p3p 0:74f0ae286b03 68 #define MPU6050_RA_ZRMOT_DUR 0x22
p3p 0:74f0ae286b03 69 #define MPU6050_RA_FIFO_EN 0x23
p3p 0:74f0ae286b03 70 #define MPU6050_RA_I2C_MST_CTRL 0x24
p3p 0:74f0ae286b03 71 #define MPU6050_RA_I2C_SLV0_ADDR 0x25
p3p 0:74f0ae286b03 72 #define MPU6050_RA_I2C_SLV0_REG 0x26
p3p 0:74f0ae286b03 73 #define MPU6050_RA_I2C_SLV0_CTRL 0x27
p3p 0:74f0ae286b03 74 #define MPU6050_RA_I2C_SLV1_ADDR 0x28
p3p 0:74f0ae286b03 75 #define MPU6050_RA_I2C_SLV1_REG 0x29
p3p 0:74f0ae286b03 76 #define MPU6050_RA_I2C_SLV1_CTRL 0x2A
p3p 0:74f0ae286b03 77 #define MPU6050_RA_I2C_SLV2_ADDR 0x2B
p3p 0:74f0ae286b03 78 #define MPU6050_RA_I2C_SLV2_REG 0x2C
p3p 0:74f0ae286b03 79 #define MPU6050_RA_I2C_SLV2_CTRL 0x2D
p3p 0:74f0ae286b03 80 #define MPU6050_RA_I2C_SLV3_ADDR 0x2E
p3p 0:74f0ae286b03 81 #define MPU6050_RA_I2C_SLV3_REG 0x2F
p3p 0:74f0ae286b03 82 #define MPU6050_RA_I2C_SLV3_CTRL 0x30
p3p 0:74f0ae286b03 83 #define MPU6050_RA_I2C_SLV4_ADDR 0x31
p3p 0:74f0ae286b03 84 #define MPU6050_RA_I2C_SLV4_REG 0x32
p3p 0:74f0ae286b03 85 #define MPU6050_RA_I2C_SLV4_DO 0x33
p3p 0:74f0ae286b03 86 #define MPU6050_RA_I2C_SLV4_CTRL 0x34
p3p 0:74f0ae286b03 87 #define MPU6050_RA_I2C_SLV4_DI 0x35
p3p 0:74f0ae286b03 88 #define MPU6050_RA_I2C_MST_STATUS 0x36
p3p 0:74f0ae286b03 89 #define MPU6050_RA_INT_PIN_CFG 0x37
p3p 0:74f0ae286b03 90 #define MPU6050_RA_INT_ENABLE 0x38
p3p 0:74f0ae286b03 91 #define MPU6050_RA_DMP_INT_STATUS 0x39
p3p 0:74f0ae286b03 92 #define MPU6050_RA_INT_STATUS 0x3A
p3p 0:74f0ae286b03 93 #define MPU6050_RA_ACCEL_XOUT_H 0x3B
p3p 0:74f0ae286b03 94 #define MPU6050_RA_ACCEL_XOUT_L 0x3C
p3p 0:74f0ae286b03 95 #define MPU6050_RA_ACCEL_YOUT_H 0x3D
p3p 0:74f0ae286b03 96 #define MPU6050_RA_ACCEL_YOUT_L 0x3E
p3p 0:74f0ae286b03 97 #define MPU6050_RA_ACCEL_ZOUT_H 0x3F
p3p 0:74f0ae286b03 98 #define MPU6050_RA_ACCEL_ZOUT_L 0x40
p3p 0:74f0ae286b03 99 #define MPU6050_RA_TEMP_OUT_H 0x41
p3p 0:74f0ae286b03 100 #define MPU6050_RA_TEMP_OUT_L 0x42
p3p 0:74f0ae286b03 101 #define MPU6050_RA_GYRO_XOUT_H 0x43
p3p 0:74f0ae286b03 102 #define MPU6050_RA_GYRO_XOUT_L 0x44
p3p 0:74f0ae286b03 103 #define MPU6050_RA_GYRO_YOUT_H 0x45
p3p 0:74f0ae286b03 104 #define MPU6050_RA_GYRO_YOUT_L 0x46
p3p 0:74f0ae286b03 105 #define MPU6050_RA_GYRO_ZOUT_H 0x47
p3p 0:74f0ae286b03 106 #define MPU6050_RA_GYRO_ZOUT_L 0x48
p3p 0:74f0ae286b03 107 #define MPU6050_RA_EXT_SENS_DATA_00 0x49
p3p 0:74f0ae286b03 108 #define MPU6050_RA_EXT_SENS_DATA_01 0x4A
p3p 0:74f0ae286b03 109 #define MPU6050_RA_EXT_SENS_DATA_02 0x4B
p3p 0:74f0ae286b03 110 #define MPU6050_RA_EXT_SENS_DATA_03 0x4C
p3p 0:74f0ae286b03 111 #define MPU6050_RA_EXT_SENS_DATA_04 0x4D
p3p 0:74f0ae286b03 112 #define MPU6050_RA_EXT_SENS_DATA_05 0x4E
p3p 0:74f0ae286b03 113 #define MPU6050_RA_EXT_SENS_DATA_06 0x4F
p3p 0:74f0ae286b03 114 #define MPU6050_RA_EXT_SENS_DATA_07 0x50
p3p 0:74f0ae286b03 115 #define MPU6050_RA_EXT_SENS_DATA_08 0x51
p3p 0:74f0ae286b03 116 #define MPU6050_RA_EXT_SENS_DATA_09 0x52
p3p 0:74f0ae286b03 117 #define MPU6050_RA_EXT_SENS_DATA_10 0x53
p3p 0:74f0ae286b03 118 #define MPU6050_RA_EXT_SENS_DATA_11 0x54
p3p 0:74f0ae286b03 119 #define MPU6050_RA_EXT_SENS_DATA_12 0x55
p3p 0:74f0ae286b03 120 #define MPU6050_RA_EXT_SENS_DATA_13 0x56
p3p 0:74f0ae286b03 121 #define MPU6050_RA_EXT_SENS_DATA_14 0x57
p3p 0:74f0ae286b03 122 #define MPU6050_RA_EXT_SENS_DATA_15 0x58
p3p 0:74f0ae286b03 123 #define MPU6050_RA_EXT_SENS_DATA_16 0x59
p3p 0:74f0ae286b03 124 #define MPU6050_RA_EXT_SENS_DATA_17 0x5A
p3p 0:74f0ae286b03 125 #define MPU6050_RA_EXT_SENS_DATA_18 0x5B
p3p 0:74f0ae286b03 126 #define MPU6050_RA_EXT_SENS_DATA_19 0x5C
p3p 0:74f0ae286b03 127 #define MPU6050_RA_EXT_SENS_DATA_20 0x5D
p3p 0:74f0ae286b03 128 #define MPU6050_RA_EXT_SENS_DATA_21 0x5E
p3p 0:74f0ae286b03 129 #define MPU6050_RA_EXT_SENS_DATA_22 0x5F
p3p 0:74f0ae286b03 130 #define MPU6050_RA_EXT_SENS_DATA_23 0x60
p3p 0:74f0ae286b03 131 #define MPU6050_RA_MOT_DETECT_STATUS 0x61
p3p 0:74f0ae286b03 132 #define MPU6050_RA_I2C_SLV0_DO 0x63
p3p 0:74f0ae286b03 133 #define MPU6050_RA_I2C_SLV1_DO 0x64
p3p 0:74f0ae286b03 134 #define MPU6050_RA_I2C_SLV2_DO 0x65
p3p 0:74f0ae286b03 135 #define MPU6050_RA_I2C_SLV3_DO 0x66
p3p 0:74f0ae286b03 136 #define MPU6050_RA_I2C_MST_DELAY_CTRL 0x67
p3p 0:74f0ae286b03 137 #define MPU6050_RA_SIGNAL_PATH_RESET 0x68
p3p 0:74f0ae286b03 138 #define MPU6050_RA_MOT_DETECT_CTRL 0x69
p3p 0:74f0ae286b03 139 #define MPU6050_RA_USER_CTRL 0x6A
p3p 0:74f0ae286b03 140 #define MPU6050_RA_PWR_MGMT_1 0x6B
p3p 0:74f0ae286b03 141 #define MPU6050_RA_PWR_MGMT_2 0x6C
p3p 0:74f0ae286b03 142 #define MPU6050_RA_BANK_SEL 0x6D
p3p 0:74f0ae286b03 143 #define MPU6050_RA_MEM_START_ADDR 0x6E
p3p 0:74f0ae286b03 144 #define MPU6050_RA_MEM_R_W 0x6F
p3p 0:74f0ae286b03 145 #define MPU6050_RA_DMP_CFG_1 0x70
p3p 0:74f0ae286b03 146 #define MPU6050_RA_DMP_CFG_2 0x71
p3p 0:74f0ae286b03 147 #define MPU6050_RA_FIFO_COUNTH 0x72
p3p 0:74f0ae286b03 148 #define MPU6050_RA_FIFO_COUNTL 0x73
p3p 0:74f0ae286b03 149 #define MPU6050_RA_FIFO_R_W 0x74
p3p 0:74f0ae286b03 150 #define MPU6050_RA_WHO_AM_I 0x75
p3p 0:74f0ae286b03 151
p3p 0:74f0ae286b03 152 #define MPU6050_TC_PWR_MODE_BIT 7
p3p 0:74f0ae286b03 153 #define MPU6050_TC_OFFSET_BIT 6
p3p 0:74f0ae286b03 154 #define MPU6050_TC_OFFSET_LENGTH 6
p3p 0:74f0ae286b03 155 #define MPU6050_TC_OTP_BNK_VLD_BIT 0
p3p 0:74f0ae286b03 156
p3p 0:74f0ae286b03 157 #define MPU6050_VDDIO_LEVEL_VLOGIC 0
p3p 0:74f0ae286b03 158 #define MPU6050_VDDIO_LEVEL_VDD 1
p3p 0:74f0ae286b03 159
p3p 0:74f0ae286b03 160 #define MPU6050_CFG_EXT_SYNC_SET_BIT 5
p3p 0:74f0ae286b03 161 #define MPU6050_CFG_EXT_SYNC_SET_LENGTH 3
p3p 0:74f0ae286b03 162 #define MPU6050_CFG_DLPF_CFG_BIT 2
p3p 0:74f0ae286b03 163 #define MPU6050_CFG_DLPF_CFG_LENGTH 3
p3p 0:74f0ae286b03 164
p3p 0:74f0ae286b03 165 #define MPU6050_EXT_SYNC_DISABLED 0x0
p3p 0:74f0ae286b03 166 #define MPU6050_EXT_SYNC_TEMP_OUT_L 0x1
p3p 0:74f0ae286b03 167 #define MPU6050_EXT_SYNC_GYRO_XOUT_L 0x2
p3p 0:74f0ae286b03 168 #define MPU6050_EXT_SYNC_GYRO_YOUT_L 0x3
p3p 0:74f0ae286b03 169 #define MPU6050_EXT_SYNC_GYRO_ZOUT_L 0x4
p3p 0:74f0ae286b03 170 #define MPU6050_EXT_SYNC_ACCEL_XOUT_L 0x5
p3p 0:74f0ae286b03 171 #define MPU6050_EXT_SYNC_ACCEL_YOUT_L 0x6
p3p 0:74f0ae286b03 172 #define MPU6050_EXT_SYNC_ACCEL_ZOUT_L 0x7
p3p 0:74f0ae286b03 173
p3p 0:74f0ae286b03 174 #define MPU6050_DLPF_BW_256 0x00
p3p 0:74f0ae286b03 175 #define MPU6050_DLPF_BW_188 0x01
p3p 0:74f0ae286b03 176 #define MPU6050_DLPF_BW_98 0x02
p3p 0:74f0ae286b03 177 #define MPU6050_DLPF_BW_42 0x03
p3p 0:74f0ae286b03 178 #define MPU6050_DLPF_BW_20 0x04
p3p 0:74f0ae286b03 179 #define MPU6050_DLPF_BW_10 0x05
p3p 0:74f0ae286b03 180 #define MPU6050_DLPF_BW_5 0x06
p3p 0:74f0ae286b03 181
p3p 0:74f0ae286b03 182 #define MPU6050_GCONFIG_FS_SEL_BIT 4
p3p 0:74f0ae286b03 183 #define MPU6050_GCONFIG_FS_SEL_LENGTH 2
p3p 0:74f0ae286b03 184
p3p 0:74f0ae286b03 185 #define MPU6050_GYRO_FS_250 0x00
p3p 0:74f0ae286b03 186 #define MPU6050_GYRO_FS_500 0x01
p3p 0:74f0ae286b03 187 #define MPU6050_GYRO_FS_1000 0x02
p3p 0:74f0ae286b03 188 #define MPU6050_GYRO_FS_2000 0x03
p3p 0:74f0ae286b03 189
p3p 0:74f0ae286b03 190 #define MPU6050_ACONFIG_XA_ST_BIT 7
p3p 0:74f0ae286b03 191 #define MPU6050_ACONFIG_YA_ST_BIT 6
p3p 0:74f0ae286b03 192 #define MPU6050_ACONFIG_ZA_ST_BIT 5
p3p 0:74f0ae286b03 193 #define MPU6050_ACONFIG_AFS_SEL_BIT 4
p3p 0:74f0ae286b03 194 #define MPU6050_ACONFIG_AFS_SEL_LENGTH 2
p3p 0:74f0ae286b03 195 #define MPU6050_ACONFIG_ACCEL_HPF_BIT 2
p3p 0:74f0ae286b03 196 #define MPU6050_ACONFIG_ACCEL_HPF_LENGTH 3
p3p 0:74f0ae286b03 197
p3p 0:74f0ae286b03 198 #define MPU6050_ACCEL_FS_2 0x00
p3p 0:74f0ae286b03 199 #define MPU6050_ACCEL_FS_4 0x01
p3p 0:74f0ae286b03 200 #define MPU6050_ACCEL_FS_8 0x02
p3p 0:74f0ae286b03 201 #define MPU6050_ACCEL_FS_16 0x03
p3p 0:74f0ae286b03 202
p3p 0:74f0ae286b03 203 #define MPU6050_DHPF_RESET 0x00
p3p 0:74f0ae286b03 204 #define MPU6050_DHPF_5 0x01
p3p 0:74f0ae286b03 205 #define MPU6050_DHPF_2P5 0x02
p3p 0:74f0ae286b03 206 #define MPU6050_DHPF_1P25 0x03
p3p 0:74f0ae286b03 207 #define MPU6050_DHPF_0P63 0x04
p3p 0:74f0ae286b03 208 #define MPU6050_DHPF_HOLD 0x07
p3p 0:74f0ae286b03 209
p3p 0:74f0ae286b03 210 #define MPU6050_TEMP_FIFO_EN_BIT 7
p3p 0:74f0ae286b03 211 #define MPU6050_XG_FIFO_EN_BIT 6
p3p 0:74f0ae286b03 212 #define MPU6050_YG_FIFO_EN_BIT 5
p3p 0:74f0ae286b03 213 #define MPU6050_ZG_FIFO_EN_BIT 4
p3p 0:74f0ae286b03 214 #define MPU6050_ACCEL_FIFO_EN_BIT 3
p3p 0:74f0ae286b03 215 #define MPU6050_SLV2_FIFO_EN_BIT 2
p3p 0:74f0ae286b03 216 #define MPU6050_SLV1_FIFO_EN_BIT 1
p3p 0:74f0ae286b03 217 #define MPU6050_SLV0_FIFO_EN_BIT 0
p3p 0:74f0ae286b03 218
p3p 0:74f0ae286b03 219 #define MPU6050_MULT_MST_EN_BIT 7
p3p 0:74f0ae286b03 220 #define MPU6050_WAIT_FOR_ES_BIT 6
p3p 0:74f0ae286b03 221 #define MPU6050_SLV_3_FIFO_EN_BIT 5
p3p 0:74f0ae286b03 222 #define MPU6050_I2C_MST_P_NSR_BIT 4
p3p 0:74f0ae286b03 223 #define MPU6050_I2C_MST_CLK_BIT 3
p3p 0:74f0ae286b03 224 #define MPU6050_I2C_MST_CLK_LENGTH 4
p3p 0:74f0ae286b03 225
p3p 0:74f0ae286b03 226 #define MPU6050_CLOCK_DIV_348 0x0
p3p 0:74f0ae286b03 227 #define MPU6050_CLOCK_DIV_333 0x1
p3p 0:74f0ae286b03 228 #define MPU6050_CLOCK_DIV_320 0x2
p3p 0:74f0ae286b03 229 #define MPU6050_CLOCK_DIV_308 0x3
p3p 0:74f0ae286b03 230 #define MPU6050_CLOCK_DIV_296 0x4
p3p 0:74f0ae286b03 231 #define MPU6050_CLOCK_DIV_286 0x5
p3p 0:74f0ae286b03 232 #define MPU6050_CLOCK_DIV_276 0x6
p3p 0:74f0ae286b03 233 #define MPU6050_CLOCK_DIV_267 0x7
p3p 0:74f0ae286b03 234 #define MPU6050_CLOCK_DIV_258 0x8
p3p 0:74f0ae286b03 235 #define MPU6050_CLOCK_DIV_500 0x9
p3p 0:74f0ae286b03 236 #define MPU6050_CLOCK_DIV_471 0xA
p3p 0:74f0ae286b03 237 #define MPU6050_CLOCK_DIV_444 0xB
p3p 0:74f0ae286b03 238 #define MPU6050_CLOCK_DIV_421 0xC
p3p 0:74f0ae286b03 239 #define MPU6050_CLOCK_DIV_400 0xD
p3p 0:74f0ae286b03 240 #define MPU6050_CLOCK_DIV_381 0xE
p3p 0:74f0ae286b03 241 #define MPU6050_CLOCK_DIV_364 0xF
p3p 0:74f0ae286b03 242
p3p 0:74f0ae286b03 243 #define MPU6050_I2C_SLV_RW_BIT 7
p3p 0:74f0ae286b03 244 #define MPU6050_I2C_SLV_ADDR_BIT 6
p3p 0:74f0ae286b03 245 #define MPU6050_I2C_SLV_ADDR_LENGTH 7
p3p 0:74f0ae286b03 246 #define MPU6050_I2C_SLV_EN_BIT 7
p3p 0:74f0ae286b03 247 #define MPU6050_I2C_SLV_BYTE_SW_BIT 6
p3p 0:74f0ae286b03 248 #define MPU6050_I2C_SLV_REG_DIS_BIT 5
p3p 0:74f0ae286b03 249 #define MPU6050_I2C_SLV_GRP_BIT 4
p3p 0:74f0ae286b03 250 #define MPU6050_I2C_SLV_LEN_BIT 3
p3p 0:74f0ae286b03 251 #define MPU6050_I2C_SLV_LEN_LENGTH 4
p3p 0:74f0ae286b03 252
p3p 0:74f0ae286b03 253 #define MPU6050_I2C_SLV4_RW_BIT 7
p3p 0:74f0ae286b03 254 #define MPU6050_I2C_SLV4_ADDR_BIT 6
p3p 0:74f0ae286b03 255 #define MPU6050_I2C_SLV4_ADDR_LENGTH 7
p3p 0:74f0ae286b03 256 #define MPU6050_I2C_SLV4_EN_BIT 7
p3p 0:74f0ae286b03 257 #define MPU6050_I2C_SLV4_INT_EN_BIT 6
p3p 0:74f0ae286b03 258 #define MPU6050_I2C_SLV4_REG_DIS_BIT 5
p3p 0:74f0ae286b03 259 #define MPU6050_I2C_SLV4_MST_DLY_BIT 4
p3p 0:74f0ae286b03 260 #define MPU6050_I2C_SLV4_MST_DLY_LENGTH 5
p3p 0:74f0ae286b03 261
p3p 0:74f0ae286b03 262 #define MPU6050_MST_PASS_THROUGH_BIT 7
p3p 0:74f0ae286b03 263 #define MPU6050_MST_I2C_SLV4_DONE_BIT 6
p3p 0:74f0ae286b03 264 #define MPU6050_MST_I2C_LOST_ARB_BIT 5
p3p 0:74f0ae286b03 265 #define MPU6050_MST_I2C_SLV4_NACK_BIT 4
p3p 0:74f0ae286b03 266 #define MPU6050_MST_I2C_SLV3_NACK_BIT 3
p3p 0:74f0ae286b03 267 #define MPU6050_MST_I2C_SLV2_NACK_BIT 2
p3p 0:74f0ae286b03 268 #define MPU6050_MST_I2C_SLV1_NACK_BIT 1
p3p 0:74f0ae286b03 269 #define MPU6050_MST_I2C_SLV0_NACK_BIT 0
p3p 0:74f0ae286b03 270
p3p 0:74f0ae286b03 271 #define MPU6050_INTCFG_INT_LEVEL_BIT 7
p3p 0:74f0ae286b03 272 #define MPU6050_INTCFG_INT_OPEN_BIT 6
p3p 0:74f0ae286b03 273 #define MPU6050_INTCFG_LATCH_INT_EN_BIT 5
p3p 0:74f0ae286b03 274 #define MPU6050_INTCFG_INT_RD_CLEAR_BIT 4
p3p 0:74f0ae286b03 275 #define MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT 3
p3p 0:74f0ae286b03 276 #define MPU6050_INTCFG_FSYNC_INT_EN_BIT 2
p3p 0:74f0ae286b03 277 #define MPU6050_INTCFG_I2C_BYPASS_EN_BIT 1
p3p 0:74f0ae286b03 278 #define MPU6050_INTCFG_CLKOUT_EN_BIT 0
p3p 0:74f0ae286b03 279
p3p 0:74f0ae286b03 280 #define MPU6050_INTMODE_ACTIVEHIGH 0x00
p3p 0:74f0ae286b03 281 #define MPU6050_INTMODE_ACTIVELOW 0x01
p3p 0:74f0ae286b03 282
p3p 0:74f0ae286b03 283 #define MPU6050_INTDRV_PUSHPULL 0x00
p3p 0:74f0ae286b03 284 #define MPU6050_INTDRV_OPENDRAIN 0x01
p3p 0:74f0ae286b03 285
p3p 0:74f0ae286b03 286 #define MPU6050_INTLATCH_50USPULSE 0x00
p3p 0:74f0ae286b03 287 #define MPU6050_INTLATCH_WAITCLEAR 0x01
p3p 0:74f0ae286b03 288
p3p 0:74f0ae286b03 289 #define MPU6050_INTCLEAR_STATUSREAD 0x00
p3p 0:74f0ae286b03 290 #define MPU6050_INTCLEAR_ANYREAD 0x01
p3p 0:74f0ae286b03 291
p3p 0:74f0ae286b03 292 #define MPU6050_INTERRUPT_FF_BIT 7
p3p 0:74f0ae286b03 293 #define MPU6050_INTERRUPT_MOT_BIT 6
p3p 0:74f0ae286b03 294 #define MPU6050_INTERRUPT_ZMOT_BIT 5
p3p 0:74f0ae286b03 295 #define MPU6050_INTERRUPT_FIFO_OFLOW_BIT 4
p3p 0:74f0ae286b03 296 #define MPU6050_INTERRUPT_I2C_MST_INT_BIT 3
p3p 0:74f0ae286b03 297 #define MPU6050_INTERRUPT_PLL_RDY_INT_BIT 2
p3p 0:74f0ae286b03 298 #define MPU6050_INTERRUPT_DMP_INT_BIT 1
p3p 0:74f0ae286b03 299 #define MPU6050_INTERRUPT_DATA_RDY_BIT 0
p3p 0:74f0ae286b03 300
p3p 0:74f0ae286b03 301 // TODO: figure out what these actually do
p3p 0:74f0ae286b03 302 // UMPL source code is not very obivous
p3p 0:74f0ae286b03 303 #define MPU6050_DMPINT_5_BIT 5
p3p 0:74f0ae286b03 304 #define MPU6050_DMPINT_4_BIT 4
p3p 0:74f0ae286b03 305 #define MPU6050_DMPINT_3_BIT 3
p3p 0:74f0ae286b03 306 #define MPU6050_DMPINT_2_BIT 2
p3p 0:74f0ae286b03 307 #define MPU6050_DMPINT_1_BIT 1
p3p 0:74f0ae286b03 308 #define MPU6050_DMPINT_0_BIT 0
p3p 0:74f0ae286b03 309
p3p 0:74f0ae286b03 310 #define MPU6050_MOTION_MOT_XNEG_BIT 7
p3p 0:74f0ae286b03 311 #define MPU6050_MOTION_MOT_XPOS_BIT 6
p3p 0:74f0ae286b03 312 #define MPU6050_MOTION_MOT_YNEG_BIT 5
p3p 0:74f0ae286b03 313 #define MPU6050_MOTION_MOT_YPOS_BIT 4
p3p 0:74f0ae286b03 314 #define MPU6050_MOTION_MOT_ZNEG_BIT 3
p3p 0:74f0ae286b03 315 #define MPU6050_MOTION_MOT_ZPOS_BIT 2
p3p 0:74f0ae286b03 316 #define MPU6050_MOTION_MOT_ZRMOT_BIT 0
p3p 0:74f0ae286b03 317
p3p 0:74f0ae286b03 318 #define MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT 7
p3p 0:74f0ae286b03 319 #define MPU6050_DELAYCTRL_I2C_SLV4_DLY_EN_BIT 4
p3p 0:74f0ae286b03 320 #define MPU6050_DELAYCTRL_I2C_SLV3_DLY_EN_BIT 3
p3p 0:74f0ae286b03 321 #define MPU6050_DELAYCTRL_I2C_SLV2_DLY_EN_BIT 2
p3p 0:74f0ae286b03 322 #define MPU6050_DELAYCTRL_I2C_SLV1_DLY_EN_BIT 1
p3p 0:74f0ae286b03 323 #define MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT 0
p3p 0:74f0ae286b03 324
p3p 0:74f0ae286b03 325 #define MPU6050_PATHRESET_GYRO_RESET_BIT 2
p3p 0:74f0ae286b03 326 #define MPU6050_PATHRESET_ACCEL_RESET_BIT 1
p3p 0:74f0ae286b03 327 #define MPU6050_PATHRESET_TEMP_RESET_BIT 0
p3p 0:74f0ae286b03 328
p3p 0:74f0ae286b03 329 #define MPU6050_DETECT_ACCEL_ON_DELAY_BIT 5
p3p 0:74f0ae286b03 330 #define MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH 2
p3p 0:74f0ae286b03 331 #define MPU6050_DETECT_FF_COUNT_BIT 3
p3p 0:74f0ae286b03 332 #define MPU6050_DETECT_FF_COUNT_LENGTH 2
p3p 0:74f0ae286b03 333 #define MPU6050_DETECT_MOT_COUNT_BIT 1
p3p 0:74f0ae286b03 334 #define MPU6050_DETECT_MOT_COUNT_LENGTH 2
p3p 0:74f0ae286b03 335
p3p 0:74f0ae286b03 336 #define MPU6050_DETECT_DECREMENT_RESET 0x0
p3p 0:74f0ae286b03 337 #define MPU6050_DETECT_DECREMENT_1 0x1
p3p 0:74f0ae286b03 338 #define MPU6050_DETECT_DECREMENT_2 0x2
p3p 0:74f0ae286b03 339 #define MPU6050_DETECT_DECREMENT_4 0x3
p3p 0:74f0ae286b03 340
p3p 0:74f0ae286b03 341 #define MPU6050_USERCTRL_DMP_EN_BIT 7
p3p 0:74f0ae286b03 342 #define MPU6050_USERCTRL_FIFO_EN_BIT 6
p3p 0:74f0ae286b03 343 #define MPU6050_USERCTRL_I2C_MST_EN_BIT 5
p3p 0:74f0ae286b03 344 #define MPU6050_USERCTRL_I2C_IF_DIS_BIT 4
p3p 0:74f0ae286b03 345 #define MPU6050_USERCTRL_DMP_RESET_BIT 3
p3p 0:74f0ae286b03 346 #define MPU6050_USERCTRL_FIFO_RESET_BIT 2
p3p 0:74f0ae286b03 347 #define MPU6050_USERCTRL_I2C_MST_RESET_BIT 1
p3p 0:74f0ae286b03 348 #define MPU6050_USERCTRL_SIG_COND_RESET_BIT 0
p3p 0:74f0ae286b03 349
p3p 0:74f0ae286b03 350 #define MPU6050_PWR1_DEVICE_RESET_BIT 7
p3p 0:74f0ae286b03 351 #define MPU6050_PWR1_SLEEP_BIT 6
p3p 0:74f0ae286b03 352 #define MPU6050_PWR1_CYCLE_BIT 5
p3p 0:74f0ae286b03 353 #define MPU6050_PWR1_TEMP_DIS_BIT 3
p3p 0:74f0ae286b03 354 #define MPU6050_PWR1_CLKSEL_BIT 2
p3p 0:74f0ae286b03 355 #define MPU6050_PWR1_CLKSEL_LENGTH 3
p3p 0:74f0ae286b03 356
p3p 0:74f0ae286b03 357 #define MPU6050_CLOCK_INTERNAL 0x00
p3p 0:74f0ae286b03 358 #define MPU6050_CLOCK_PLL_XGYRO 0x01
p3p 0:74f0ae286b03 359 #define MPU6050_CLOCK_PLL_YGYRO 0x02
p3p 0:74f0ae286b03 360 #define MPU6050_CLOCK_PLL_ZGYRO 0x03
p3p 0:74f0ae286b03 361 #define MPU6050_CLOCK_PLL_EXT32K 0x04
p3p 0:74f0ae286b03 362 #define MPU6050_CLOCK_PLL_EXT19M 0x05
p3p 0:74f0ae286b03 363 #define MPU6050_CLOCK_KEEP_RESET 0x07
p3p 0:74f0ae286b03 364
p3p 0:74f0ae286b03 365 #define MPU6050_PWR2_LP_WAKE_CTRL_BIT 7
p3p 0:74f0ae286b03 366 #define MPU6050_PWR2_LP_WAKE_CTRL_LENGTH 2
p3p 0:74f0ae286b03 367 #define MPU6050_PWR2_STBY_XA_BIT 5
p3p 0:74f0ae286b03 368 #define MPU6050_PWR2_STBY_YA_BIT 4
p3p 0:74f0ae286b03 369 #define MPU6050_PWR2_STBY_ZA_BIT 3
p3p 0:74f0ae286b03 370 #define MPU6050_PWR2_STBY_XG_BIT 2
p3p 0:74f0ae286b03 371 #define MPU6050_PWR2_STBY_YG_BIT 1
p3p 0:74f0ae286b03 372 #define MPU6050_PWR2_STBY_ZG_BIT 0
p3p 0:74f0ae286b03 373
p3p 0:74f0ae286b03 374 #define MPU6050_WAKE_FREQ_1P25 0x0
p3p 0:74f0ae286b03 375 #define MPU6050_WAKE_FREQ_2P5 0x1
p3p 0:74f0ae286b03 376 #define MPU6050_WAKE_FREQ_5 0x2
p3p 0:74f0ae286b03 377 #define MPU6050_WAKE_FREQ_10 0x3
p3p 0:74f0ae286b03 378
p3p 0:74f0ae286b03 379 #define MPU6050_BANKSEL_PRFTCH_EN_BIT 6
p3p 0:74f0ae286b03 380 #define MPU6050_BANKSEL_CFG_USER_BANK_BIT 5
p3p 0:74f0ae286b03 381 #define MPU6050_BANKSEL_MEM_SEL_BIT 4
p3p 0:74f0ae286b03 382 #define MPU6050_BANKSEL_MEM_SEL_LENGTH 5
p3p 0:74f0ae286b03 383
p3p 0:74f0ae286b03 384 #define MPU6050_WHO_AM_I_BIT 6
p3p 0:74f0ae286b03 385 #define MPU6050_WHO_AM_I_LENGTH 6
p3p 0:74f0ae286b03 386
p3p 0:74f0ae286b03 387 #define MPU6050_DMP_MEMORY_BANKS 8
p3p 0:74f0ae286b03 388 #define MPU6050_DMP_MEMORY_BANK_SIZE 256
p3p 0:74f0ae286b03 389 #define MPU6050_DMP_MEMORY_CHUNK_SIZE 16