mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c@169:e3b6fe271b81, 2017-07-19 (annotated)

Committer:
Kojto
Date:
Wed Jul 19 17:31:21 2017 +0100
Revision:
169:e3b6fe271b81
Parent:
167:e84263d55307
Child:
174:b96e65c34a4d
This updates the lib to the mbed lib v 147

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /*
<> 149:156823d33999 2 * Copyright (c) 2013 Nordic Semiconductor ASA
<> 149:156823d33999 3 * All rights reserved.
<> 149:156823d33999 4 *
<> 149:156823d33999 5 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 6 * are permitted provided that the following conditions are met:
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * 1. Redistributions of source code must retain the above copyright notice, this list
<> 149:156823d33999 9 * of conditions and the following disclaimer.
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
<> 149:156823d33999 12 * integrated circuit in a product or a software update for such product, must reproduce
<> 149:156823d33999 13 * the above copyright notice, this list of conditions and the following disclaimer in
<> 149:156823d33999 14 * the documentation and/or other materials provided with the distribution.
<> 149:156823d33999 15 *
<> 149:156823d33999 16 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
<> 149:156823d33999 17 * used to endorse or promote products derived from this software without specific prior
<> 149:156823d33999 18 * written permission.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * 4. This software, with or without modification, must only be used with a
<> 149:156823d33999 21 * Nordic Semiconductor ASA integrated circuit.
<> 149:156823d33999 22 *
<> 149:156823d33999 23 * 5. Any software provided in binary or object form under this license must not be reverse
<> 149:156823d33999 24 * engineered, decompiled, modified and/or disassembled.
<> 149:156823d33999 25 *
<> 149:156823d33999 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 149:156823d33999 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 149:156823d33999 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 149:156823d33999 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 149:156823d33999 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 149:156823d33999 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 149:156823d33999 33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 149:156823d33999 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 149:156823d33999 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 36 *
<> 149:156823d33999 37 */
<> 149:156823d33999 38
<> 149:156823d33999 39 #include "us_ticker_api.h"
<> 149:156823d33999 40 #include "common_rtc.h"
<> 149:156823d33999 41 #include "app_util.h"
<> 149:156823d33999 42 #include "nrf_drv_common.h"
<> 149:156823d33999 43 #include "lp_ticker_api.h"
Anna Bridge 163:74e0ce7f98e8 44 #include "mbed_critical.h"
<> 149:156823d33999 45
AnnaBridge 165:e614a9f1c9e2 46 #if defined(NRF52_ERRATA_20)
AnnaBridge 165:e614a9f1c9e2 47 #include "softdevice_handler.h"
AnnaBridge 165:e614a9f1c9e2 48 #endif
<> 149:156823d33999 49
<> 149:156823d33999 50 //------------------------------------------------------------------------------
<> 149:156823d33999 51 // Common stuff used also by lp_ticker and rtc_api (see "common_rtc.h").
<> 149:156823d33999 52 //
<> 149:156823d33999 53 #include "app_util_platform.h"
<> 149:156823d33999 54
<> 149:156823d33999 55 bool m_common_rtc_enabled = false;
<> 149:156823d33999 56 uint32_t volatile m_common_rtc_overflows = 0;
<> 149:156823d33999 57
Anna Bridge 163:74e0ce7f98e8 58 __STATIC_INLINE void rtc_ovf_event_check(void)
Anna Bridge 163:74e0ce7f98e8 59 {
Anna Bridge 163:74e0ce7f98e8 60 if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) {
Anna Bridge 163:74e0ce7f98e8 61 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
Anna Bridge 163:74e0ce7f98e8 62 // Don't disable this event. It shall occur periodically.
Anna Bridge 163:74e0ce7f98e8 63
Anna Bridge 163:74e0ce7f98e8 64 ++m_common_rtc_overflows;
Anna Bridge 163:74e0ce7f98e8 65 }
Anna Bridge 163:74e0ce7f98e8 66 }
Anna Bridge 163:74e0ce7f98e8 67
<> 149:156823d33999 68 #if defined(TARGET_MCU_NRF51822)
<> 149:156823d33999 69 void common_rtc_irq_handler(void)
<> 149:156823d33999 70 #else
<> 149:156823d33999 71 void COMMON_RTC_IRQ_HANDLER(void)
<> 149:156823d33999 72 #endif
<> 149:156823d33999 73 {
Anna Bridge 163:74e0ce7f98e8 74
Anna Bridge 163:74e0ce7f98e8 75 rtc_ovf_event_check();
Anna Bridge 163:74e0ce7f98e8 76
<> 149:156823d33999 77 if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT)) {
<> 149:156823d33999 78 us_ticker_irq_handler();
<> 149:156823d33999 79 }
<> 149:156823d33999 80
<> 149:156823d33999 81 #if DEVICE_LOWPOWERTIMER
<> 149:156823d33999 82 if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT)) {
<> 149:156823d33999 83
<> 149:156823d33999 84 lp_ticker_irq_handler();
<> 149:156823d33999 85 }
<> 149:156823d33999 86 #endif
AnnaBridge 165:e614a9f1c9e2 87 }
<> 149:156823d33999 88
AnnaBridge 165:e614a9f1c9e2 89 // Function for fix errata 20: RTC Register values are invalid
AnnaBridge 165:e614a9f1c9e2 90 __STATIC_INLINE void errata_20(void)
AnnaBridge 165:e614a9f1c9e2 91 {
AnnaBridge 165:e614a9f1c9e2 92 #if defined(NRF52_ERRATA_20)
AnnaBridge 165:e614a9f1c9e2 93 if (!softdevice_handler_is_enabled())
AnnaBridge 165:e614a9f1c9e2 94 {
AnnaBridge 165:e614a9f1c9e2 95 NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
AnnaBridge 165:e614a9f1c9e2 96 NRF_CLOCK->TASKS_LFCLKSTART = 1;
AnnaBridge 165:e614a9f1c9e2 97
AnnaBridge 165:e614a9f1c9e2 98 while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0)
AnnaBridge 165:e614a9f1c9e2 99 {
AnnaBridge 165:e614a9f1c9e2 100 }
AnnaBridge 165:e614a9f1c9e2 101 }
AnnaBridge 165:e614a9f1c9e2 102 NRF_RTC1->TASKS_STOP = 0;
AnnaBridge 165:e614a9f1c9e2 103 #endif
<> 149:156823d33999 104 }
<> 149:156823d33999 105
<> 150:02e0a0aed4ec 106 void RTC1_IRQHandler(void);
<> 150:02e0a0aed4ec 107
<> 149:156823d33999 108 void common_rtc_init(void)
<> 149:156823d33999 109 {
<> 149:156823d33999 110 if (m_common_rtc_enabled) {
<> 149:156823d33999 111 return;
<> 149:156823d33999 112 }
<> 149:156823d33999 113
AnnaBridge 165:e614a9f1c9e2 114 errata_20();
AnnaBridge 165:e614a9f1c9e2 115
<> 150:02e0a0aed4ec 116 NVIC_SetVector(RTC1_IRQn, (uint32_t)RTC1_IRQHandler);
<> 150:02e0a0aed4ec 117
<> 149:156823d33999 118 // RTC is driven by the low frequency (32.768 kHz) clock, a proper request
<> 149:156823d33999 119 // must be made to have it running.
<> 149:156823d33999 120 // Currently this clock is started in 'SystemInit' (see "system_nrf51.c"
<> 149:156823d33999 121 // or "system_nrf52.c", respectively).
<> 149:156823d33999 122
<> 149:156823d33999 123 nrf_rtc_prescaler_set(COMMON_RTC_INSTANCE, 0);
<> 149:156823d33999 124
<> 149:156823d33999 125 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT);
<> 149:156823d33999 126 #if defined(TARGET_MCU_NRF51822)
<> 149:156823d33999 127 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
<> 149:156823d33999 128 #endif
<> 149:156823d33999 129 #if DEVICE_LOWPOWERTIMER
<> 149:156823d33999 130 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT);
<> 149:156823d33999 131 #endif
<> 149:156823d33999 132 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
<> 149:156823d33999 133
<> 149:156823d33999 134 // Interrupts on all related events are enabled permanently. Particular
<> 149:156823d33999 135 // events will be enabled or disabled as needed (such approach is more
<> 149:156823d33999 136 // energy efficient).
<> 149:156823d33999 137 nrf_rtc_int_enable(COMMON_RTC_INSTANCE,
AnnaBridge 165:e614a9f1c9e2 138 #if DEVICE_LOWPOWERTIMER
<> 149:156823d33999 139 LP_TICKER_INT_MASK |
AnnaBridge 165:e614a9f1c9e2 140 #endif
<> 149:156823d33999 141 US_TICKER_INT_MASK |
<> 149:156823d33999 142 NRF_RTC_INT_OVERFLOW_MASK);
<> 149:156823d33999 143
<> 149:156823d33999 144 // This event is enabled permanently, since overflow indications are needed
<> 149:156823d33999 145 // continuously.
<> 149:156823d33999 146 nrf_rtc_event_enable(COMMON_RTC_INSTANCE, NRF_RTC_INT_OVERFLOW_MASK);
<> 149:156823d33999 147 // All other relevant events are initially disabled.
<> 149:156823d33999 148 nrf_rtc_event_disable(COMMON_RTC_INSTANCE,
AnnaBridge 165:e614a9f1c9e2 149 #if defined(TARGET_MCU_NRF51822)
<> 149:156823d33999 150 OS_TICK_INT_MASK |
AnnaBridge 165:e614a9f1c9e2 151 #endif
AnnaBridge 165:e614a9f1c9e2 152 #if DEVICE_LOWPOWERTIMER
<> 149:156823d33999 153 LP_TICKER_INT_MASK |
AnnaBridge 165:e614a9f1c9e2 154 #endif
<> 149:156823d33999 155 US_TICKER_INT_MASK);
<> 149:156823d33999 156
<> 149:156823d33999 157 nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE),
<> 150:02e0a0aed4ec 158 #ifdef NRF51
<> 150:02e0a0aed4ec 159 APP_IRQ_PRIORITY_LOW
AnnaBridge 165:e614a9f1c9e2 160 #elif defined(NRF52) || defined(NRF52840_XXAA)
<> 150:02e0a0aed4ec 161 APP_IRQ_PRIORITY_LOWEST
<> 150:02e0a0aed4ec 162 #endif
<> 150:02e0a0aed4ec 163 );
<> 149:156823d33999 164
<> 149:156823d33999 165 nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_START);
<> 149:156823d33999 166
<> 149:156823d33999 167 m_common_rtc_enabled = true;
<> 149:156823d33999 168 }
<> 149:156823d33999 169
Anna Bridge 163:74e0ce7f98e8 170 __STATIC_INLINE void rtc_ovf_event_safe_check(void)
Anna Bridge 163:74e0ce7f98e8 171 {
Anna Bridge 163:74e0ce7f98e8 172 core_util_critical_section_enter();
Anna Bridge 163:74e0ce7f98e8 173
Anna Bridge 163:74e0ce7f98e8 174 rtc_ovf_event_check();
Anna Bridge 163:74e0ce7f98e8 175
Anna Bridge 163:74e0ce7f98e8 176 core_util_critical_section_exit();
Anna Bridge 163:74e0ce7f98e8 177 }
Anna Bridge 163:74e0ce7f98e8 178
Anna Bridge 163:74e0ce7f98e8 179
<> 149:156823d33999 180 uint32_t common_rtc_32bit_ticks_get(void)
<> 149:156823d33999 181 {
Anna Bridge 163:74e0ce7f98e8 182 uint32_t ticks;
Anna Bridge 163:74e0ce7f98e8 183 uint32_t prev_overflows;
Anna Bridge 163:74e0ce7f98e8 184
Anna Bridge 163:74e0ce7f98e8 185 do {
Anna Bridge 163:74e0ce7f98e8 186 prev_overflows = m_common_rtc_overflows;
Anna Bridge 163:74e0ce7f98e8 187
Anna Bridge 163:74e0ce7f98e8 188 ticks = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
Anna Bridge 163:74e0ce7f98e8 189 // The counter used for time measurements is less than 32 bit wide,
Anna Bridge 163:74e0ce7f98e8 190 // so its value is complemented with the number of registered overflows
Anna Bridge 163:74e0ce7f98e8 191 // of the counter.
Anna Bridge 163:74e0ce7f98e8 192 ticks += (m_common_rtc_overflows << RTC_COUNTER_BITS);
Anna Bridge 163:74e0ce7f98e8 193
Anna Bridge 163:74e0ce7f98e8 194 // Check in case that OVF occurred during execution of a RTC handler (apply if call was from RTC handler)
Anna Bridge 163:74e0ce7f98e8 195 // m_common_rtc_overflows might been updated in this call.
Anna Bridge 163:74e0ce7f98e8 196 rtc_ovf_event_safe_check();
Anna Bridge 163:74e0ce7f98e8 197
Anna Bridge 163:74e0ce7f98e8 198 // If call was made from a low priority level m_common_rtc_overflows might have been updated in RTC handler.
Anna Bridge 163:74e0ce7f98e8 199 } while (m_common_rtc_overflows != prev_overflows);
Anna Bridge 163:74e0ce7f98e8 200
<> 149:156823d33999 201 return ticks;
<> 149:156823d33999 202 }
<> 149:156823d33999 203
<> 149:156823d33999 204 uint64_t common_rtc_64bit_us_get(void)
<> 149:156823d33999 205 {
<> 149:156823d33999 206 uint32_t ticks = common_rtc_32bit_ticks_get();
<> 149:156823d33999 207 // [ticks -> microseconds]
<> 149:156823d33999 208 return ROUNDED_DIV(((uint64_t)ticks) * 1000000, RTC_INPUT_FREQ);
<> 149:156823d33999 209 }
<> 149:156823d33999 210
<> 149:156823d33999 211 void common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel,
<> 149:156823d33999 212 uint32_t int_mask)
<> 149:156823d33999 213 {
<> 149:156823d33999 214 // The internal counter is clocked with a frequency that cannot be easily
<> 149:156823d33999 215 // multiplied to 1 MHz, therefore besides the translation of values
<> 149:156823d33999 216 // (microsecond <-> ticks) a special care of overflows handling must be
<> 149:156823d33999 217 // taken. Here the 32-bit timestamp value is complemented with information
<> 149:156823d33999 218 // about current the system up time of (ticks + number of overflows of tick
<> 149:156823d33999 219 // counter on upper bits, converted to microseconds), and such 64-bit value
<> 149:156823d33999 220 // is then translated to counter ticks. Finally, the lower 24 bits of thus
<> 149:156823d33999 221 // calculated value is written to the counter compare register to prepare
<> 149:156823d33999 222 // the interrupt generation.
<> 149:156823d33999 223 uint64_t current_time64 = common_rtc_64bit_us_get();
<> 149:156823d33999 224 // [add upper 32 bits from the current time to the timestamp value]
<> 149:156823d33999 225 uint64_t timestamp64 = us_timestamp +
<> 149:156823d33999 226 (current_time64 & ~(uint64_t)0xFFFFFFFF);
<> 149:156823d33999 227 // [if the original timestamp value happens to be after the 32 bit counter
<> 149:156823d33999 228 // of microsends overflows, correct the upper 32 bits accordingly]
<> 149:156823d33999 229 if (us_timestamp < (uint32_t)(current_time64 & 0xFFFFFFFF)) {
<> 149:156823d33999 230 timestamp64 += ((uint64_t)1 << 32);
<> 149:156823d33999 231 }
<> 149:156823d33999 232 // [microseconds -> ticks, always round the result up to avoid too early
<> 149:156823d33999 233 // interrupt generation]
<> 149:156823d33999 234 uint32_t compare_value =
<> 149:156823d33999 235 (uint32_t)CEIL_DIV((timestamp64) * RTC_INPUT_FREQ, 1000000);
<> 149:156823d33999 236
Anna Bridge 163:74e0ce7f98e8 237
Anna Bridge 163:74e0ce7f98e8 238 core_util_critical_section_enter();
<> 149:156823d33999 239 // The COMPARE event occurs when the value in compare register is N and
<> 149:156823d33999 240 // the counter value changes from N-1 to N. Therefore, the minimal safe
<> 149:156823d33999 241 // difference between the compare value to be set and the current counter
<> 149:156823d33999 242 // value is 2 ticks. This guarantees that the compare trigger is properly
<> 149:156823d33999 243 // setup before the compare condition occurs.
<> 149:156823d33999 244 uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2;
<> 149:156823d33999 245 if ((int)(compare_value - closest_safe_compare) <= 0) {
<> 149:156823d33999 246 compare_value = closest_safe_compare;
<> 149:156823d33999 247 }
<> 149:156823d33999 248
<> 149:156823d33999 249 nrf_rtc_cc_set(COMMON_RTC_INSTANCE, cc_channel, RTC_WRAP(compare_value));
<> 149:156823d33999 250 nrf_rtc_event_enable(COMMON_RTC_INSTANCE, int_mask);
Anna Bridge 163:74e0ce7f98e8 251
Anna Bridge 163:74e0ce7f98e8 252 core_util_critical_section_exit();
<> 149:156823d33999 253 }
<> 149:156823d33999 254 //------------------------------------------------------------------------------
<> 149:156823d33999 255
<> 149:156823d33999 256
<> 149:156823d33999 257 void us_ticker_init(void)
<> 149:156823d33999 258 {
<> 149:156823d33999 259 common_rtc_init();
<> 149:156823d33999 260 }
<> 149:156823d33999 261
<> 149:156823d33999 262 uint32_t us_ticker_read()
<> 149:156823d33999 263 {
<> 149:156823d33999 264 us_ticker_init();
<> 149:156823d33999 265 return (uint32_t)common_rtc_64bit_us_get();
<> 149:156823d33999 266 }
<> 149:156823d33999 267
<> 149:156823d33999 268 void us_ticker_set_interrupt(timestamp_t timestamp)
<> 149:156823d33999 269 {
<> 149:156823d33999 270 common_rtc_set_interrupt(timestamp,
<> 149:156823d33999 271 US_TICKER_CC_CHANNEL, US_TICKER_INT_MASK);
<> 149:156823d33999 272 }
<> 149:156823d33999 273
<> 149:156823d33999 274 void us_ticker_disable_interrupt(void)
<> 149:156823d33999 275 {
<> 149:156823d33999 276 nrf_rtc_event_disable(COMMON_RTC_INSTANCE, US_TICKER_INT_MASK);
<> 149:156823d33999 277 }
<> 149:156823d33999 278
<> 149:156823d33999 279 void us_ticker_clear_interrupt(void)
<> 149:156823d33999 280 {
<> 149:156823d33999 281 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT);
<> 149:156823d33999 282 }
<> 149:156823d33999 283
<> 149:156823d33999 284
<> 149:156823d33999 285 // Since there is no SysTick on NRF51, the RTC1 channel 1 is used as an
<> 149:156823d33999 286 // alternative source of RTOS ticks.
<> 149:156823d33999 287 #if defined(TARGET_MCU_NRF51822)
<> 149:156823d33999 288
<> 160:d5399cc887bb 289 #include "mbed_toolchain.h"
<> 149:156823d33999 290
<> 149:156823d33999 291
<> 149:156823d33999 292 #define MAX_RTC_COUNTER_VAL ((1uL << RTC_COUNTER_BITS) - 1)
<> 149:156823d33999 293
<> 149:156823d33999 294 /**
<> 149:156823d33999 295 * The value previously set in the capture compare register of channel 1
<> 149:156823d33999 296 */
<> 149:156823d33999 297 static uint32_t previous_tick_cc_value = 0;
<> 149:156823d33999 298
AnnaBridge 167:e84263d55307 299 /* The Period of RTC oscillator, unit [1/RTC1_CONFIG_FREQUENCY] */
AnnaBridge 167:e84263d55307 300 static uint32_t os_rtc_period;
AnnaBridge 167:e84263d55307 301
AnnaBridge 167:e84263d55307 302 /* Variable for frozen RTC1 counter value. It is used when system timer is disabled. */
AnnaBridge 167:e84263d55307 303 static uint32_t frozen_sub_tick = 0;
AnnaBridge 167:e84263d55307 304
AnnaBridge 167:e84263d55307 305
AnnaBridge 167:e84263d55307 306 #ifdef MBED_CONF_RTOS_PRESENT
AnnaBridge 167:e84263d55307 307 #include "rtx_os.h" //import osRtxInfo, SysTick_Handler()
AnnaBridge 167:e84263d55307 308
AnnaBridge 167:e84263d55307 309 static inline void clear_tick_interrupt();
AnnaBridge 167:e84263d55307 310 #endif
<> 149:156823d33999 311
AnnaBridge 167:e84263d55307 312 #ifndef RTC1_CONFIG_FREQUENCY
AnnaBridge 167:e84263d55307 313 #define RTC1_CONFIG_FREQUENCY 32678 // [Hz]
AnnaBridge 167:e84263d55307 314 #endif
<> 149:156823d33999 315
AnnaBridge 167:e84263d55307 316
<> 149:156823d33999 317
AnnaBridge 167:e84263d55307 318 void COMMON_RTC_IRQ_HANDLER(void)
<> 149:156823d33999 319 {
AnnaBridge 167:e84263d55307 320 if(nrf_rtc_event_pending(COMMON_RTC_INSTANCE, OS_TICK_EVENT)) {
AnnaBridge 167:e84263d55307 321 #ifdef MBED_CONF_RTOS_PRESENT
AnnaBridge 167:e84263d55307 322 clear_tick_interrupt();
AnnaBridge 167:e84263d55307 323 // Trigger the SysTick_Handler just after exit form RTC Handler.
AnnaBridge 167:e84263d55307 324 NVIC_SetPendingIRQ(SWI3_IRQn);
<> 149:156823d33999 325
AnnaBridge 167:e84263d55307 326 nrf_gpio_pin_set(11);
AnnaBridge 167:e84263d55307 327 #endif
AnnaBridge 167:e84263d55307 328 } else {
AnnaBridge 167:e84263d55307 329 common_rtc_irq_handler();
AnnaBridge 167:e84263d55307 330 }
<> 149:156823d33999 331 }
<> 149:156823d33999 332
<> 149:156823d33999 333
AnnaBridge 167:e84263d55307 334 #ifdef MBED_CONF_RTOS_PRESENT
<> 149:156823d33999 335 /**
<> 149:156823d33999 336 * Return the next number of clock cycle needed for the next tick.
AnnaBridge 167:e84263d55307 337 * @note This function has been carefully optimized for a systick occurring every 1000us.
<> 149:156823d33999 338 */
AnnaBridge 165:e614a9f1c9e2 339 static uint32_t get_next_tick_cc_delta()
AnnaBridge 165:e614a9f1c9e2 340 {
<> 149:156823d33999 341 uint32_t delta = 0;
<> 149:156823d33999 342
AnnaBridge 167:e84263d55307 343 if (osRtxConfig.tick_freq != 1000) {
<> 149:156823d33999 344 // In RTX, by default SYSTICK is is used.
<> 149:156823d33999 345 // A tick event is generated every os_trv + 1 clock cycles of the system timer.
AnnaBridge 167:e84263d55307 346 delta = os_rtc_period;
<> 149:156823d33999 347 } else {
<> 149:156823d33999 348 // If the clockrate is set to 1000us then 1000 tick should happen every second.
<> 149:156823d33999 349 // Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31.
<> 149:156823d33999 350 // If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be
<> 149:156823d33999 351 // generated in 32000 clock cycle instead of 32768 clock cycles.
<> 149:156823d33999 352 // As a result, if a user schedule an OS timer to start in 100s, the timer will start
<> 149:156823d33999 353 // instead after 97.656s
<> 149:156823d33999 354 // The code below fix this issue, a clock rate of 1000s will generate 1000 ticks in 32768
<> 149:156823d33999 355 // clock cycles.
<> 149:156823d33999 356 // The strategy is simple, for 1000 ticks:
<> 149:156823d33999 357 // * 768 ticks will occur 33 clock cycles after the previous tick
<> 149:156823d33999 358 // * 232 ticks will occur 32 clock cycles after the previous tick
<> 149:156823d33999 359 // By default every delta is equal to 33.
<> 149:156823d33999 360 // Every five ticks (20%, 200 delta in one second), the delta is equal to 32
<> 149:156823d33999 361 // The remaining (32) deltas equal to 32 are distributed using primes numbers.
<> 149:156823d33999 362 static uint32_t counter = 0;
<> 149:156823d33999 363 if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) {
<> 149:156823d33999 364 delta = 32;
<> 149:156823d33999 365 } else {
<> 149:156823d33999 366 delta = 33;
<> 149:156823d33999 367 }
<> 149:156823d33999 368 ++counter;
<> 149:156823d33999 369 if (counter == 1000) {
<> 149:156823d33999 370 counter = 0;
<> 149:156823d33999 371 }
<> 149:156823d33999 372 }
<> 149:156823d33999 373 return delta;
<> 149:156823d33999 374 }
<> 149:156823d33999 375
AnnaBridge 165:e614a9f1c9e2 376 static inline void clear_tick_interrupt()
AnnaBridge 165:e614a9f1c9e2 377 {
<> 149:156823d33999 378 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
<> 149:156823d33999 379 nrf_rtc_event_disable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
<> 149:156823d33999 380 }
<> 149:156823d33999 381
<> 149:156823d33999 382 /**
<> 149:156823d33999 383 * Indicate if a value is included in a range which can be wrapped.
<> 149:156823d33999 384 * @param begin start of the range
<> 149:156823d33999 385 * @param end end of the range
<> 149:156823d33999 386 * @param val value to check
<> 149:156823d33999 387 * @return true if the value is included in the range and false otherwise.
<> 149:156823d33999 388 */
AnnaBridge 165:e614a9f1c9e2 389 static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val)
AnnaBridge 165:e614a9f1c9e2 390 {
<> 149:156823d33999 391 // regular case, begin < end
<> 149:156823d33999 392 // return true if begin <= val < end
<> 149:156823d33999 393 if (begin < end) {
<> 149:156823d33999 394 if (begin <= val && val < end) {
<> 149:156823d33999 395 return true;
<> 149:156823d33999 396 } else {
<> 149:156823d33999 397 return false;
<> 149:156823d33999 398 }
<> 149:156823d33999 399 } else {
<> 149:156823d33999 400 // In this case end < begin because it has wrap around the limits
<> 149:156823d33999 401 // return false if end < val < begin
<> 149:156823d33999 402 if (end < val && val < begin) {
<> 149:156823d33999 403 return false;
<> 149:156823d33999 404 } else {
<> 149:156823d33999 405 return true;
<> 149:156823d33999 406 }
<> 149:156823d33999 407 }
<> 149:156823d33999 408
<> 149:156823d33999 409 }
<> 149:156823d33999 410
<> 149:156823d33999 411 /**
<> 149:156823d33999 412 * Register the next tick.
<> 149:156823d33999 413 */
AnnaBridge 165:e614a9f1c9e2 414 static void register_next_tick()
AnnaBridge 165:e614a9f1c9e2 415 {
<> 149:156823d33999 416 previous_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
<> 149:156823d33999 417 uint32_t delta = get_next_tick_cc_delta();
<> 149:156823d33999 418 uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL;
<> 149:156823d33999 419
<> 149:156823d33999 420 // Disable irq directly for few cycles,
<> 149:156823d33999 421 // Validation of the new CC value against the COUNTER,
<> 149:156823d33999 422 // Setting the new CC value and enabling CC IRQ should be an atomic operation
<> 149:156823d33999 423 // Otherwise, there is a possibility to set an invalid CC value because
<> 149:156823d33999 424 // the RTC1 keeps running.
<> 149:156823d33999 425 // This code is very short 20-38 cycles in the worst case, it shouldn't
<> 149:156823d33999 426 // disturb softdevice.
<> 149:156823d33999 427 __disable_irq();
<> 149:156823d33999 428 uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
<> 149:156823d33999 429
<> 149:156823d33999 430 // If an overflow occur, set the next tick in COUNTER + delta clock cycles
<> 149:156823d33999 431 if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter + 1) == false) {
<> 149:156823d33999 432 new_compare_value = current_counter + delta;
<> 149:156823d33999 433 }
<> 149:156823d33999 434 nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, new_compare_value);
<> 149:156823d33999 435 // Enable generation of the compare event for the value set above (this
<> 149:156823d33999 436 // event will trigger the interrupt).
<> 149:156823d33999 437 nrf_rtc_event_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
<> 149:156823d33999 438 __enable_irq();
<> 149:156823d33999 439 }
<> 149:156823d33999 440
AnnaBridge 167:e84263d55307 441
<> 149:156823d33999 442 /**
<> 149:156823d33999 443 * Initialize alternative hardware timer as RTX kernel timer
<> 149:156823d33999 444 * This function is directly called by RTX.
<> 149:156823d33999 445 * @note this function shouldn't be called directly.
<> 149:156823d33999 446 * @return IRQ number of the alternative hardware timer
<> 149:156823d33999 447 */
AnnaBridge 167:e84263d55307 448 int32_t osRtxSysTimerSetup(void)
<> 149:156823d33999 449 {
<> 149:156823d33999 450 common_rtc_init();
AnnaBridge 167:e84263d55307 451
AnnaBridge 167:e84263d55307 452 os_rtc_period = (RTC1_CONFIG_FREQUENCY) / osRtxConfig.tick_freq;
<> 149:156823d33999 453
<> 149:156823d33999 454 return nrf_drv_get_IRQn(COMMON_RTC_INSTANCE);
<> 149:156823d33999 455 }
<> 149:156823d33999 456
AnnaBridge 167:e84263d55307 457 // Start SysTickt timer emulation
AnnaBridge 167:e84263d55307 458 void osRtxSysTimerEnable(void)
AnnaBridge 167:e84263d55307 459 {
AnnaBridge 167:e84263d55307 460 nrf_rtc_int_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
AnnaBridge 167:e84263d55307 461
AnnaBridge 167:e84263d55307 462 uint32_t current_cnt = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
AnnaBridge 167:e84263d55307 463 nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, current_cnt);
AnnaBridge 167:e84263d55307 464 register_next_tick();
AnnaBridge 167:e84263d55307 465
AnnaBridge 167:e84263d55307 466 NVIC_SetVector(SWI3_IRQn, (uint32_t)SysTick_Handler);
AnnaBridge 167:e84263d55307 467 NVIC_SetPriority(SWI3_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Emulated Systick Interrupt */
AnnaBridge 167:e84263d55307 468 NVIC_EnableIRQ(SWI3_IRQn);
AnnaBridge 167:e84263d55307 469 }
AnnaBridge 167:e84263d55307 470
AnnaBridge 167:e84263d55307 471 // Stop SysTickt timer emulation
AnnaBridge 167:e84263d55307 472 void osRtxSysTimerDisable(void)
AnnaBridge 167:e84263d55307 473 {
AnnaBridge 167:e84263d55307 474 nrf_rtc_int_disable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
AnnaBridge 167:e84263d55307 475
AnnaBridge 167:e84263d55307 476 // RTC1 is free runing. osRtxSysTimerGetCount will return proper frozen value
AnnaBridge 167:e84263d55307 477 // thanks to geting frozen value instead of RTC1 counter value
AnnaBridge 167:e84263d55307 478 frozen_sub_tick = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
AnnaBridge 167:e84263d55307 479 }
AnnaBridge 167:e84263d55307 480
AnnaBridge 167:e84263d55307 481
AnnaBridge 167:e84263d55307 482
<> 149:156823d33999 483 /**
<> 149:156823d33999 484 * Acknowledge the tick interrupt.
<> 149:156823d33999 485 * This function is called by the function OS_Tick_Handler of RTX.
<> 149:156823d33999 486 * @note this function shouldn't be called directly.
<> 149:156823d33999 487 */
AnnaBridge 167:e84263d55307 488 void osRtxSysTimerAckIRQ(void)
<> 149:156823d33999 489 {
<> 149:156823d33999 490 register_next_tick();
<> 149:156823d33999 491 }
<> 149:156823d33999 492
AnnaBridge 167:e84263d55307 493 // provide a free running incremental value over the entire 32-bit range
AnnaBridge 167:e84263d55307 494 uint32_t osRtxSysTimerGetCount(void)
AnnaBridge 165:e614a9f1c9e2 495 {
AnnaBridge 167:e84263d55307 496 uint32_t current_cnt;
AnnaBridge 167:e84263d55307 497 uint32_t sub_tick;
<> 149:156823d33999 498
AnnaBridge 167:e84263d55307 499 if (nrf_rtc_int_is_enabled(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK)) {
AnnaBridge 167:e84263d55307 500 // system timer is enabled
AnnaBridge 167:e84263d55307 501 current_cnt = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
AnnaBridge 167:e84263d55307 502
AnnaBridge 167:e84263d55307 503 if (current_cnt >= previous_tick_cc_value) {
AnnaBridge 167:e84263d55307 504 //0 prev current MAX
AnnaBridge 167:e84263d55307 505 //|------|---------|------------|---->
AnnaBridge 167:e84263d55307 506 sub_tick = current_cnt - previous_tick_cc_value;
AnnaBridge 167:e84263d55307 507 } else {
AnnaBridge 167:e84263d55307 508 //0 current prev MAX
AnnaBridge 167:e84263d55307 509 //|------|---------|------------|---->
AnnaBridge 167:e84263d55307 510 sub_tick = MAX_RTC_COUNTER_VAL - previous_tick_cc_value + current_cnt;
AnnaBridge 167:e84263d55307 511 }
AnnaBridge 167:e84263d55307 512 } else { // system timer is disabled
AnnaBridge 167:e84263d55307 513 sub_tick = frozen_sub_tick;
AnnaBridge 167:e84263d55307 514 }
AnnaBridge 167:e84263d55307 515
AnnaBridge 167:e84263d55307 516 return (os_rtc_period * osRtxInfo.kernel.tick) + sub_tick;
<> 149:156823d33999 517 }
<> 149:156823d33999 518
AnnaBridge 167:e84263d55307 519 // Timer Tick frequency
AnnaBridge 167:e84263d55307 520 uint32_t osRtxSysTimerGetFreq (void) {
AnnaBridge 167:e84263d55307 521 return RTC1_CONFIG_FREQUENCY;
<> 149:156823d33999 522 }
<> 149:156823d33999 523
AnnaBridge 167:e84263d55307 524 #endif // #ifdef MBED_CONF_RTOS_PRESENT
AnnaBridge 167:e84263d55307 525
<> 149:156823d33999 526 #endif // defined(TARGET_MCU_NRF51822)