fsl_xcvr_zgbe_config.c

00001 /*
00002  * Copyright (c) 2015, Freescale Semiconductor, Inc.
00003  * Copyright 2016-2017 NXP
00004  *
00005  * Redistribution and use in source and binary forms, with or without modification,
00006  * are permitted provided that the following conditions are met:
00007  *
00008  * o Redistributions of source code must retain the above copyright notice, this list
00009  *   of conditions and the following disclaimer.
00010  *
00011  * o Redistributions in binary form must reproduce the above copyright notice, this
00012  *   list of conditions and the following disclaimer in the documentation and/or
00013  *   other materials provided with the distribution.
00014  *
00015  * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00016  *   contributors may be used to endorse or promote products derived from this
00017  *   software without specific prior written permission.
00018  *
00019  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00020  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00021  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00022  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00023  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00024  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00025  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00026  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00027  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00028  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00029  */
00030 
00031 #include "fsl_xcvr.h "
00032 
00033 /*******************************************************************************
00034  * Definitions
00035  ******************************************************************************/
00036 
00037 /*******************************************************************************
00038  * Prototypes
00039  ******************************************************************************/
00040 
00041 /*******************************************************************************
00042  * Variables
00043  ******************************************************************************/
00044 
00045 /*******************************************************************************
00046  * Code
00047  ******************************************************************************/
00048 const xcvr_mode_config_t zgbe_mode_config =
00049 {
00050     .radio_mode = ZIGBEE_MODE,
00051     .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_ZigBee_MASK,
00052 
00053     /* XCVR_MISC configs */
00054     .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
00055                       XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
00056                       XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
00057     .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(4) |
00058                       XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
00059                       XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(2),
00060 
00061     /* XCVR_PHY configs */
00062     .phy_pre_ref0_init = 0x0, /* Not used in Zigbee */
00063     .phy_pre_ref1_init = 0x0, /* Not used in Zigbee */
00064     .phy_pre_ref2_init = 0x0, /* Not used in Zigbee */
00065 
00066     .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) |
00067                      XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 
00068                      XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
00069                      XCVR_PHY_CFG1_BSM_EN_BLE(0) |
00070                      XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
00071                      XCVR_PHY_CFG1_CTS_THRESH(0xC0) |
00072                      XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
00073 
00074     .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
00075 #if !RADIO_IS_GEN_2P1
00076                     | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
00077 #endif /* !RADIO_IS_GEN_2P1 */
00078     ,
00079 
00080     /* XCVR_PLL_DIG configs */
00081 
00082     /* XCVR_RX_DIG configs */
00083     .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */
00084                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
00085                               XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
00086 
00087     .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */
00088                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
00089 
00090     .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
00091     /* XCVR_TSM configs */
00092 #if (DATA_PADDING_EN)
00093     .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+ZGBE_TX_DIG_EN_TX_HI_ADJ), /* DATA_PADDING adjustments are specified relative to the non-Zigbee base timing */ 
00094 #else
00095     .tsm_timing_35_init = B0(ZGBE_TX_DIG_EN_ASSERT),
00096 #endif /* (DATA_PADDING_EN) */
00097 
00098     /* XCVR_TX_DIG configs */
00099     .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
00100                     XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) |
00101                     XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
00102                     XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
00103                     XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
00104                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
00105                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
00106                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
00107                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0) ,
00108     .tx_gfsk_coeff1_26mhz = 0,
00109     .tx_gfsk_coeff2_26mhz = 0,
00110     .tx_gfsk_coeff1_32mhz = 0,
00111     .tx_gfsk_coeff2_32mhz = 0,
00112 };
00113 
00114 const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config =
00115 {
00116     .radio_mode = ZIGBEE_MODE,
00117     .data_rate = DR_500KBPS,
00118     
00119     .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
00120     .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */
00121 
00122     .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
00123     .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(1) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(1), /* BBA_BW_SEL and BBA2_BW_SEL */ 
00124     .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
00125     .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(1), /*TZA_BW_SEL */ 
00126 
00127     .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
00128                      XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
00129                        
00130     /* AGC configs */
00131     .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(8) |
00132                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00133                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00134                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00135                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) |
00136                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00137     .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) |
00138                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00139                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00140                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00141                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) |
00142                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00143 
00144     /* All constant values are represented as 16 bits, register writes will remove unused bits */
00145     .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF,
00146     .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF,
00147     .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0002,
00148     .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0008,
00149     .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A,
00150     .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0000,
00151     .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE8,
00152     .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7,
00153     .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFE6,
00154     .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0022,
00155     .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0075,
00156     .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00B2,
00157 
00158      /* IEEE 802.15.4 32MHz Channel Filter -- 1.55/1.25/5/0.97/B5 */
00159     .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF,
00160     .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF,
00161     .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005,
00162     .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0004,
00163     .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2,
00164     .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2,
00165     .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001D,
00166     .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0025,
00167     .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFCE,
00168     .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFA1,
00169     .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0040,
00170     .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0124,
00171 
00172     .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
00173                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
00174                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
00175                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
00176                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
00177                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
00178                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
00179                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
00180     .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
00181                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
00182                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
00183                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
00184                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
00185                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
00186 
00187     .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
00188     .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
00189 };
00190 
00191 /* CUSTOM datarate dependent config structure for ONLY 802.15.4 */
00192 /*!
00193  * @brief  XCVR 500K bps DATA RATE specific configure structure
00194  */
00195 const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config =
00196 {
00197     .data_rate = DR_500KBPS,
00198     .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) |
00199                        XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) |
00200                        XCVR_PHY_EL_CFG_EL_INTERVAL(0x10) ,
00201     .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) |
00202                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
00203     .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) |
00204                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
00205 
00206     .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(13) |
00207                              XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
00208     .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) |
00209                              XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
00210 
00211     .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) |
00212                               XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29),
00213     .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(21) |
00214                               XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(47),
00215 
00216     .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
00217                               XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
00218                               XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) |
00219                               XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
00220                               XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
00221                               XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
00222                               XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
00223 
00224     .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
00225                               XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
00226                               XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) |
00227                               XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
00228                               XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
00229                               XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
00230                               XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
00231 
00232     .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) |
00233                                XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) |
00234                                XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2),
00235     .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(1) |
00236                                XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) |
00237                                XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1),
00238 
00239     .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) |
00240                            XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4),
00241     .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(48) |
00242                            XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(0),
00243 };
00244