fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c

00001 /*
00002  * Copyright 2016-2017 NXP
00003  *
00004  * Redistribution and use in source and binary forms, with or without modification,
00005  * are permitted provided that the following conditions are met:
00006  *
00007  * o Redistributions of source code must retain the above copyright notice, this list
00008  *   of conditions and the following disclaimer.
00009  *
00010  * o Redistributions in binary form must reproduce the above copyright notice, this
00011  *   list of conditions and the following disclaimer in the documentation and/or
00012  *   other materials provided with the distribution.
00013  *
00014  * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00015  *   contributors may be used to endorse or promote products derived from this
00016  *   software without specific prior written permission.
00017  *
00018  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00019  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00020  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00021  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00022  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00023  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00024  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00025  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00026  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00027  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00028  */
00029 
00030 #include "fsl_xcvr.h "
00031 
00032 /*******************************************************************************
00033  * Definitions
00034  ******************************************************************************/
00035 
00036 /*******************************************************************************
00037  * Prototypes
00038  ******************************************************************************/
00039 
00040 /*******************************************************************************
00041  * Variables
00042  ******************************************************************************/
00043 
00044 /*******************************************************************************
00045  * Code
00046  ******************************************************************************/
00047 /* MODE only configuration */
00048 const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config =
00049 {
00050     .radio_mode = GFSK_BT_0p3_h_0p5,
00051     .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
00052 
00053     /* XCVR_MISC configs */
00054     .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
00055                       XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
00056                       XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
00057     .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
00058                       XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
00059                       XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
00060 
00061     /* XCVR_PHY configs */
00062     .phy_pre_ref0_init = 0x7BCDEB39,
00063     .phy_pre_ref1_init = 0xCEF7DEF7,
00064     .phy_pre_ref2_init = 0x0000CEB7,
00065 
00066     .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
00067                      XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
00068                      XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
00069                      XCVR_PHY_CFG1_BSM_EN_BLE(0) |
00070                      XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
00071                      XCVR_PHY_CFG1_CTS_THRESH(0xda) |
00072                      XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
00073 
00074     .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
00075 #if !RADIO_IS_GEN_2P1
00076                      | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
00077 #endif /* !RADIO_IS_GEN_2P1 */
00078     ,
00079 
00080     /* XCVR_RX_DIG configs */
00081     .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
00082                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
00083                               XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
00084 
00085     .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
00086                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
00087 
00088     .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
00089 
00090     /* XCVR_TSM configs */
00091 #if (DATA_PADDING_EN)
00092     .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
00093 #else
00094     .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
00095 #endif /* (DATA_PADDING_EN) */
00096 
00097     /* XCVR_TX_DIG configs */
00098     .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
00099                     XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) |
00100                     XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
00101                     XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */
00102                     XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
00103                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
00104                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
00105                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
00106                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
00107     .tx_gfsk_coeff1_26mhz = (107U) << 0 | /* coeff 2/13 */
00108                             (164U) << 7 | /* coeff 6/9 */
00109                             (125U) << 16 | /* coef 3/12 */
00110                             (169U) << 23, /* coeff 7/8 */
00111     .tx_gfsk_coeff2_26mhz = (72U) << 0 | /* coeff 0/15 */
00112                             (90U) << 8 | /* coeff 1/14 */
00113                             (141U) << 16 | /* coeff 4/11 */
00114                             (155U) << 24, /* coeff 5/10 */
00115     .tx_gfsk_coeff1_32mhz = (70U) << 0 | /* coeff 2/13 */
00116                             (216U) << 7 | /* coeff 6/9 */
00117                             (105U) << 16 | /* coef 3/12 */
00118                             (233U) << 23, /* coeff 7/8 */
00119     .tx_gfsk_coeff2_32mhz = (25U) << 0 | /* coeff 0/15 */
00120                             (44U) << 8 | /* coeff 1/14 */
00121                             (145U) << 16 | /* coeff 4/11 */
00122                             (184U) << 24, /* coeff 5/10 */
00123 };
00124 
00125 /* MODE & DATA RATE combined configuration */
00126 const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config =
00127 {
00128     .radio_mode = GFSK_BT_0p3_h_0p5,
00129     .data_rate = DR_1MBPS,
00130 
00131     .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
00132     .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
00133     .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
00134     .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ 
00135     .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
00136     .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ 
00137 
00138     .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
00139                      XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
00140 
00141     /* AGC configs */
00142     .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) |
00143                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00144                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00145                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00146                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00147                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00148     .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
00149                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00150                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00151                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00152                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00153                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00154 
00155     /* All constant values are represented as 16 bits, register writes will remove unused bits */
00156     .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF,
00157     .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD,
00158     .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF9,
00159     .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF4,
00160     .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF2,
00161     .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF5,
00162     .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0000,
00163     .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0011,
00164     .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0028,
00165     .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041,
00166     .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0055,
00167     .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0061,
00168 
00169     /* 32MHz Channel Filter */
00170     .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
00171     .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF,
00172     .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFA,
00173     .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4,
00174     .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF0,
00175     .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0,
00176     .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF9,
00177     .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000B,
00178     .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0025,
00179     .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0043,
00180     .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005C,
00181     .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006A,
00182 
00183     .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
00184                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
00185                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
00186                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
00187                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
00188                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
00189                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
00190                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
00191     .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
00192                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
00193                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
00194                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
00195                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
00196                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
00197 
00198     .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
00199     .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
00200 };
00201 
00202 const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config =
00203 {
00204     .radio_mode = GFSK_BT_0p3_h_0p5,
00205     .data_rate = DR_500KBPS,
00206 
00207     .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
00208     .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
00209     .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
00210     .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
00211     .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
00212     .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
00213 
00214     .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
00215                      XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
00216 
00217     /* AGC configs */
00218     .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
00219                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00220                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00221                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00222                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00223                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00224     .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
00225                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00226                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00227                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00228                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00229                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00230 
00231     /* All constant values are represented as 16 bits, register writes will remove unused bits */
00232     .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
00233     .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000,
00234     .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFC,
00235     .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF7,
00236     .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF3,
00237     .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF2,
00238     .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF9,
00239     .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A,
00240     .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0023,
00241     .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0040,
00242     .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059,
00243     .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0068,
00244 
00245     /* 32MHz Channel Filter */
00246     .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
00247     .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0001,
00248     .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFF,
00249     .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA,
00250     .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF3,
00251     .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEF,
00252     .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF3,
00253     .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001,
00254     .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001D,
00255     .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x003F,
00256     .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F,
00257     .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0072,
00258 
00259     .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
00260                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
00261                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
00262                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
00263                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
00264                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
00265                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
00266                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
00267     .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
00268                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
00269                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
00270                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
00271                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
00272                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
00273 
00274     .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
00275     .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
00276 };
00277 
00278 const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config =
00279 {
00280     .radio_mode = GFSK_BT_0p3_h_0p5,
00281     .data_rate = DR_250KBPS,
00282     
00283     .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
00284     .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
00285     .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
00286     .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
00287     .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
00288     .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
00289              
00290     .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
00291                      XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
00292 
00293     /* AGC configs */
00294     .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
00295                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00296                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
00297                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00298                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00299                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00300     .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
00301                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00302                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00303                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00304                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00305                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00306 
00307     /* All constant values are represented as 16 bits, register writes will remove unused bits */
00308     .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
00309     .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003,
00310     .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0003,
00311     .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFF,
00312     .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF7,
00313     .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEE,
00314     .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC,
00315     .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFF7,
00316     .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0014,
00317     .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003C,
00318     .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0064,
00319     .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007D,
00320 
00321     /* 32MHz Channel Filter */
00322     .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
00323     .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
00324     .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005,
00325     .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003,
00326     .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC,
00327     .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0,
00328     .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8,
00329     .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF,
00330     .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B,
00331     .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038,
00332     .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068,
00333     .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086,
00334 
00335     .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
00336                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
00337                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
00338                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
00339                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
00340                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
00341                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
00342                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
00343     .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
00344                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
00345                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
00346                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
00347                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
00348                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1),
00349 
00350     .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
00351     .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
00352 };
00353