fsl_xcvr_ant_config.c

00001 /*
00002  * Copyright (c) 2015, Freescale Semiconductor, Inc.
00003  * Copyright 2016-2017 NXP
00004  *
00005  * Redistribution and use in source and binary forms, with or without modification,
00006  * are permitted provided that the following conditions are met:
00007  *
00008  * o Redistributions of source code must retain the above copyright notice, this list
00009  *   of conditions and the following disclaimer.
00010  *
00011  * o Redistributions in binary form must reproduce the above copyright notice, this
00012  *   list of conditions and the following disclaimer in the documentation and/or
00013  *   other materials provided with the distribution.
00014  *
00015  * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00016  *   contributors may be used to endorse or promote products derived from this
00017  *   software without specific prior written permission.
00018  *
00019  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00020  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00021  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00022  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00023  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00024  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00025  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00026  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00027  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00028  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00029  */
00030 
00031 #include "fsl_xcvr.h "
00032 
00033 /*******************************************************************************
00034  * Definitions
00035  ******************************************************************************/
00036 
00037 /*******************************************************************************
00038  * Prototypes
00039  ******************************************************************************/
00040 
00041 /*******************************************************************************
00042  * Variables
00043  ******************************************************************************/
00044 
00045 /*******************************************************************************
00046  * Code
00047  ******************************************************************************/
00048 const xcvr_mode_config_t ant_mode_config =
00049 {
00050     .radio_mode = ANT_MODE,
00051     .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK 
00052 #if !RADIO_IS_GEN_2P1
00053     | SIM_SCGC5_ANT_MASK
00054 #endif /* !RADIO_IS_GEN_2P1 */
00055     ,
00056 
00057     /* XCVR_MISC configs */
00058     .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
00059                       XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
00060                       XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
00061     .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(3) |
00062                       XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
00063                       XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
00064 
00065     /* XCVR_PHY configs */
00066     .phy_pre_ref0_init = RW0PS(0, 0x1B) |
00067                          RW0PS(1, 0x1CU) |
00068                          RW0PS(2, 0x1CU) |
00069                          RW0PS(3, 0x1CU) |
00070                          RW0PS(4, 0x1DU) |
00071                          RW0PS(5, 0x1DU) |
00072                          RW0PS(6, 0x1EU & 0x3U), /* Phase info #6 overlaps two initialization words - only need two lowest bits*/
00073     .phy_pre_ref1_init = (0x1E) >> 2 | /* Phase info #6 overlaps two initialization words  - manually compute the shift */
00074                          RW1PS(7, 0x1EU) |
00075                          RW1PS(8, 0x1EU) |
00076                          RW1PS(9, 0x1EU) |
00077                          RW1PS(10, 0x1EU) |
00078                          RW1PS(11, 0x1DU) |
00079                          RW1PS(12, 0x1DU & 0xFU), /* Phase info #12 overlaps two initialization words */
00080     .phy_pre_ref2_init = (0x1D) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift */
00081                          RW2PS(13, 0x1CU) |
00082                          RW2PS(14, 0x1CU) |
00083                          RW2PS(15, 0x1CU),
00084 
00085     .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
00086                      XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 
00087                      XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
00088                      XCVR_PHY_CFG1_BSM_EN_BLE(0) |
00089                      XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
00090                      XCVR_PHY_CFG1_CTS_THRESH(0xF8) |
00091                      XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
00092 
00093     .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) 
00094 #if !RADIO_IS_GEN_2P1
00095                      | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
00096 #endif /* !RADIO_IS_GEN_2P1 */
00097     ,
00098 
00099     /* XCVR_RX_DIG configs */
00100     .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
00101                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
00102                               XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
00103 
00104     .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
00105                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
00106 
00107     .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
00108     /* XCVR_TSM configs */
00109 #if (DATA_PADDING_EN)
00110     .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
00111 #else
00112     .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
00113 #endif /* (DATA_PADDING_EN) */
00114 
00115     /* XCVR_TX_DIG configs */
00116     .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
00117                     XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) |
00118                     XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
00119                     XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
00120                     XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
00121                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
00122                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
00123                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
00124                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
00125     .tx_gfsk_coeff1_26mhz = 0,
00126     .tx_gfsk_coeff2_26mhz = 0,
00127     .tx_gfsk_coeff1_32mhz = 0,
00128     .tx_gfsk_coeff2_32mhz = 0,
00129 };
00130 
00131 /* MODE & DATA RATE combined configuration */
00132 const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config =
00133 {
00134     .radio_mode = ANT_MODE,
00135     .data_rate = DR_1MBPS,
00136 
00137     .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
00138     .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
00139     .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
00140     .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
00141     .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
00142     .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
00143 
00144     .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
00145                      XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
00146 
00147     /* AGC configs */
00148     .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
00149                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00150                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00151                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00152                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00153                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00154     .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) |
00155                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00156                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00157                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00158                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00159                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00160 
00161     /* All constant values are represented as 16 bits, register writes will remove unused bits */
00162     .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB,
00163     .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5,
00164     .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0,
00165     .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC,
00166     .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC,
00167     .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3,
00168     .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001,
00169     .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016,
00170     .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F,
00171     .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049,
00172     .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D,
00173     .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069,
00174 
00175      /* ANT 32MHz Channel Filter */
00176     .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9,
00177     .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4,
00178     .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED,
00179     .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7,
00180     .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7,
00181     .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE,
00182     .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD,
00183     .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015,
00184     .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031,
00185     .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E,
00186     .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066,
00187     .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073,
00188 
00189     .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
00190                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
00191                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
00192                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
00193                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
00194                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
00195                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
00196                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
00197     .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
00198                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
00199                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
00200                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
00201                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
00202                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
00203 
00204     .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
00205     .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
00206 };
00207