Port from Avnet's Internet Of Things full WiGo demo: SmartConfig - WebServer - Exosite - Android sensor Fusion App

Dependencies:   NVIC_set_all_priorities mbed cc3000_hostdriver_mbedsocket TEMT6200 TSI Wi-Go_eCompass_Lib_V3 WiGo_BattCharger

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Show/hide line numbers I2C_busreset.cpp Source File

I2C_busreset.cpp

00001 /**************************************************************************************************
00002  *****                                                                                        *****
00003  *****  Name: KL25Z I2C_busreset.cpp                                                          *****
00004  *****  Date: 24/11/2013                                                                      *****
00005  *****  Auth: Frank Vannieuwkerke                                                             *****
00006  *****  Func: library for unblocking I2C bus on KL25Z board                                   *****
00007  *****  Info: MPL3115A2-AN4481                                                                *****
00008  **************************************************************************************************/
00009 
00010 #include "I2C_busreset.h"
00011 
00012 void I2C_busreset(void)
00013 {
00014     I2C0->C1 &= 0x7f;                 // Disable I2C0 bus
00015     I2C1->C1 &= 0x7f;                 // Disable I2C1 bus
00016     PORTE->PCR[1] = PORT_PCR_MUX(1);  // PTE1 Alt1 (pin)
00017     PORTE->PCR[0] = PORT_PCR_MUX(1);  // PTE0 Alt1 (pin)
00018     PORTE->PCR[24] = PORT_PCR_MUX(1); // PTE24 Alt1 (pin)
00019     PORTE->PCR[25] = PORT_PCR_MUX(1); // PTE25 Alt1 (pin)
00020     if((PTE->PDIR & 0x3) != 3)        // When PTE0 / PTE1 are not 1 : I2C1 bus lock-up
00021     {
00022         PTE->PDDR |= 0x2;             // Set PTE1 as a GPIO output so we can bit bang it
00023         PTE->PDOR |= 0x2;             // Set PTE1 (SCL) pin high;
00024         wait_ms(1);
00025         while(!(PTE->PDIR & 0x1))     // bit bang SCL until the offending device releases the bus
00026         {   
00027             PTE->PDOR &= 0xfffffffd;  // Set PTE1 (SCL) pin low;
00028             wait_ms(1);
00029             PTE->PDOR |= 0x2;         // Set PTE1 (SCL) pin high;
00030             wait_ms(1);
00031         }
00032     }
00033     if((PTE->PDIR & 0x03000000) != 0x03000000)  // When PTE24 / PTE25 are not 1 : I2C0 bus lock-up
00034     {
00035         PTE->PDDR |= 0x01000000;      // Set PTE24 as a GPIO output so we can bit bang it
00036         PTE->PDOR |= 0x01000000;      // Set PTE24 (SCL) pin high;
00037         wait_ms(1);
00038         while(!(PTE->PDIR & 0x1))     // bit bang SCL until the offending device releases the bus
00039         {   
00040             PTE->PDOR &= 0xfeffffff;  // Set PTE24 (SCL) pin low;
00041             wait_ms(1);
00042             PTE->PDOR |= 0x01000000;  // Set PTE24 (SCL) pin high;
00043             wait_ms(1);
00044         }
00045     }
00046     // Reinstate I2C bus pins
00047     PORTE->PCR[1] = PORT_PCR_MUX(6);  // PTE1 Alt6 (SCL)
00048     PORTE->PCR[0] = PORT_PCR_MUX(6);  // PTE0 Alt6 (SDA)
00049     PORTE->PCR[24] = PORT_PCR_MUX(5); // PTE24 Alt6 (SCL)
00050     PORTE->PCR[25] = PORT_PCR_MUX(5); // PTE25 Alt6 (SDA)
00051     I2C0->C1 |= 0x80;                 // Enable I2C0 bus
00052     I2C1->C1 |= 0x80;                 // Enable I2C1 bus
00053 }
00054 
00055 
00056 
00057 
00058