Toyomasa Watarai / Mbed OS armcc_info

Describes predefine macros for mbed online compiler (armcc)

mbed/TARGET_LPC1114/core_cmFunc.h@6:40e873bbc5f7, 2017-03-16 (annotated)

Committer:
MACRUM
Date:
Thu Mar 16 21:58:09 2017 +0900
Revision:
6:40e873bbc5f7
Add licence header info

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MACRUM 6:40e873bbc5f7 1 /**************************************************************************//**
MACRUM 6:40e873bbc5f7 2 * @file core_cmFunc.h
MACRUM 6:40e873bbc5f7 3 * @brief CMSIS Cortex-M Core Function Access Header File
MACRUM 6:40e873bbc5f7 4 * @version V4.10
MACRUM 6:40e873bbc5f7 5 * @date 18. March 2015
MACRUM 6:40e873bbc5f7 6 *
MACRUM 6:40e873bbc5f7 7 * @note
MACRUM 6:40e873bbc5f7 8 *
MACRUM 6:40e873bbc5f7 9 ******************************************************************************/
MACRUM 6:40e873bbc5f7 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
MACRUM 6:40e873bbc5f7 11
MACRUM 6:40e873bbc5f7 12 All rights reserved.
MACRUM 6:40e873bbc5f7 13 Redistribution and use in source and binary forms, with or without
MACRUM 6:40e873bbc5f7 14 modification, are permitted provided that the following conditions are met:
MACRUM 6:40e873bbc5f7 15 - Redistributions of source code must retain the above copyright
MACRUM 6:40e873bbc5f7 16 notice, this list of conditions and the following disclaimer.
MACRUM 6:40e873bbc5f7 17 - Redistributions in binary form must reproduce the above copyright
MACRUM 6:40e873bbc5f7 18 notice, this list of conditions and the following disclaimer in the
MACRUM 6:40e873bbc5f7 19 documentation and/or other materials provided with the distribution.
MACRUM 6:40e873bbc5f7 20 - Neither the name of ARM nor the names of its contributors may be used
MACRUM 6:40e873bbc5f7 21 to endorse or promote products derived from this software without
MACRUM 6:40e873bbc5f7 22 specific prior written permission.
MACRUM 6:40e873bbc5f7 23 *
MACRUM 6:40e873bbc5f7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MACRUM 6:40e873bbc5f7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MACRUM 6:40e873bbc5f7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MACRUM 6:40e873bbc5f7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MACRUM 6:40e873bbc5f7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MACRUM 6:40e873bbc5f7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MACRUM 6:40e873bbc5f7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MACRUM 6:40e873bbc5f7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MACRUM 6:40e873bbc5f7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MACRUM 6:40e873bbc5f7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MACRUM 6:40e873bbc5f7 34 POSSIBILITY OF SUCH DAMAGE.
MACRUM 6:40e873bbc5f7 35 ---------------------------------------------------------------------------*/
MACRUM 6:40e873bbc5f7 36
MACRUM 6:40e873bbc5f7 37
MACRUM 6:40e873bbc5f7 38 #ifndef __CORE_CMFUNC_H
MACRUM 6:40e873bbc5f7 39 #define __CORE_CMFUNC_H
MACRUM 6:40e873bbc5f7 40
MACRUM 6:40e873bbc5f7 41
MACRUM 6:40e873bbc5f7 42 /* ########################### Core Function Access ########################### */
MACRUM 6:40e873bbc5f7 43 /** \ingroup CMSIS_Core_FunctionInterface
MACRUM 6:40e873bbc5f7 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
MACRUM 6:40e873bbc5f7 45 @{
MACRUM 6:40e873bbc5f7 46 */
MACRUM 6:40e873bbc5f7 47
MACRUM 6:40e873bbc5f7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MACRUM 6:40e873bbc5f7 49 /* ARM armcc specific functions */
MACRUM 6:40e873bbc5f7 50
MACRUM 6:40e873bbc5f7 51 #if (__ARMCC_VERSION < 400677)
MACRUM 6:40e873bbc5f7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
MACRUM 6:40e873bbc5f7 53 #endif
MACRUM 6:40e873bbc5f7 54
MACRUM 6:40e873bbc5f7 55 /* intrinsic void __enable_irq(); */
MACRUM 6:40e873bbc5f7 56 /* intrinsic void __disable_irq(); */
MACRUM 6:40e873bbc5f7 57
MACRUM 6:40e873bbc5f7 58 /** \brief Get Control Register
MACRUM 6:40e873bbc5f7 59
MACRUM 6:40e873bbc5f7 60 This function returns the content of the Control Register.
MACRUM 6:40e873bbc5f7 61
MACRUM 6:40e873bbc5f7 62 \return Control Register value
MACRUM 6:40e873bbc5f7 63 */
MACRUM 6:40e873bbc5f7 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
MACRUM 6:40e873bbc5f7 65 {
MACRUM 6:40e873bbc5f7 66 register uint32_t __regControl __ASM("control");
MACRUM 6:40e873bbc5f7 67 return(__regControl);
MACRUM 6:40e873bbc5f7 68 }
MACRUM 6:40e873bbc5f7 69
MACRUM 6:40e873bbc5f7 70
MACRUM 6:40e873bbc5f7 71 /** \brief Set Control Register
MACRUM 6:40e873bbc5f7 72
MACRUM 6:40e873bbc5f7 73 This function writes the given value to the Control Register.
MACRUM 6:40e873bbc5f7 74
MACRUM 6:40e873bbc5f7 75 \param [in] control Control Register value to set
MACRUM 6:40e873bbc5f7 76 */
MACRUM 6:40e873bbc5f7 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
MACRUM 6:40e873bbc5f7 78 {
MACRUM 6:40e873bbc5f7 79 register uint32_t __regControl __ASM("control");
MACRUM 6:40e873bbc5f7 80 __regControl = control;
MACRUM 6:40e873bbc5f7 81 }
MACRUM 6:40e873bbc5f7 82
MACRUM 6:40e873bbc5f7 83
MACRUM 6:40e873bbc5f7 84 /** \brief Get IPSR Register
MACRUM 6:40e873bbc5f7 85
MACRUM 6:40e873bbc5f7 86 This function returns the content of the IPSR Register.
MACRUM 6:40e873bbc5f7 87
MACRUM 6:40e873bbc5f7 88 \return IPSR Register value
MACRUM 6:40e873bbc5f7 89 */
MACRUM 6:40e873bbc5f7 90 __STATIC_INLINE uint32_t __get_IPSR(void)
MACRUM 6:40e873bbc5f7 91 {
MACRUM 6:40e873bbc5f7 92 register uint32_t __regIPSR __ASM("ipsr");
MACRUM 6:40e873bbc5f7 93 return(__regIPSR);
MACRUM 6:40e873bbc5f7 94 }
MACRUM 6:40e873bbc5f7 95
MACRUM 6:40e873bbc5f7 96
MACRUM 6:40e873bbc5f7 97 /** \brief Get APSR Register
MACRUM 6:40e873bbc5f7 98
MACRUM 6:40e873bbc5f7 99 This function returns the content of the APSR Register.
MACRUM 6:40e873bbc5f7 100
MACRUM 6:40e873bbc5f7 101 \return APSR Register value
MACRUM 6:40e873bbc5f7 102 */
MACRUM 6:40e873bbc5f7 103 __STATIC_INLINE uint32_t __get_APSR(void)
MACRUM 6:40e873bbc5f7 104 {
MACRUM 6:40e873bbc5f7 105 register uint32_t __regAPSR __ASM("apsr");
MACRUM 6:40e873bbc5f7 106 return(__regAPSR);
MACRUM 6:40e873bbc5f7 107 }
MACRUM 6:40e873bbc5f7 108
MACRUM 6:40e873bbc5f7 109
MACRUM 6:40e873bbc5f7 110 /** \brief Get xPSR Register
MACRUM 6:40e873bbc5f7 111
MACRUM 6:40e873bbc5f7 112 This function returns the content of the xPSR Register.
MACRUM 6:40e873bbc5f7 113
MACRUM 6:40e873bbc5f7 114 \return xPSR Register value
MACRUM 6:40e873bbc5f7 115 */
MACRUM 6:40e873bbc5f7 116 __STATIC_INLINE uint32_t __get_xPSR(void)
MACRUM 6:40e873bbc5f7 117 {
MACRUM 6:40e873bbc5f7 118 register uint32_t __regXPSR __ASM("xpsr");
MACRUM 6:40e873bbc5f7 119 return(__regXPSR);
MACRUM 6:40e873bbc5f7 120 }
MACRUM 6:40e873bbc5f7 121
MACRUM 6:40e873bbc5f7 122
MACRUM 6:40e873bbc5f7 123 /** \brief Get Process Stack Pointer
MACRUM 6:40e873bbc5f7 124
MACRUM 6:40e873bbc5f7 125 This function returns the current value of the Process Stack Pointer (PSP).
MACRUM 6:40e873bbc5f7 126
MACRUM 6:40e873bbc5f7 127 \return PSP Register value
MACRUM 6:40e873bbc5f7 128 */
MACRUM 6:40e873bbc5f7 129 __STATIC_INLINE uint32_t __get_PSP(void)
MACRUM 6:40e873bbc5f7 130 {
MACRUM 6:40e873bbc5f7 131 register uint32_t __regProcessStackPointer __ASM("psp");
MACRUM 6:40e873bbc5f7 132 return(__regProcessStackPointer);
MACRUM 6:40e873bbc5f7 133 }
MACRUM 6:40e873bbc5f7 134
MACRUM 6:40e873bbc5f7 135
MACRUM 6:40e873bbc5f7 136 /** \brief Set Process Stack Pointer
MACRUM 6:40e873bbc5f7 137
MACRUM 6:40e873bbc5f7 138 This function assigns the given value to the Process Stack Pointer (PSP).
MACRUM 6:40e873bbc5f7 139
MACRUM 6:40e873bbc5f7 140 \param [in] topOfProcStack Process Stack Pointer value to set
MACRUM 6:40e873bbc5f7 141 */
MACRUM 6:40e873bbc5f7 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MACRUM 6:40e873bbc5f7 143 {
MACRUM 6:40e873bbc5f7 144 register uint32_t __regProcessStackPointer __ASM("psp");
MACRUM 6:40e873bbc5f7 145 __regProcessStackPointer = topOfProcStack;
MACRUM 6:40e873bbc5f7 146 }
MACRUM 6:40e873bbc5f7 147
MACRUM 6:40e873bbc5f7 148
MACRUM 6:40e873bbc5f7 149 /** \brief Get Main Stack Pointer
MACRUM 6:40e873bbc5f7 150
MACRUM 6:40e873bbc5f7 151 This function returns the current value of the Main Stack Pointer (MSP).
MACRUM 6:40e873bbc5f7 152
MACRUM 6:40e873bbc5f7 153 \return MSP Register value
MACRUM 6:40e873bbc5f7 154 */
MACRUM 6:40e873bbc5f7 155 __STATIC_INLINE uint32_t __get_MSP(void)
MACRUM 6:40e873bbc5f7 156 {
MACRUM 6:40e873bbc5f7 157 register uint32_t __regMainStackPointer __ASM("msp");
MACRUM 6:40e873bbc5f7 158 return(__regMainStackPointer);
MACRUM 6:40e873bbc5f7 159 }
MACRUM 6:40e873bbc5f7 160
MACRUM 6:40e873bbc5f7 161
MACRUM 6:40e873bbc5f7 162 /** \brief Set Main Stack Pointer
MACRUM 6:40e873bbc5f7 163
MACRUM 6:40e873bbc5f7 164 This function assigns the given value to the Main Stack Pointer (MSP).
MACRUM 6:40e873bbc5f7 165
MACRUM 6:40e873bbc5f7 166 \param [in] topOfMainStack Main Stack Pointer value to set
MACRUM 6:40e873bbc5f7 167 */
MACRUM 6:40e873bbc5f7 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
MACRUM 6:40e873bbc5f7 169 {
MACRUM 6:40e873bbc5f7 170 register uint32_t __regMainStackPointer __ASM("msp");
MACRUM 6:40e873bbc5f7 171 __regMainStackPointer = topOfMainStack;
MACRUM 6:40e873bbc5f7 172 }
MACRUM 6:40e873bbc5f7 173
MACRUM 6:40e873bbc5f7 174
MACRUM 6:40e873bbc5f7 175 /** \brief Get Priority Mask
MACRUM 6:40e873bbc5f7 176
MACRUM 6:40e873bbc5f7 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
MACRUM 6:40e873bbc5f7 178
MACRUM 6:40e873bbc5f7 179 \return Priority Mask value
MACRUM 6:40e873bbc5f7 180 */
MACRUM 6:40e873bbc5f7 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
MACRUM 6:40e873bbc5f7 182 {
MACRUM 6:40e873bbc5f7 183 register uint32_t __regPriMask __ASM("primask");
MACRUM 6:40e873bbc5f7 184 return(__regPriMask);
MACRUM 6:40e873bbc5f7 185 }
MACRUM 6:40e873bbc5f7 186
MACRUM 6:40e873bbc5f7 187
MACRUM 6:40e873bbc5f7 188 /** \brief Set Priority Mask
MACRUM 6:40e873bbc5f7 189
MACRUM 6:40e873bbc5f7 190 This function assigns the given value to the Priority Mask Register.
MACRUM 6:40e873bbc5f7 191
MACRUM 6:40e873bbc5f7 192 \param [in] priMask Priority Mask
MACRUM 6:40e873bbc5f7 193 */
MACRUM 6:40e873bbc5f7 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
MACRUM 6:40e873bbc5f7 195 {
MACRUM 6:40e873bbc5f7 196 register uint32_t __regPriMask __ASM("primask");
MACRUM 6:40e873bbc5f7 197 __regPriMask = (priMask);
MACRUM 6:40e873bbc5f7 198 }
MACRUM 6:40e873bbc5f7 199
MACRUM 6:40e873bbc5f7 200
MACRUM 6:40e873bbc5f7 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MACRUM 6:40e873bbc5f7 202
MACRUM 6:40e873bbc5f7 203 /** \brief Enable FIQ
MACRUM 6:40e873bbc5f7 204
MACRUM 6:40e873bbc5f7 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MACRUM 6:40e873bbc5f7 206 Can only be executed in Privileged modes.
MACRUM 6:40e873bbc5f7 207 */
MACRUM 6:40e873bbc5f7 208 #define __enable_fault_irq __enable_fiq
MACRUM 6:40e873bbc5f7 209
MACRUM 6:40e873bbc5f7 210
MACRUM 6:40e873bbc5f7 211 /** \brief Disable FIQ
MACRUM 6:40e873bbc5f7 212
MACRUM 6:40e873bbc5f7 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MACRUM 6:40e873bbc5f7 214 Can only be executed in Privileged modes.
MACRUM 6:40e873bbc5f7 215 */
MACRUM 6:40e873bbc5f7 216 #define __disable_fault_irq __disable_fiq
MACRUM 6:40e873bbc5f7 217
MACRUM 6:40e873bbc5f7 218
MACRUM 6:40e873bbc5f7 219 /** \brief Get Base Priority
MACRUM 6:40e873bbc5f7 220
MACRUM 6:40e873bbc5f7 221 This function returns the current value of the Base Priority register.
MACRUM 6:40e873bbc5f7 222
MACRUM 6:40e873bbc5f7 223 \return Base Priority register value
MACRUM 6:40e873bbc5f7 224 */
MACRUM 6:40e873bbc5f7 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
MACRUM 6:40e873bbc5f7 226 {
MACRUM 6:40e873bbc5f7 227 register uint32_t __regBasePri __ASM("basepri");
MACRUM 6:40e873bbc5f7 228 return(__regBasePri);
MACRUM 6:40e873bbc5f7 229 }
MACRUM 6:40e873bbc5f7 230
MACRUM 6:40e873bbc5f7 231
MACRUM 6:40e873bbc5f7 232 /** \brief Set Base Priority
MACRUM 6:40e873bbc5f7 233
MACRUM 6:40e873bbc5f7 234 This function assigns the given value to the Base Priority register.
MACRUM 6:40e873bbc5f7 235
MACRUM 6:40e873bbc5f7 236 \param [in] basePri Base Priority value to set
MACRUM 6:40e873bbc5f7 237 */
MACRUM 6:40e873bbc5f7 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
MACRUM 6:40e873bbc5f7 239 {
MACRUM 6:40e873bbc5f7 240 register uint32_t __regBasePri __ASM("basepri");
MACRUM 6:40e873bbc5f7 241 __regBasePri = (basePri & 0xff);
MACRUM 6:40e873bbc5f7 242 }
MACRUM 6:40e873bbc5f7 243
MACRUM 6:40e873bbc5f7 244
MACRUM 6:40e873bbc5f7 245 /** \brief Set Base Priority with condition
MACRUM 6:40e873bbc5f7 246
MACRUM 6:40e873bbc5f7 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
MACRUM 6:40e873bbc5f7 248 or the new value increases the BASEPRI priority level.
MACRUM 6:40e873bbc5f7 249
MACRUM 6:40e873bbc5f7 250 \param [in] basePri Base Priority value to set
MACRUM 6:40e873bbc5f7 251 */
MACRUM 6:40e873bbc5f7 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
MACRUM 6:40e873bbc5f7 253 {
MACRUM 6:40e873bbc5f7 254 register uint32_t __regBasePriMax __ASM("basepri_max");
MACRUM 6:40e873bbc5f7 255 __regBasePriMax = (basePri & 0xff);
MACRUM 6:40e873bbc5f7 256 }
MACRUM 6:40e873bbc5f7 257
MACRUM 6:40e873bbc5f7 258
MACRUM 6:40e873bbc5f7 259 /** \brief Get Fault Mask
MACRUM 6:40e873bbc5f7 260
MACRUM 6:40e873bbc5f7 261 This function returns the current value of the Fault Mask register.
MACRUM 6:40e873bbc5f7 262
MACRUM 6:40e873bbc5f7 263 \return Fault Mask register value
MACRUM 6:40e873bbc5f7 264 */
MACRUM 6:40e873bbc5f7 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
MACRUM 6:40e873bbc5f7 266 {
MACRUM 6:40e873bbc5f7 267 register uint32_t __regFaultMask __ASM("faultmask");
MACRUM 6:40e873bbc5f7 268 return(__regFaultMask);
MACRUM 6:40e873bbc5f7 269 }
MACRUM 6:40e873bbc5f7 270
MACRUM 6:40e873bbc5f7 271
MACRUM 6:40e873bbc5f7 272 /** \brief Set Fault Mask
MACRUM 6:40e873bbc5f7 273
MACRUM 6:40e873bbc5f7 274 This function assigns the given value to the Fault Mask register.
MACRUM 6:40e873bbc5f7 275
MACRUM 6:40e873bbc5f7 276 \param [in] faultMask Fault Mask value to set
MACRUM 6:40e873bbc5f7 277 */
MACRUM 6:40e873bbc5f7 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
MACRUM 6:40e873bbc5f7 279 {
MACRUM 6:40e873bbc5f7 280 register uint32_t __regFaultMask __ASM("faultmask");
MACRUM 6:40e873bbc5f7 281 __regFaultMask = (faultMask & (uint32_t)1);
MACRUM 6:40e873bbc5f7 282 }
MACRUM 6:40e873bbc5f7 283
MACRUM 6:40e873bbc5f7 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
MACRUM 6:40e873bbc5f7 285
MACRUM 6:40e873bbc5f7 286
MACRUM 6:40e873bbc5f7 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
MACRUM 6:40e873bbc5f7 288
MACRUM 6:40e873bbc5f7 289 /** \brief Get FPSCR
MACRUM 6:40e873bbc5f7 290
MACRUM 6:40e873bbc5f7 291 This function returns the current value of the Floating Point Status/Control register.
MACRUM 6:40e873bbc5f7 292
MACRUM 6:40e873bbc5f7 293 \return Floating Point Status/Control register value
MACRUM 6:40e873bbc5f7 294 */
MACRUM 6:40e873bbc5f7 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
MACRUM 6:40e873bbc5f7 296 {
MACRUM 6:40e873bbc5f7 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MACRUM 6:40e873bbc5f7 298 register uint32_t __regfpscr __ASM("fpscr");
MACRUM 6:40e873bbc5f7 299 return(__regfpscr);
MACRUM 6:40e873bbc5f7 300 #else
MACRUM 6:40e873bbc5f7 301 return(0);
MACRUM 6:40e873bbc5f7 302 #endif
MACRUM 6:40e873bbc5f7 303 }
MACRUM 6:40e873bbc5f7 304
MACRUM 6:40e873bbc5f7 305
MACRUM 6:40e873bbc5f7 306 /** \brief Set FPSCR
MACRUM 6:40e873bbc5f7 307
MACRUM 6:40e873bbc5f7 308 This function assigns the given value to the Floating Point Status/Control register.
MACRUM 6:40e873bbc5f7 309
MACRUM 6:40e873bbc5f7 310 \param [in] fpscr Floating Point Status/Control value to set
MACRUM 6:40e873bbc5f7 311 */
MACRUM 6:40e873bbc5f7 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MACRUM 6:40e873bbc5f7 313 {
MACRUM 6:40e873bbc5f7 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MACRUM 6:40e873bbc5f7 315 register uint32_t __regfpscr __ASM("fpscr");
MACRUM 6:40e873bbc5f7 316 __regfpscr = (fpscr);
MACRUM 6:40e873bbc5f7 317 #endif
MACRUM 6:40e873bbc5f7 318 }
MACRUM 6:40e873bbc5f7 319
MACRUM 6:40e873bbc5f7 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
MACRUM 6:40e873bbc5f7 321
MACRUM 6:40e873bbc5f7 322
MACRUM 6:40e873bbc5f7 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MACRUM 6:40e873bbc5f7 324 /* GNU gcc specific functions */
MACRUM 6:40e873bbc5f7 325
MACRUM 6:40e873bbc5f7 326 /** \brief Enable IRQ Interrupts
MACRUM 6:40e873bbc5f7 327
MACRUM 6:40e873bbc5f7 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
MACRUM 6:40e873bbc5f7 329 Can only be executed in Privileged modes.
MACRUM 6:40e873bbc5f7 330 */
MACRUM 6:40e873bbc5f7 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
MACRUM 6:40e873bbc5f7 332 {
MACRUM 6:40e873bbc5f7 333 __ASM volatile ("cpsie i" : : : "memory");
MACRUM 6:40e873bbc5f7 334 }
MACRUM 6:40e873bbc5f7 335
MACRUM 6:40e873bbc5f7 336
MACRUM 6:40e873bbc5f7 337 /** \brief Disable IRQ Interrupts
MACRUM 6:40e873bbc5f7 338
MACRUM 6:40e873bbc5f7 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
MACRUM 6:40e873bbc5f7 340 Can only be executed in Privileged modes.
MACRUM 6:40e873bbc5f7 341 */
MACRUM 6:40e873bbc5f7 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
MACRUM 6:40e873bbc5f7 343 {
MACRUM 6:40e873bbc5f7 344 __ASM volatile ("cpsid i" : : : "memory");
MACRUM 6:40e873bbc5f7 345 }
MACRUM 6:40e873bbc5f7 346
MACRUM 6:40e873bbc5f7 347
MACRUM 6:40e873bbc5f7 348 /** \brief Get Control Register
MACRUM 6:40e873bbc5f7 349
MACRUM 6:40e873bbc5f7 350 This function returns the content of the Control Register.
MACRUM 6:40e873bbc5f7 351
MACRUM 6:40e873bbc5f7 352 \return Control Register value
MACRUM 6:40e873bbc5f7 353 */
MACRUM 6:40e873bbc5f7 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
MACRUM 6:40e873bbc5f7 355 {
MACRUM 6:40e873bbc5f7 356 uint32_t result;
MACRUM 6:40e873bbc5f7 357
MACRUM 6:40e873bbc5f7 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
MACRUM 6:40e873bbc5f7 359 return(result);
MACRUM 6:40e873bbc5f7 360 }
MACRUM 6:40e873bbc5f7 361
MACRUM 6:40e873bbc5f7 362
MACRUM 6:40e873bbc5f7 363 /** \brief Set Control Register
MACRUM 6:40e873bbc5f7 364
MACRUM 6:40e873bbc5f7 365 This function writes the given value to the Control Register.
MACRUM 6:40e873bbc5f7 366
MACRUM 6:40e873bbc5f7 367 \param [in] control Control Register value to set
MACRUM 6:40e873bbc5f7 368 */
MACRUM 6:40e873bbc5f7 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
MACRUM 6:40e873bbc5f7 370 {
MACRUM 6:40e873bbc5f7 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
MACRUM 6:40e873bbc5f7 372 }
MACRUM 6:40e873bbc5f7 373
MACRUM 6:40e873bbc5f7 374
MACRUM 6:40e873bbc5f7 375 /** \brief Get IPSR Register
MACRUM 6:40e873bbc5f7 376
MACRUM 6:40e873bbc5f7 377 This function returns the content of the IPSR Register.
MACRUM 6:40e873bbc5f7 378
MACRUM 6:40e873bbc5f7 379 \return IPSR Register value
MACRUM 6:40e873bbc5f7 380 */
MACRUM 6:40e873bbc5f7 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
MACRUM 6:40e873bbc5f7 382 {
MACRUM 6:40e873bbc5f7 383 uint32_t result;
MACRUM 6:40e873bbc5f7 384
MACRUM 6:40e873bbc5f7 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
MACRUM 6:40e873bbc5f7 386 return(result);
MACRUM 6:40e873bbc5f7 387 }
MACRUM 6:40e873bbc5f7 388
MACRUM 6:40e873bbc5f7 389
MACRUM 6:40e873bbc5f7 390 /** \brief Get APSR Register
MACRUM 6:40e873bbc5f7 391
MACRUM 6:40e873bbc5f7 392 This function returns the content of the APSR Register.
MACRUM 6:40e873bbc5f7 393
MACRUM 6:40e873bbc5f7 394 \return APSR Register value
MACRUM 6:40e873bbc5f7 395 */
MACRUM 6:40e873bbc5f7 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
MACRUM 6:40e873bbc5f7 397 {
MACRUM 6:40e873bbc5f7 398 uint32_t result;
MACRUM 6:40e873bbc5f7 399
MACRUM 6:40e873bbc5f7 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
MACRUM 6:40e873bbc5f7 401 return(result);
MACRUM 6:40e873bbc5f7 402 }
MACRUM 6:40e873bbc5f7 403
MACRUM 6:40e873bbc5f7 404
MACRUM 6:40e873bbc5f7 405 /** \brief Get xPSR Register
MACRUM 6:40e873bbc5f7 406
MACRUM 6:40e873bbc5f7 407 This function returns the content of the xPSR Register.
MACRUM 6:40e873bbc5f7 408
MACRUM 6:40e873bbc5f7 409 \return xPSR Register value
MACRUM 6:40e873bbc5f7 410 */
MACRUM 6:40e873bbc5f7 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
MACRUM 6:40e873bbc5f7 412 {
MACRUM 6:40e873bbc5f7 413 uint32_t result;
MACRUM 6:40e873bbc5f7 414
MACRUM 6:40e873bbc5f7 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
MACRUM 6:40e873bbc5f7 416 return(result);
MACRUM 6:40e873bbc5f7 417 }
MACRUM 6:40e873bbc5f7 418
MACRUM 6:40e873bbc5f7 419
MACRUM 6:40e873bbc5f7 420 /** \brief Get Process Stack Pointer
MACRUM 6:40e873bbc5f7 421
MACRUM 6:40e873bbc5f7 422 This function returns the current value of the Process Stack Pointer (PSP).
MACRUM 6:40e873bbc5f7 423
MACRUM 6:40e873bbc5f7 424 \return PSP Register value
MACRUM 6:40e873bbc5f7 425 */
MACRUM 6:40e873bbc5f7 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
MACRUM 6:40e873bbc5f7 427 {
MACRUM 6:40e873bbc5f7 428 register uint32_t result;
MACRUM 6:40e873bbc5f7 429
MACRUM 6:40e873bbc5f7 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
MACRUM 6:40e873bbc5f7 431 return(result);
MACRUM 6:40e873bbc5f7 432 }
MACRUM 6:40e873bbc5f7 433
MACRUM 6:40e873bbc5f7 434
MACRUM 6:40e873bbc5f7 435 /** \brief Set Process Stack Pointer
MACRUM 6:40e873bbc5f7 436
MACRUM 6:40e873bbc5f7 437 This function assigns the given value to the Process Stack Pointer (PSP).
MACRUM 6:40e873bbc5f7 438
MACRUM 6:40e873bbc5f7 439 \param [in] topOfProcStack Process Stack Pointer value to set
MACRUM 6:40e873bbc5f7 440 */
MACRUM 6:40e873bbc5f7 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MACRUM 6:40e873bbc5f7 442 {
MACRUM 6:40e873bbc5f7 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
MACRUM 6:40e873bbc5f7 444 }
MACRUM 6:40e873bbc5f7 445
MACRUM 6:40e873bbc5f7 446
MACRUM 6:40e873bbc5f7 447 /** \brief Get Main Stack Pointer
MACRUM 6:40e873bbc5f7 448
MACRUM 6:40e873bbc5f7 449 This function returns the current value of the Main Stack Pointer (MSP).
MACRUM 6:40e873bbc5f7 450
MACRUM 6:40e873bbc5f7 451 \return MSP Register value
MACRUM 6:40e873bbc5f7 452 */
MACRUM 6:40e873bbc5f7 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
MACRUM 6:40e873bbc5f7 454 {
MACRUM 6:40e873bbc5f7 455 register uint32_t result;
MACRUM 6:40e873bbc5f7 456
MACRUM 6:40e873bbc5f7 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
MACRUM 6:40e873bbc5f7 458 return(result);
MACRUM 6:40e873bbc5f7 459 }
MACRUM 6:40e873bbc5f7 460
MACRUM 6:40e873bbc5f7 461
MACRUM 6:40e873bbc5f7 462 /** \brief Set Main Stack Pointer
MACRUM 6:40e873bbc5f7 463
MACRUM 6:40e873bbc5f7 464 This function assigns the given value to the Main Stack Pointer (MSP).
MACRUM 6:40e873bbc5f7 465
MACRUM 6:40e873bbc5f7 466 \param [in] topOfMainStack Main Stack Pointer value to set
MACRUM 6:40e873bbc5f7 467 */
MACRUM 6:40e873bbc5f7 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
MACRUM 6:40e873bbc5f7 469 {
MACRUM 6:40e873bbc5f7 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
MACRUM 6:40e873bbc5f7 471 }
MACRUM 6:40e873bbc5f7 472
MACRUM 6:40e873bbc5f7 473
MACRUM 6:40e873bbc5f7 474 /** \brief Get Priority Mask
MACRUM 6:40e873bbc5f7 475
MACRUM 6:40e873bbc5f7 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
MACRUM 6:40e873bbc5f7 477
MACRUM 6:40e873bbc5f7 478 \return Priority Mask value
MACRUM 6:40e873bbc5f7 479 */
MACRUM 6:40e873bbc5f7 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
MACRUM 6:40e873bbc5f7 481 {
MACRUM 6:40e873bbc5f7 482 uint32_t result;
MACRUM 6:40e873bbc5f7 483
MACRUM 6:40e873bbc5f7 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
MACRUM 6:40e873bbc5f7 485 return(result);
MACRUM 6:40e873bbc5f7 486 }
MACRUM 6:40e873bbc5f7 487
MACRUM 6:40e873bbc5f7 488
MACRUM 6:40e873bbc5f7 489 /** \brief Set Priority Mask
MACRUM 6:40e873bbc5f7 490
MACRUM 6:40e873bbc5f7 491 This function assigns the given value to the Priority Mask Register.
MACRUM 6:40e873bbc5f7 492
MACRUM 6:40e873bbc5f7 493 \param [in] priMask Priority Mask
MACRUM 6:40e873bbc5f7 494 */
MACRUM 6:40e873bbc5f7 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
MACRUM 6:40e873bbc5f7 496 {
MACRUM 6:40e873bbc5f7 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
MACRUM 6:40e873bbc5f7 498 }
MACRUM 6:40e873bbc5f7 499
MACRUM 6:40e873bbc5f7 500
MACRUM 6:40e873bbc5f7 501 #if (__CORTEX_M >= 0x03)
MACRUM 6:40e873bbc5f7 502
MACRUM 6:40e873bbc5f7 503 /** \brief Enable FIQ
MACRUM 6:40e873bbc5f7 504
MACRUM 6:40e873bbc5f7 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MACRUM 6:40e873bbc5f7 506 Can only be executed in Privileged modes.
MACRUM 6:40e873bbc5f7 507 */
MACRUM 6:40e873bbc5f7 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
MACRUM 6:40e873bbc5f7 509 {
MACRUM 6:40e873bbc5f7 510 __ASM volatile ("cpsie f" : : : "memory");
MACRUM 6:40e873bbc5f7 511 }
MACRUM 6:40e873bbc5f7 512
MACRUM 6:40e873bbc5f7 513
MACRUM 6:40e873bbc5f7 514 /** \brief Disable FIQ
MACRUM 6:40e873bbc5f7 515
MACRUM 6:40e873bbc5f7 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MACRUM 6:40e873bbc5f7 517 Can only be executed in Privileged modes.
MACRUM 6:40e873bbc5f7 518 */
MACRUM 6:40e873bbc5f7 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
MACRUM 6:40e873bbc5f7 520 {
MACRUM 6:40e873bbc5f7 521 __ASM volatile ("cpsid f" : : : "memory");
MACRUM 6:40e873bbc5f7 522 }
MACRUM 6:40e873bbc5f7 523
MACRUM 6:40e873bbc5f7 524
MACRUM 6:40e873bbc5f7 525 /** \brief Get Base Priority
MACRUM 6:40e873bbc5f7 526
MACRUM 6:40e873bbc5f7 527 This function returns the current value of the Base Priority register.
MACRUM 6:40e873bbc5f7 528
MACRUM 6:40e873bbc5f7 529 \return Base Priority register value
MACRUM 6:40e873bbc5f7 530 */
MACRUM 6:40e873bbc5f7 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
MACRUM 6:40e873bbc5f7 532 {
MACRUM 6:40e873bbc5f7 533 uint32_t result;
MACRUM 6:40e873bbc5f7 534
MACRUM 6:40e873bbc5f7 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
MACRUM 6:40e873bbc5f7 536 return(result);
MACRUM 6:40e873bbc5f7 537 }
MACRUM 6:40e873bbc5f7 538
MACRUM 6:40e873bbc5f7 539
MACRUM 6:40e873bbc5f7 540 /** \brief Set Base Priority
MACRUM 6:40e873bbc5f7 541
MACRUM 6:40e873bbc5f7 542 This function assigns the given value to the Base Priority register.
MACRUM 6:40e873bbc5f7 543
MACRUM 6:40e873bbc5f7 544 \param [in] basePri Base Priority value to set
MACRUM 6:40e873bbc5f7 545 */
MACRUM 6:40e873bbc5f7 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
MACRUM 6:40e873bbc5f7 547 {
MACRUM 6:40e873bbc5f7 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
MACRUM 6:40e873bbc5f7 549 }
MACRUM 6:40e873bbc5f7 550
MACRUM 6:40e873bbc5f7 551
MACRUM 6:40e873bbc5f7 552 /** \brief Set Base Priority with condition
MACRUM 6:40e873bbc5f7 553
MACRUM 6:40e873bbc5f7 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
MACRUM 6:40e873bbc5f7 555 or the new value increases the BASEPRI priority level.
MACRUM 6:40e873bbc5f7 556
MACRUM 6:40e873bbc5f7 557 \param [in] basePri Base Priority value to set
MACRUM 6:40e873bbc5f7 558 */
MACRUM 6:40e873bbc5f7 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
MACRUM 6:40e873bbc5f7 560 {
MACRUM 6:40e873bbc5f7 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
MACRUM 6:40e873bbc5f7 562 }
MACRUM 6:40e873bbc5f7 563
MACRUM 6:40e873bbc5f7 564
MACRUM 6:40e873bbc5f7 565 /** \brief Get Fault Mask
MACRUM 6:40e873bbc5f7 566
MACRUM 6:40e873bbc5f7 567 This function returns the current value of the Fault Mask register.
MACRUM 6:40e873bbc5f7 568
MACRUM 6:40e873bbc5f7 569 \return Fault Mask register value
MACRUM 6:40e873bbc5f7 570 */
MACRUM 6:40e873bbc5f7 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
MACRUM 6:40e873bbc5f7 572 {
MACRUM 6:40e873bbc5f7 573 uint32_t result;
MACRUM 6:40e873bbc5f7 574
MACRUM 6:40e873bbc5f7 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
MACRUM 6:40e873bbc5f7 576 return(result);
MACRUM 6:40e873bbc5f7 577 }
MACRUM 6:40e873bbc5f7 578
MACRUM 6:40e873bbc5f7 579
MACRUM 6:40e873bbc5f7 580 /** \brief Set Fault Mask
MACRUM 6:40e873bbc5f7 581
MACRUM 6:40e873bbc5f7 582 This function assigns the given value to the Fault Mask register.
MACRUM 6:40e873bbc5f7 583
MACRUM 6:40e873bbc5f7 584 \param [in] faultMask Fault Mask value to set
MACRUM 6:40e873bbc5f7 585 */
MACRUM 6:40e873bbc5f7 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
MACRUM 6:40e873bbc5f7 587 {
MACRUM 6:40e873bbc5f7 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
MACRUM 6:40e873bbc5f7 589 }
MACRUM 6:40e873bbc5f7 590
MACRUM 6:40e873bbc5f7 591 #endif /* (__CORTEX_M >= 0x03) */
MACRUM 6:40e873bbc5f7 592
MACRUM 6:40e873bbc5f7 593
MACRUM 6:40e873bbc5f7 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
MACRUM 6:40e873bbc5f7 595
MACRUM 6:40e873bbc5f7 596 /** \brief Get FPSCR
MACRUM 6:40e873bbc5f7 597
MACRUM 6:40e873bbc5f7 598 This function returns the current value of the Floating Point Status/Control register.
MACRUM 6:40e873bbc5f7 599
MACRUM 6:40e873bbc5f7 600 \return Floating Point Status/Control register value
MACRUM 6:40e873bbc5f7 601 */
MACRUM 6:40e873bbc5f7 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
MACRUM 6:40e873bbc5f7 603 {
MACRUM 6:40e873bbc5f7 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MACRUM 6:40e873bbc5f7 605 uint32_t result;
MACRUM 6:40e873bbc5f7 606
MACRUM 6:40e873bbc5f7 607 /* Empty asm statement works as a scheduling barrier */
MACRUM 6:40e873bbc5f7 608 __ASM volatile ("");
MACRUM 6:40e873bbc5f7 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
MACRUM 6:40e873bbc5f7 610 __ASM volatile ("");
MACRUM 6:40e873bbc5f7 611 return(result);
MACRUM 6:40e873bbc5f7 612 #else
MACRUM 6:40e873bbc5f7 613 return(0);
MACRUM 6:40e873bbc5f7 614 #endif
MACRUM 6:40e873bbc5f7 615 }
MACRUM 6:40e873bbc5f7 616
MACRUM 6:40e873bbc5f7 617
MACRUM 6:40e873bbc5f7 618 /** \brief Set FPSCR
MACRUM 6:40e873bbc5f7 619
MACRUM 6:40e873bbc5f7 620 This function assigns the given value to the Floating Point Status/Control register.
MACRUM 6:40e873bbc5f7 621
MACRUM 6:40e873bbc5f7 622 \param [in] fpscr Floating Point Status/Control value to set
MACRUM 6:40e873bbc5f7 623 */
MACRUM 6:40e873bbc5f7 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MACRUM 6:40e873bbc5f7 625 {
MACRUM 6:40e873bbc5f7 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MACRUM 6:40e873bbc5f7 627 /* Empty asm statement works as a scheduling barrier */
MACRUM 6:40e873bbc5f7 628 __ASM volatile ("");
MACRUM 6:40e873bbc5f7 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
MACRUM 6:40e873bbc5f7 630 __ASM volatile ("");
MACRUM 6:40e873bbc5f7 631 #endif
MACRUM 6:40e873bbc5f7 632 }
MACRUM 6:40e873bbc5f7 633
MACRUM 6:40e873bbc5f7 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
MACRUM 6:40e873bbc5f7 635
MACRUM 6:40e873bbc5f7 636
MACRUM 6:40e873bbc5f7 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MACRUM 6:40e873bbc5f7 638 /* IAR iccarm specific functions */
MACRUM 6:40e873bbc5f7 639 #include <cmsis_iar.h>
MACRUM 6:40e873bbc5f7 640
MACRUM 6:40e873bbc5f7 641
MACRUM 6:40e873bbc5f7 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MACRUM 6:40e873bbc5f7 643 /* TI CCS specific functions */
MACRUM 6:40e873bbc5f7 644 #include <cmsis_ccs.h>
MACRUM 6:40e873bbc5f7 645
MACRUM 6:40e873bbc5f7 646
MACRUM 6:40e873bbc5f7 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MACRUM 6:40e873bbc5f7 648 /* TASKING carm specific functions */
MACRUM 6:40e873bbc5f7 649 /*
MACRUM 6:40e873bbc5f7 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
MACRUM 6:40e873bbc5f7 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
MACRUM 6:40e873bbc5f7 652 * Including the CMSIS ones.
MACRUM 6:40e873bbc5f7 653 */
MACRUM 6:40e873bbc5f7 654
MACRUM 6:40e873bbc5f7 655
MACRUM 6:40e873bbc5f7 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
MACRUM 6:40e873bbc5f7 657 /* Cosmic specific functions */
MACRUM 6:40e873bbc5f7 658 #include <cmsis_csm.h>
MACRUM 6:40e873bbc5f7 659
MACRUM 6:40e873bbc5f7 660 #endif
MACRUM 6:40e873bbc5f7 661
MACRUM 6:40e873bbc5f7 662 /*@} end of CMSIS_Core_RegAccFunctions */
MACRUM 6:40e873bbc5f7 663
MACRUM 6:40e873bbc5f7 664 #endif /* __CORE_CMFUNC_H */