Toyomasa Watarai / Mbed OS armcc_info

Describes predefine macros for mbed online compiler (armcc)

mbed/TARGET_LPC1114/core_cm4_simd.h@6:40e873bbc5f7, 2017-03-16 (annotated)

Committer:
MACRUM
Date:
Thu Mar 16 21:58:09 2017 +0900
Revision:
6:40e873bbc5f7
Add licence header info

Who changed what in which revision?

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MACRUM 6:40e873bbc5f7 1 /**************************************************************************//**
MACRUM 6:40e873bbc5f7 2 * @file core_cm4_simd.h
MACRUM 6:40e873bbc5f7 3 * @brief CMSIS Cortex-M4 SIMD Header File
MACRUM 6:40e873bbc5f7 4 * @version V3.20
MACRUM 6:40e873bbc5f7 5 * @date 25. February 2013
MACRUM 6:40e873bbc5f7 6 *
MACRUM 6:40e873bbc5f7 7 * @note
MACRUM 6:40e873bbc5f7 8 *
MACRUM 6:40e873bbc5f7 9 ******************************************************************************/
MACRUM 6:40e873bbc5f7 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
MACRUM 6:40e873bbc5f7 11
MACRUM 6:40e873bbc5f7 12 All rights reserved.
MACRUM 6:40e873bbc5f7 13 Redistribution and use in source and binary forms, with or without
MACRUM 6:40e873bbc5f7 14 modification, are permitted provided that the following conditions are met:
MACRUM 6:40e873bbc5f7 15 - Redistributions of source code must retain the above copyright
MACRUM 6:40e873bbc5f7 16 notice, this list of conditions and the following disclaimer.
MACRUM 6:40e873bbc5f7 17 - Redistributions in binary form must reproduce the above copyright
MACRUM 6:40e873bbc5f7 18 notice, this list of conditions and the following disclaimer in the
MACRUM 6:40e873bbc5f7 19 documentation and/or other materials provided with the distribution.
MACRUM 6:40e873bbc5f7 20 - Neither the name of ARM nor the names of its contributors may be used
MACRUM 6:40e873bbc5f7 21 to endorse or promote products derived from this software without
MACRUM 6:40e873bbc5f7 22 specific prior written permission.
MACRUM 6:40e873bbc5f7 23 *
MACRUM 6:40e873bbc5f7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MACRUM 6:40e873bbc5f7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MACRUM 6:40e873bbc5f7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MACRUM 6:40e873bbc5f7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MACRUM 6:40e873bbc5f7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MACRUM 6:40e873bbc5f7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MACRUM 6:40e873bbc5f7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MACRUM 6:40e873bbc5f7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MACRUM 6:40e873bbc5f7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MACRUM 6:40e873bbc5f7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MACRUM 6:40e873bbc5f7 34 POSSIBILITY OF SUCH DAMAGE.
MACRUM 6:40e873bbc5f7 35 ---------------------------------------------------------------------------*/
MACRUM 6:40e873bbc5f7 36
MACRUM 6:40e873bbc5f7 37
MACRUM 6:40e873bbc5f7 38 #ifdef __cplusplus
MACRUM 6:40e873bbc5f7 39 extern "C" {
MACRUM 6:40e873bbc5f7 40 #endif
MACRUM 6:40e873bbc5f7 41
MACRUM 6:40e873bbc5f7 42 #ifndef __CORE_CM4_SIMD_H
MACRUM 6:40e873bbc5f7 43 #define __CORE_CM4_SIMD_H
MACRUM 6:40e873bbc5f7 44
MACRUM 6:40e873bbc5f7 45
MACRUM 6:40e873bbc5f7 46 /*******************************************************************************
MACRUM 6:40e873bbc5f7 47 * Hardware Abstraction Layer
MACRUM 6:40e873bbc5f7 48 ******************************************************************************/
MACRUM 6:40e873bbc5f7 49
MACRUM 6:40e873bbc5f7 50
MACRUM 6:40e873bbc5f7 51 /* ################### Compiler specific Intrinsics ########################### */
MACRUM 6:40e873bbc5f7 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
MACRUM 6:40e873bbc5f7 53 Access to dedicated SIMD instructions
MACRUM 6:40e873bbc5f7 54 @{
MACRUM 6:40e873bbc5f7 55 */
MACRUM 6:40e873bbc5f7 56
MACRUM 6:40e873bbc5f7 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MACRUM 6:40e873bbc5f7 58 /* ARM armcc specific functions */
MACRUM 6:40e873bbc5f7 59
MACRUM 6:40e873bbc5f7 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MACRUM 6:40e873bbc5f7 61 #define __SADD8 __sadd8
MACRUM 6:40e873bbc5f7 62 #define __QADD8 __qadd8
MACRUM 6:40e873bbc5f7 63 #define __SHADD8 __shadd8
MACRUM 6:40e873bbc5f7 64 #define __UADD8 __uadd8
MACRUM 6:40e873bbc5f7 65 #define __UQADD8 __uqadd8
MACRUM 6:40e873bbc5f7 66 #define __UHADD8 __uhadd8
MACRUM 6:40e873bbc5f7 67 #define __SSUB8 __ssub8
MACRUM 6:40e873bbc5f7 68 #define __QSUB8 __qsub8
MACRUM 6:40e873bbc5f7 69 #define __SHSUB8 __shsub8
MACRUM 6:40e873bbc5f7 70 #define __USUB8 __usub8
MACRUM 6:40e873bbc5f7 71 #define __UQSUB8 __uqsub8
MACRUM 6:40e873bbc5f7 72 #define __UHSUB8 __uhsub8
MACRUM 6:40e873bbc5f7 73 #define __SADD16 __sadd16
MACRUM 6:40e873bbc5f7 74 #define __QADD16 __qadd16
MACRUM 6:40e873bbc5f7 75 #define __SHADD16 __shadd16
MACRUM 6:40e873bbc5f7 76 #define __UADD16 __uadd16
MACRUM 6:40e873bbc5f7 77 #define __UQADD16 __uqadd16
MACRUM 6:40e873bbc5f7 78 #define __UHADD16 __uhadd16
MACRUM 6:40e873bbc5f7 79 #define __SSUB16 __ssub16
MACRUM 6:40e873bbc5f7 80 #define __QSUB16 __qsub16
MACRUM 6:40e873bbc5f7 81 #define __SHSUB16 __shsub16
MACRUM 6:40e873bbc5f7 82 #define __USUB16 __usub16
MACRUM 6:40e873bbc5f7 83 #define __UQSUB16 __uqsub16
MACRUM 6:40e873bbc5f7 84 #define __UHSUB16 __uhsub16
MACRUM 6:40e873bbc5f7 85 #define __SASX __sasx
MACRUM 6:40e873bbc5f7 86 #define __QASX __qasx
MACRUM 6:40e873bbc5f7 87 #define __SHASX __shasx
MACRUM 6:40e873bbc5f7 88 #define __UASX __uasx
MACRUM 6:40e873bbc5f7 89 #define __UQASX __uqasx
MACRUM 6:40e873bbc5f7 90 #define __UHASX __uhasx
MACRUM 6:40e873bbc5f7 91 #define __SSAX __ssax
MACRUM 6:40e873bbc5f7 92 #define __QSAX __qsax
MACRUM 6:40e873bbc5f7 93 #define __SHSAX __shsax
MACRUM 6:40e873bbc5f7 94 #define __USAX __usax
MACRUM 6:40e873bbc5f7 95 #define __UQSAX __uqsax
MACRUM 6:40e873bbc5f7 96 #define __UHSAX __uhsax
MACRUM 6:40e873bbc5f7 97 #define __USAD8 __usad8
MACRUM 6:40e873bbc5f7 98 #define __USADA8 __usada8
MACRUM 6:40e873bbc5f7 99 #define __SSAT16 __ssat16
MACRUM 6:40e873bbc5f7 100 #define __USAT16 __usat16
MACRUM 6:40e873bbc5f7 101 #define __UXTB16 __uxtb16
MACRUM 6:40e873bbc5f7 102 #define __UXTAB16 __uxtab16
MACRUM 6:40e873bbc5f7 103 #define __SXTB16 __sxtb16
MACRUM 6:40e873bbc5f7 104 #define __SXTAB16 __sxtab16
MACRUM 6:40e873bbc5f7 105 #define __SMUAD __smuad
MACRUM 6:40e873bbc5f7 106 #define __SMUADX __smuadx
MACRUM 6:40e873bbc5f7 107 #define __SMLAD __smlad
MACRUM 6:40e873bbc5f7 108 #define __SMLADX __smladx
MACRUM 6:40e873bbc5f7 109 #define __SMLALD __smlald
MACRUM 6:40e873bbc5f7 110 #define __SMLALDX __smlaldx
MACRUM 6:40e873bbc5f7 111 #define __SMUSD __smusd
MACRUM 6:40e873bbc5f7 112 #define __SMUSDX __smusdx
MACRUM 6:40e873bbc5f7 113 #define __SMLSD __smlsd
MACRUM 6:40e873bbc5f7 114 #define __SMLSDX __smlsdx
MACRUM 6:40e873bbc5f7 115 #define __SMLSLD __smlsld
MACRUM 6:40e873bbc5f7 116 #define __SMLSLDX __smlsldx
MACRUM 6:40e873bbc5f7 117 #define __SEL __sel
MACRUM 6:40e873bbc5f7 118 #define __QADD __qadd
MACRUM 6:40e873bbc5f7 119 #define __QSUB __qsub
MACRUM 6:40e873bbc5f7 120
MACRUM 6:40e873bbc5f7 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
MACRUM 6:40e873bbc5f7 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
MACRUM 6:40e873bbc5f7 123
MACRUM 6:40e873bbc5f7 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
MACRUM 6:40e873bbc5f7 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
MACRUM 6:40e873bbc5f7 126
MACRUM 6:40e873bbc5f7 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
MACRUM 6:40e873bbc5f7 128 ((int64_t)(ARG3) << 32) ) >> 32))
MACRUM 6:40e873bbc5f7 129
MACRUM 6:40e873bbc5f7 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MACRUM 6:40e873bbc5f7 131
MACRUM 6:40e873bbc5f7 132
MACRUM 6:40e873bbc5f7 133
MACRUM 6:40e873bbc5f7 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MACRUM 6:40e873bbc5f7 135 /* IAR iccarm specific functions */
MACRUM 6:40e873bbc5f7 136
MACRUM 6:40e873bbc5f7 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MACRUM 6:40e873bbc5f7 138 #include <cmsis_iar.h>
MACRUM 6:40e873bbc5f7 139
MACRUM 6:40e873bbc5f7 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MACRUM 6:40e873bbc5f7 141
MACRUM 6:40e873bbc5f7 142
MACRUM 6:40e873bbc5f7 143
MACRUM 6:40e873bbc5f7 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MACRUM 6:40e873bbc5f7 145 /* TI CCS specific functions */
MACRUM 6:40e873bbc5f7 146
MACRUM 6:40e873bbc5f7 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MACRUM 6:40e873bbc5f7 148 #include <cmsis_ccs.h>
MACRUM 6:40e873bbc5f7 149
MACRUM 6:40e873bbc5f7 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MACRUM 6:40e873bbc5f7 151
MACRUM 6:40e873bbc5f7 152
MACRUM 6:40e873bbc5f7 153
MACRUM 6:40e873bbc5f7 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MACRUM 6:40e873bbc5f7 155 /* GNU gcc specific functions */
MACRUM 6:40e873bbc5f7 156
MACRUM 6:40e873bbc5f7 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MACRUM 6:40e873bbc5f7 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 159 {
MACRUM 6:40e873bbc5f7 160 uint32_t result;
MACRUM 6:40e873bbc5f7 161
MACRUM 6:40e873bbc5f7 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 163 return(result);
MACRUM 6:40e873bbc5f7 164 }
MACRUM 6:40e873bbc5f7 165
MACRUM 6:40e873bbc5f7 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 167 {
MACRUM 6:40e873bbc5f7 168 uint32_t result;
MACRUM 6:40e873bbc5f7 169
MACRUM 6:40e873bbc5f7 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 171 return(result);
MACRUM 6:40e873bbc5f7 172 }
MACRUM 6:40e873bbc5f7 173
MACRUM 6:40e873bbc5f7 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 175 {
MACRUM 6:40e873bbc5f7 176 uint32_t result;
MACRUM 6:40e873bbc5f7 177
MACRUM 6:40e873bbc5f7 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 179 return(result);
MACRUM 6:40e873bbc5f7 180 }
MACRUM 6:40e873bbc5f7 181
MACRUM 6:40e873bbc5f7 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 183 {
MACRUM 6:40e873bbc5f7 184 uint32_t result;
MACRUM 6:40e873bbc5f7 185
MACRUM 6:40e873bbc5f7 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 187 return(result);
MACRUM 6:40e873bbc5f7 188 }
MACRUM 6:40e873bbc5f7 189
MACRUM 6:40e873bbc5f7 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 191 {
MACRUM 6:40e873bbc5f7 192 uint32_t result;
MACRUM 6:40e873bbc5f7 193
MACRUM 6:40e873bbc5f7 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 195 return(result);
MACRUM 6:40e873bbc5f7 196 }
MACRUM 6:40e873bbc5f7 197
MACRUM 6:40e873bbc5f7 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 199 {
MACRUM 6:40e873bbc5f7 200 uint32_t result;
MACRUM 6:40e873bbc5f7 201
MACRUM 6:40e873bbc5f7 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 203 return(result);
MACRUM 6:40e873bbc5f7 204 }
MACRUM 6:40e873bbc5f7 205
MACRUM 6:40e873bbc5f7 206
MACRUM 6:40e873bbc5f7 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 208 {
MACRUM 6:40e873bbc5f7 209 uint32_t result;
MACRUM 6:40e873bbc5f7 210
MACRUM 6:40e873bbc5f7 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 212 return(result);
MACRUM 6:40e873bbc5f7 213 }
MACRUM 6:40e873bbc5f7 214
MACRUM 6:40e873bbc5f7 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 216 {
MACRUM 6:40e873bbc5f7 217 uint32_t result;
MACRUM 6:40e873bbc5f7 218
MACRUM 6:40e873bbc5f7 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 220 return(result);
MACRUM 6:40e873bbc5f7 221 }
MACRUM 6:40e873bbc5f7 222
MACRUM 6:40e873bbc5f7 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 224 {
MACRUM 6:40e873bbc5f7 225 uint32_t result;
MACRUM 6:40e873bbc5f7 226
MACRUM 6:40e873bbc5f7 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 228 return(result);
MACRUM 6:40e873bbc5f7 229 }
MACRUM 6:40e873bbc5f7 230
MACRUM 6:40e873bbc5f7 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 232 {
MACRUM 6:40e873bbc5f7 233 uint32_t result;
MACRUM 6:40e873bbc5f7 234
MACRUM 6:40e873bbc5f7 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 236 return(result);
MACRUM 6:40e873bbc5f7 237 }
MACRUM 6:40e873bbc5f7 238
MACRUM 6:40e873bbc5f7 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 240 {
MACRUM 6:40e873bbc5f7 241 uint32_t result;
MACRUM 6:40e873bbc5f7 242
MACRUM 6:40e873bbc5f7 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 244 return(result);
MACRUM 6:40e873bbc5f7 245 }
MACRUM 6:40e873bbc5f7 246
MACRUM 6:40e873bbc5f7 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 248 {
MACRUM 6:40e873bbc5f7 249 uint32_t result;
MACRUM 6:40e873bbc5f7 250
MACRUM 6:40e873bbc5f7 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 252 return(result);
MACRUM 6:40e873bbc5f7 253 }
MACRUM 6:40e873bbc5f7 254
MACRUM 6:40e873bbc5f7 255
MACRUM 6:40e873bbc5f7 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 257 {
MACRUM 6:40e873bbc5f7 258 uint32_t result;
MACRUM 6:40e873bbc5f7 259
MACRUM 6:40e873bbc5f7 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 261 return(result);
MACRUM 6:40e873bbc5f7 262 }
MACRUM 6:40e873bbc5f7 263
MACRUM 6:40e873bbc5f7 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 265 {
MACRUM 6:40e873bbc5f7 266 uint32_t result;
MACRUM 6:40e873bbc5f7 267
MACRUM 6:40e873bbc5f7 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 269 return(result);
MACRUM 6:40e873bbc5f7 270 }
MACRUM 6:40e873bbc5f7 271
MACRUM 6:40e873bbc5f7 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 273 {
MACRUM 6:40e873bbc5f7 274 uint32_t result;
MACRUM 6:40e873bbc5f7 275
MACRUM 6:40e873bbc5f7 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 277 return(result);
MACRUM 6:40e873bbc5f7 278 }
MACRUM 6:40e873bbc5f7 279
MACRUM 6:40e873bbc5f7 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 281 {
MACRUM 6:40e873bbc5f7 282 uint32_t result;
MACRUM 6:40e873bbc5f7 283
MACRUM 6:40e873bbc5f7 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 285 return(result);
MACRUM 6:40e873bbc5f7 286 }
MACRUM 6:40e873bbc5f7 287
MACRUM 6:40e873bbc5f7 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 289 {
MACRUM 6:40e873bbc5f7 290 uint32_t result;
MACRUM 6:40e873bbc5f7 291
MACRUM 6:40e873bbc5f7 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 293 return(result);
MACRUM 6:40e873bbc5f7 294 }
MACRUM 6:40e873bbc5f7 295
MACRUM 6:40e873bbc5f7 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 297 {
MACRUM 6:40e873bbc5f7 298 uint32_t result;
MACRUM 6:40e873bbc5f7 299
MACRUM 6:40e873bbc5f7 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 301 return(result);
MACRUM 6:40e873bbc5f7 302 }
MACRUM 6:40e873bbc5f7 303
MACRUM 6:40e873bbc5f7 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 305 {
MACRUM 6:40e873bbc5f7 306 uint32_t result;
MACRUM 6:40e873bbc5f7 307
MACRUM 6:40e873bbc5f7 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 309 return(result);
MACRUM 6:40e873bbc5f7 310 }
MACRUM 6:40e873bbc5f7 311
MACRUM 6:40e873bbc5f7 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 313 {
MACRUM 6:40e873bbc5f7 314 uint32_t result;
MACRUM 6:40e873bbc5f7 315
MACRUM 6:40e873bbc5f7 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 317 return(result);
MACRUM 6:40e873bbc5f7 318 }
MACRUM 6:40e873bbc5f7 319
MACRUM 6:40e873bbc5f7 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 321 {
MACRUM 6:40e873bbc5f7 322 uint32_t result;
MACRUM 6:40e873bbc5f7 323
MACRUM 6:40e873bbc5f7 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 325 return(result);
MACRUM 6:40e873bbc5f7 326 }
MACRUM 6:40e873bbc5f7 327
MACRUM 6:40e873bbc5f7 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 329 {
MACRUM 6:40e873bbc5f7 330 uint32_t result;
MACRUM 6:40e873bbc5f7 331
MACRUM 6:40e873bbc5f7 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 333 return(result);
MACRUM 6:40e873bbc5f7 334 }
MACRUM 6:40e873bbc5f7 335
MACRUM 6:40e873bbc5f7 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 337 {
MACRUM 6:40e873bbc5f7 338 uint32_t result;
MACRUM 6:40e873bbc5f7 339
MACRUM 6:40e873bbc5f7 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 341 return(result);
MACRUM 6:40e873bbc5f7 342 }
MACRUM 6:40e873bbc5f7 343
MACRUM 6:40e873bbc5f7 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 345 {
MACRUM 6:40e873bbc5f7 346 uint32_t result;
MACRUM 6:40e873bbc5f7 347
MACRUM 6:40e873bbc5f7 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 349 return(result);
MACRUM 6:40e873bbc5f7 350 }
MACRUM 6:40e873bbc5f7 351
MACRUM 6:40e873bbc5f7 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 353 {
MACRUM 6:40e873bbc5f7 354 uint32_t result;
MACRUM 6:40e873bbc5f7 355
MACRUM 6:40e873bbc5f7 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 357 return(result);
MACRUM 6:40e873bbc5f7 358 }
MACRUM 6:40e873bbc5f7 359
MACRUM 6:40e873bbc5f7 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 361 {
MACRUM 6:40e873bbc5f7 362 uint32_t result;
MACRUM 6:40e873bbc5f7 363
MACRUM 6:40e873bbc5f7 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 365 return(result);
MACRUM 6:40e873bbc5f7 366 }
MACRUM 6:40e873bbc5f7 367
MACRUM 6:40e873bbc5f7 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 369 {
MACRUM 6:40e873bbc5f7 370 uint32_t result;
MACRUM 6:40e873bbc5f7 371
MACRUM 6:40e873bbc5f7 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 373 return(result);
MACRUM 6:40e873bbc5f7 374 }
MACRUM 6:40e873bbc5f7 375
MACRUM 6:40e873bbc5f7 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 377 {
MACRUM 6:40e873bbc5f7 378 uint32_t result;
MACRUM 6:40e873bbc5f7 379
MACRUM 6:40e873bbc5f7 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 381 return(result);
MACRUM 6:40e873bbc5f7 382 }
MACRUM 6:40e873bbc5f7 383
MACRUM 6:40e873bbc5f7 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 385 {
MACRUM 6:40e873bbc5f7 386 uint32_t result;
MACRUM 6:40e873bbc5f7 387
MACRUM 6:40e873bbc5f7 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 389 return(result);
MACRUM 6:40e873bbc5f7 390 }
MACRUM 6:40e873bbc5f7 391
MACRUM 6:40e873bbc5f7 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 393 {
MACRUM 6:40e873bbc5f7 394 uint32_t result;
MACRUM 6:40e873bbc5f7 395
MACRUM 6:40e873bbc5f7 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 397 return(result);
MACRUM 6:40e873bbc5f7 398 }
MACRUM 6:40e873bbc5f7 399
MACRUM 6:40e873bbc5f7 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 401 {
MACRUM 6:40e873bbc5f7 402 uint32_t result;
MACRUM 6:40e873bbc5f7 403
MACRUM 6:40e873bbc5f7 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 405 return(result);
MACRUM 6:40e873bbc5f7 406 }
MACRUM 6:40e873bbc5f7 407
MACRUM 6:40e873bbc5f7 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 409 {
MACRUM 6:40e873bbc5f7 410 uint32_t result;
MACRUM 6:40e873bbc5f7 411
MACRUM 6:40e873bbc5f7 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 413 return(result);
MACRUM 6:40e873bbc5f7 414 }
MACRUM 6:40e873bbc5f7 415
MACRUM 6:40e873bbc5f7 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 417 {
MACRUM 6:40e873bbc5f7 418 uint32_t result;
MACRUM 6:40e873bbc5f7 419
MACRUM 6:40e873bbc5f7 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 421 return(result);
MACRUM 6:40e873bbc5f7 422 }
MACRUM 6:40e873bbc5f7 423
MACRUM 6:40e873bbc5f7 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 425 {
MACRUM 6:40e873bbc5f7 426 uint32_t result;
MACRUM 6:40e873bbc5f7 427
MACRUM 6:40e873bbc5f7 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 429 return(result);
MACRUM 6:40e873bbc5f7 430 }
MACRUM 6:40e873bbc5f7 431
MACRUM 6:40e873bbc5f7 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 433 {
MACRUM 6:40e873bbc5f7 434 uint32_t result;
MACRUM 6:40e873bbc5f7 435
MACRUM 6:40e873bbc5f7 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 437 return(result);
MACRUM 6:40e873bbc5f7 438 }
MACRUM 6:40e873bbc5f7 439
MACRUM 6:40e873bbc5f7 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 441 {
MACRUM 6:40e873bbc5f7 442 uint32_t result;
MACRUM 6:40e873bbc5f7 443
MACRUM 6:40e873bbc5f7 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 445 return(result);
MACRUM 6:40e873bbc5f7 446 }
MACRUM 6:40e873bbc5f7 447
MACRUM 6:40e873bbc5f7 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 449 {
MACRUM 6:40e873bbc5f7 450 uint32_t result;
MACRUM 6:40e873bbc5f7 451
MACRUM 6:40e873bbc5f7 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 453 return(result);
MACRUM 6:40e873bbc5f7 454 }
MACRUM 6:40e873bbc5f7 455
MACRUM 6:40e873bbc5f7 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
MACRUM 6:40e873bbc5f7 457 {
MACRUM 6:40e873bbc5f7 458 uint32_t result;
MACRUM 6:40e873bbc5f7 459
MACRUM 6:40e873bbc5f7 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MACRUM 6:40e873bbc5f7 461 return(result);
MACRUM 6:40e873bbc5f7 462 }
MACRUM 6:40e873bbc5f7 463
MACRUM 6:40e873bbc5f7 464 #define __SSAT16(ARG1,ARG2) \
MACRUM 6:40e873bbc5f7 465 ({ \
MACRUM 6:40e873bbc5f7 466 uint32_t __RES, __ARG1 = (ARG1); \
MACRUM 6:40e873bbc5f7 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MACRUM 6:40e873bbc5f7 468 __RES; \
MACRUM 6:40e873bbc5f7 469 })
MACRUM 6:40e873bbc5f7 470
MACRUM 6:40e873bbc5f7 471 #define __USAT16(ARG1,ARG2) \
MACRUM 6:40e873bbc5f7 472 ({ \
MACRUM 6:40e873bbc5f7 473 uint32_t __RES, __ARG1 = (ARG1); \
MACRUM 6:40e873bbc5f7 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MACRUM 6:40e873bbc5f7 475 __RES; \
MACRUM 6:40e873bbc5f7 476 })
MACRUM 6:40e873bbc5f7 477
MACRUM 6:40e873bbc5f7 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
MACRUM 6:40e873bbc5f7 479 {
MACRUM 6:40e873bbc5f7 480 uint32_t result;
MACRUM 6:40e873bbc5f7 481
MACRUM 6:40e873bbc5f7 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
MACRUM 6:40e873bbc5f7 483 return(result);
MACRUM 6:40e873bbc5f7 484 }
MACRUM 6:40e873bbc5f7 485
MACRUM 6:40e873bbc5f7 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 487 {
MACRUM 6:40e873bbc5f7 488 uint32_t result;
MACRUM 6:40e873bbc5f7 489
MACRUM 6:40e873bbc5f7 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 491 return(result);
MACRUM 6:40e873bbc5f7 492 }
MACRUM 6:40e873bbc5f7 493
MACRUM 6:40e873bbc5f7 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
MACRUM 6:40e873bbc5f7 495 {
MACRUM 6:40e873bbc5f7 496 uint32_t result;
MACRUM 6:40e873bbc5f7 497
MACRUM 6:40e873bbc5f7 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
MACRUM 6:40e873bbc5f7 499 return(result);
MACRUM 6:40e873bbc5f7 500 }
MACRUM 6:40e873bbc5f7 501
MACRUM 6:40e873bbc5f7 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 503 {
MACRUM 6:40e873bbc5f7 504 uint32_t result;
MACRUM 6:40e873bbc5f7 505
MACRUM 6:40e873bbc5f7 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 507 return(result);
MACRUM 6:40e873bbc5f7 508 }
MACRUM 6:40e873bbc5f7 509
MACRUM 6:40e873bbc5f7 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 511 {
MACRUM 6:40e873bbc5f7 512 uint32_t result;
MACRUM 6:40e873bbc5f7 513
MACRUM 6:40e873bbc5f7 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 515 return(result);
MACRUM 6:40e873bbc5f7 516 }
MACRUM 6:40e873bbc5f7 517
MACRUM 6:40e873bbc5f7 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 519 {
MACRUM 6:40e873bbc5f7 520 uint32_t result;
MACRUM 6:40e873bbc5f7 521
MACRUM 6:40e873bbc5f7 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 523 return(result);
MACRUM 6:40e873bbc5f7 524 }
MACRUM 6:40e873bbc5f7 525
MACRUM 6:40e873bbc5f7 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
MACRUM 6:40e873bbc5f7 527 {
MACRUM 6:40e873bbc5f7 528 uint32_t result;
MACRUM 6:40e873bbc5f7 529
MACRUM 6:40e873bbc5f7 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MACRUM 6:40e873bbc5f7 531 return(result);
MACRUM 6:40e873bbc5f7 532 }
MACRUM 6:40e873bbc5f7 533
MACRUM 6:40e873bbc5f7 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
MACRUM 6:40e873bbc5f7 535 {
MACRUM 6:40e873bbc5f7 536 uint32_t result;
MACRUM 6:40e873bbc5f7 537
MACRUM 6:40e873bbc5f7 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MACRUM 6:40e873bbc5f7 539 return(result);
MACRUM 6:40e873bbc5f7 540 }
MACRUM 6:40e873bbc5f7 541
MACRUM 6:40e873bbc5f7 542 #define __SMLALD(ARG1,ARG2,ARG3) \
MACRUM 6:40e873bbc5f7 543 ({ \
MACRUM 6:40e873bbc5f7 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
MACRUM 6:40e873bbc5f7 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MACRUM 6:40e873bbc5f7 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MACRUM 6:40e873bbc5f7 547 })
MACRUM 6:40e873bbc5f7 548
MACRUM 6:40e873bbc5f7 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
MACRUM 6:40e873bbc5f7 550 ({ \
MACRUM 6:40e873bbc5f7 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
MACRUM 6:40e873bbc5f7 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MACRUM 6:40e873bbc5f7 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MACRUM 6:40e873bbc5f7 554 })
MACRUM 6:40e873bbc5f7 555
MACRUM 6:40e873bbc5f7 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 557 {
MACRUM 6:40e873bbc5f7 558 uint32_t result;
MACRUM 6:40e873bbc5f7 559
MACRUM 6:40e873bbc5f7 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 561 return(result);
MACRUM 6:40e873bbc5f7 562 }
MACRUM 6:40e873bbc5f7 563
MACRUM 6:40e873bbc5f7 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 565 {
MACRUM 6:40e873bbc5f7 566 uint32_t result;
MACRUM 6:40e873bbc5f7 567
MACRUM 6:40e873bbc5f7 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 569 return(result);
MACRUM 6:40e873bbc5f7 570 }
MACRUM 6:40e873bbc5f7 571
MACRUM 6:40e873bbc5f7 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
MACRUM 6:40e873bbc5f7 573 {
MACRUM 6:40e873bbc5f7 574 uint32_t result;
MACRUM 6:40e873bbc5f7 575
MACRUM 6:40e873bbc5f7 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MACRUM 6:40e873bbc5f7 577 return(result);
MACRUM 6:40e873bbc5f7 578 }
MACRUM 6:40e873bbc5f7 579
MACRUM 6:40e873bbc5f7 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
MACRUM 6:40e873bbc5f7 581 {
MACRUM 6:40e873bbc5f7 582 uint32_t result;
MACRUM 6:40e873bbc5f7 583
MACRUM 6:40e873bbc5f7 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MACRUM 6:40e873bbc5f7 585 return(result);
MACRUM 6:40e873bbc5f7 586 }
MACRUM 6:40e873bbc5f7 587
MACRUM 6:40e873bbc5f7 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
MACRUM 6:40e873bbc5f7 589 ({ \
MACRUM 6:40e873bbc5f7 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
MACRUM 6:40e873bbc5f7 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MACRUM 6:40e873bbc5f7 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MACRUM 6:40e873bbc5f7 593 })
MACRUM 6:40e873bbc5f7 594
MACRUM 6:40e873bbc5f7 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
MACRUM 6:40e873bbc5f7 596 ({ \
MACRUM 6:40e873bbc5f7 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
MACRUM 6:40e873bbc5f7 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MACRUM 6:40e873bbc5f7 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MACRUM 6:40e873bbc5f7 600 })
MACRUM 6:40e873bbc5f7 601
MACRUM 6:40e873bbc5f7 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 603 {
MACRUM 6:40e873bbc5f7 604 uint32_t result;
MACRUM 6:40e873bbc5f7 605
MACRUM 6:40e873bbc5f7 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 607 return(result);
MACRUM 6:40e873bbc5f7 608 }
MACRUM 6:40e873bbc5f7 609
MACRUM 6:40e873bbc5f7 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 611 {
MACRUM 6:40e873bbc5f7 612 uint32_t result;
MACRUM 6:40e873bbc5f7 613
MACRUM 6:40e873bbc5f7 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 615 return(result);
MACRUM 6:40e873bbc5f7 616 }
MACRUM 6:40e873bbc5f7 617
MACRUM 6:40e873bbc5f7 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
MACRUM 6:40e873bbc5f7 619 {
MACRUM 6:40e873bbc5f7 620 uint32_t result;
MACRUM 6:40e873bbc5f7 621
MACRUM 6:40e873bbc5f7 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MACRUM 6:40e873bbc5f7 623 return(result);
MACRUM 6:40e873bbc5f7 624 }
MACRUM 6:40e873bbc5f7 625
MACRUM 6:40e873bbc5f7 626 #define __PKHBT(ARG1,ARG2,ARG3) \
MACRUM 6:40e873bbc5f7 627 ({ \
MACRUM 6:40e873bbc5f7 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
MACRUM 6:40e873bbc5f7 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
MACRUM 6:40e873bbc5f7 630 __RES; \
MACRUM 6:40e873bbc5f7 631 })
MACRUM 6:40e873bbc5f7 632
MACRUM 6:40e873bbc5f7 633 #define __PKHTB(ARG1,ARG2,ARG3) \
MACRUM 6:40e873bbc5f7 634 ({ \
MACRUM 6:40e873bbc5f7 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
MACRUM 6:40e873bbc5f7 636 if (ARG3 == 0) \
MACRUM 6:40e873bbc5f7 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
MACRUM 6:40e873bbc5f7 638 else \
MACRUM 6:40e873bbc5f7 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
MACRUM 6:40e873bbc5f7 640 __RES; \
MACRUM 6:40e873bbc5f7 641 })
MACRUM 6:40e873bbc5f7 642
MACRUM 6:40e873bbc5f7 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
MACRUM 6:40e873bbc5f7 644 {
MACRUM 6:40e873bbc5f7 645 int32_t result;
MACRUM 6:40e873bbc5f7 646
MACRUM 6:40e873bbc5f7 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
MACRUM 6:40e873bbc5f7 648 return(result);
MACRUM 6:40e873bbc5f7 649 }
MACRUM 6:40e873bbc5f7 650
MACRUM 6:40e873bbc5f7 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MACRUM 6:40e873bbc5f7 652
MACRUM 6:40e873bbc5f7 653
MACRUM 6:40e873bbc5f7 654
MACRUM 6:40e873bbc5f7 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MACRUM 6:40e873bbc5f7 656 /* TASKING carm specific functions */
MACRUM 6:40e873bbc5f7 657
MACRUM 6:40e873bbc5f7 658
MACRUM 6:40e873bbc5f7 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MACRUM 6:40e873bbc5f7 660 /* not yet supported */
MACRUM 6:40e873bbc5f7 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MACRUM 6:40e873bbc5f7 662
MACRUM 6:40e873bbc5f7 663
MACRUM 6:40e873bbc5f7 664 #endif
MACRUM 6:40e873bbc5f7 665
MACRUM 6:40e873bbc5f7 666 /*@} end of group CMSIS_SIMD_intrinsics */
MACRUM 6:40e873bbc5f7 667
MACRUM 6:40e873bbc5f7 668
MACRUM 6:40e873bbc5f7 669 #endif /* __CORE_CM4_SIMD_H */
MACRUM 6:40e873bbc5f7 670
MACRUM 6:40e873bbc5f7 671 #ifdef __cplusplus
MACRUM 6:40e873bbc5f7 672 }
MACRUM 6:40e873bbc5f7 673 #endif