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Describes predefine macros for mbed online compiler (armcc)

mbed/TARGET_LPC1114/core_cm4.h@6:40e873bbc5f7, 2017-03-16 (annotated)

Committer:: MACRUM
Date:: Thu Mar 16 21:58:09 2017 +0900
Revision:: 6:40e873bbc5f7

Add licence header info

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MACRUM	6:40e873bbc5f7	1	/************************************************************************//
MACRUM	6:40e873bbc5f7	2	* @file core_cm4.h
MACRUM	6:40e873bbc5f7	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
MACRUM	6:40e873bbc5f7	4	* @version V4.10
MACRUM	6:40e873bbc5f7	5	* @date 18. March 2015
MACRUM	6:40e873bbc5f7	6	*
MACRUM	6:40e873bbc5f7	7	* @note
MACRUM	6:40e873bbc5f7	8	*
MACRUM	6:40e873bbc5f7	9	******************************************************************************/
MACRUM	6:40e873bbc5f7	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
MACRUM	6:40e873bbc5f7	11
MACRUM	6:40e873bbc5f7	12	All rights reserved.
MACRUM	6:40e873bbc5f7	13	Redistribution and use in source and binary forms, with or without
MACRUM	6:40e873bbc5f7	14	modification, are permitted provided that the following conditions are met:
MACRUM	6:40e873bbc5f7	15	- Redistributions of source code must retain the above copyright
MACRUM	6:40e873bbc5f7	16	notice, this list of conditions and the following disclaimer.
MACRUM	6:40e873bbc5f7	17	- Redistributions in binary form must reproduce the above copyright
MACRUM	6:40e873bbc5f7	18	notice, this list of conditions and the following disclaimer in the
MACRUM	6:40e873bbc5f7	19	documentation and/or other materials provided with the distribution.
MACRUM	6:40e873bbc5f7	20	- Neither the name of ARM nor the names of its contributors may be used
MACRUM	6:40e873bbc5f7	21	to endorse or promote products derived from this software without
MACRUM	6:40e873bbc5f7	22	specific prior written permission.
MACRUM	6:40e873bbc5f7	23	*
MACRUM	6:40e873bbc5f7	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MACRUM	6:40e873bbc5f7	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MACRUM	6:40e873bbc5f7	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MACRUM	6:40e873bbc5f7	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MACRUM	6:40e873bbc5f7	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MACRUM	6:40e873bbc5f7	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MACRUM	6:40e873bbc5f7	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MACRUM	6:40e873bbc5f7	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MACRUM	6:40e873bbc5f7	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MACRUM	6:40e873bbc5f7	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MACRUM	6:40e873bbc5f7	34	POSSIBILITY OF SUCH DAMAGE.
MACRUM	6:40e873bbc5f7	35	---------------------------------------------------------------------------*/
MACRUM	6:40e873bbc5f7	36
MACRUM	6:40e873bbc5f7	37
MACRUM	6:40e873bbc5f7	38	#if defined ( __ICCARM__ )
MACRUM	6:40e873bbc5f7	39	#pragma system_include /* treat file as system include file for MISRA check */
MACRUM	6:40e873bbc5f7	40	#endif
MACRUM	6:40e873bbc5f7	41
MACRUM	6:40e873bbc5f7	42	#ifndef __CORE_CM4_H_GENERIC
MACRUM	6:40e873bbc5f7	43	#define __CORE_CM4_H_GENERIC
MACRUM	6:40e873bbc5f7	44
MACRUM	6:40e873bbc5f7	45	#ifdef __cplusplus
MACRUM	6:40e873bbc5f7	46	extern "C" {
MACRUM	6:40e873bbc5f7	47	#endif
MACRUM	6:40e873bbc5f7	48
MACRUM	6:40e873bbc5f7	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
MACRUM	6:40e873bbc5f7	50	CMSIS violates the following MISRA-C:2004 rules:
MACRUM	6:40e873bbc5f7	51
MACRUM	6:40e873bbc5f7	52	\li Required Rule 8.5, object/function definition in header file.<br>
MACRUM	6:40e873bbc5f7	53	Function definitions in header files are used to allow 'inlining'.
MACRUM	6:40e873bbc5f7	54
MACRUM	6:40e873bbc5f7	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
MACRUM	6:40e873bbc5f7	56	Unions are used for effective representation of core registers.
MACRUM	6:40e873bbc5f7	57
MACRUM	6:40e873bbc5f7	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
MACRUM	6:40e873bbc5f7	59	Function-like macros are used to allow more efficient code.
MACRUM	6:40e873bbc5f7	60	*/
MACRUM	6:40e873bbc5f7	61
MACRUM	6:40e873bbc5f7	62
MACRUM	6:40e873bbc5f7	63	/*******************************************************************************
MACRUM	6:40e873bbc5f7	64	* CMSIS definitions
MACRUM	6:40e873bbc5f7	65	******************************************************************************/
MACRUM	6:40e873bbc5f7	66	/** \ingroup Cortex_M4
MACRUM	6:40e873bbc5f7	67	@{
MACRUM	6:40e873bbc5f7	68	*/
MACRUM	6:40e873bbc5f7	69
MACRUM	6:40e873bbc5f7	70	/* CMSIS CM4 definitions */
MACRUM	6:40e873bbc5f7	71	#define __CM4_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
MACRUM	6:40e873bbc5f7	72	#define __CM4_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
MACRUM	6:40e873bbc5f7	73	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) \| \
MACRUM	6:40e873bbc5f7	74	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
MACRUM	6:40e873bbc5f7	75
MACRUM	6:40e873bbc5f7	76	#define __CORTEX_M (0x04) /!< Cortex-M Core /
MACRUM	6:40e873bbc5f7	77
MACRUM	6:40e873bbc5f7	78
MACRUM	6:40e873bbc5f7	79	#if defined ( __CC_ARM )
MACRUM	6:40e873bbc5f7	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
MACRUM	6:40e873bbc5f7	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
MACRUM	6:40e873bbc5f7	82	#define __STATIC_INLINE static __inline
MACRUM	6:40e873bbc5f7	83
MACRUM	6:40e873bbc5f7	84	#elif defined ( __GNUC__ )
MACRUM	6:40e873bbc5f7	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
MACRUM	6:40e873bbc5f7	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
MACRUM	6:40e873bbc5f7	87	#define __STATIC_INLINE static inline
MACRUM	6:40e873bbc5f7	88
MACRUM	6:40e873bbc5f7	89	#elif defined ( __ICCARM__ )
MACRUM	6:40e873bbc5f7	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
MACRUM	6:40e873bbc5f7	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
MACRUM	6:40e873bbc5f7	92	#define __STATIC_INLINE static inline
MACRUM	6:40e873bbc5f7	93
MACRUM	6:40e873bbc5f7	94	#elif defined ( __TMS470__ )
MACRUM	6:40e873bbc5f7	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
MACRUM	6:40e873bbc5f7	96	#define __STATIC_INLINE static inline
MACRUM	6:40e873bbc5f7	97
MACRUM	6:40e873bbc5f7	98	#elif defined ( __TASKING__ )
MACRUM	6:40e873bbc5f7	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
MACRUM	6:40e873bbc5f7	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
MACRUM	6:40e873bbc5f7	101	#define __STATIC_INLINE static inline
MACRUM	6:40e873bbc5f7	102
MACRUM	6:40e873bbc5f7	103	#elif defined ( __CSMC__ )
MACRUM	6:40e873bbc5f7	104	#define __packed
MACRUM	6:40e873bbc5f7	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
MACRUM	6:40e873bbc5f7	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
MACRUM	6:40e873bbc5f7	107	#define __STATIC_INLINE static inline
MACRUM	6:40e873bbc5f7	108
MACRUM	6:40e873bbc5f7	109	#endif
MACRUM	6:40e873bbc5f7	110
MACRUM	6:40e873bbc5f7	111	/** __FPU_USED indicates whether an FPU is used or not.
MACRUM	6:40e873bbc5f7	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
MACRUM	6:40e873bbc5f7	113	*/
MACRUM	6:40e873bbc5f7	114	#if defined ( __CC_ARM )
MACRUM	6:40e873bbc5f7	115	#if defined __TARGET_FPU_VFP
MACRUM	6:40e873bbc5f7	116	#if (__FPU_PRESENT == 1)
MACRUM	6:40e873bbc5f7	117	#define __FPU_USED 1
MACRUM	6:40e873bbc5f7	118	#else
MACRUM	6:40e873bbc5f7	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MACRUM	6:40e873bbc5f7	120	#define __FPU_USED 0
MACRUM	6:40e873bbc5f7	121	#endif
MACRUM	6:40e873bbc5f7	122	#else
MACRUM	6:40e873bbc5f7	123	#define __FPU_USED 0
MACRUM	6:40e873bbc5f7	124	#endif
MACRUM	6:40e873bbc5f7	125
MACRUM	6:40e873bbc5f7	126	#elif defined ( __GNUC__ )
MACRUM	6:40e873bbc5f7	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
MACRUM	6:40e873bbc5f7	128	#if (__FPU_PRESENT == 1)
MACRUM	6:40e873bbc5f7	129	#define __FPU_USED 1
MACRUM	6:40e873bbc5f7	130	#else
MACRUM	6:40e873bbc5f7	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MACRUM	6:40e873bbc5f7	132	#define __FPU_USED 0
MACRUM	6:40e873bbc5f7	133	#endif
MACRUM	6:40e873bbc5f7	134	#else
MACRUM	6:40e873bbc5f7	135	#define __FPU_USED 0
MACRUM	6:40e873bbc5f7	136	#endif
MACRUM	6:40e873bbc5f7	137
MACRUM	6:40e873bbc5f7	138	#elif defined ( __ICCARM__ )
MACRUM	6:40e873bbc5f7	139	#if defined __ARMVFP__
MACRUM	6:40e873bbc5f7	140	#if (__FPU_PRESENT == 1)
MACRUM	6:40e873bbc5f7	141	#define __FPU_USED 1
MACRUM	6:40e873bbc5f7	142	#else
MACRUM	6:40e873bbc5f7	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MACRUM	6:40e873bbc5f7	144	#define __FPU_USED 0
MACRUM	6:40e873bbc5f7	145	#endif
MACRUM	6:40e873bbc5f7	146	#else
MACRUM	6:40e873bbc5f7	147	#define __FPU_USED 0
MACRUM	6:40e873bbc5f7	148	#endif
MACRUM	6:40e873bbc5f7	149
MACRUM	6:40e873bbc5f7	150	#elif defined ( __TMS470__ )
MACRUM	6:40e873bbc5f7	151	#if defined __TI_VFP_SUPPORT__
MACRUM	6:40e873bbc5f7	152	#if (__FPU_PRESENT == 1)
MACRUM	6:40e873bbc5f7	153	#define __FPU_USED 1
MACRUM	6:40e873bbc5f7	154	#else
MACRUM	6:40e873bbc5f7	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MACRUM	6:40e873bbc5f7	156	#define __FPU_USED 0
MACRUM	6:40e873bbc5f7	157	#endif
MACRUM	6:40e873bbc5f7	158	#else
MACRUM	6:40e873bbc5f7	159	#define __FPU_USED 0
MACRUM	6:40e873bbc5f7	160	#endif
MACRUM	6:40e873bbc5f7	161
MACRUM	6:40e873bbc5f7	162	#elif defined ( __TASKING__ )
MACRUM	6:40e873bbc5f7	163	#if defined __FPU_VFP__
MACRUM	6:40e873bbc5f7	164	#if (__FPU_PRESENT == 1)
MACRUM	6:40e873bbc5f7	165	#define __FPU_USED 1
MACRUM	6:40e873bbc5f7	166	#else
MACRUM	6:40e873bbc5f7	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MACRUM	6:40e873bbc5f7	168	#define __FPU_USED 0
MACRUM	6:40e873bbc5f7	169	#endif
MACRUM	6:40e873bbc5f7	170	#else
MACRUM	6:40e873bbc5f7	171	#define __FPU_USED 0
MACRUM	6:40e873bbc5f7	172	#endif
MACRUM	6:40e873bbc5f7	173
MACRUM	6:40e873bbc5f7	174	#elif defined ( __CSMC__ ) /* Cosmic */
MACRUM	6:40e873bbc5f7	175	#if ( __CSMC__ & 0x400) // FPU present for parser
MACRUM	6:40e873bbc5f7	176	#if (__FPU_PRESENT == 1)
MACRUM	6:40e873bbc5f7	177	#define __FPU_USED 1
MACRUM	6:40e873bbc5f7	178	#else
MACRUM	6:40e873bbc5f7	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MACRUM	6:40e873bbc5f7	180	#define __FPU_USED 0
MACRUM	6:40e873bbc5f7	181	#endif
MACRUM	6:40e873bbc5f7	182	#else
MACRUM	6:40e873bbc5f7	183	#define __FPU_USED 0
MACRUM	6:40e873bbc5f7	184	#endif
MACRUM	6:40e873bbc5f7	185	#endif
MACRUM	6:40e873bbc5f7	186
MACRUM	6:40e873bbc5f7	187	#include <stdint.h> /* standard types definitions */
MACRUM	6:40e873bbc5f7	188	#include <core_cmInstr.h> /* Core Instruction Access */
MACRUM	6:40e873bbc5f7	189	#include <core_cmFunc.h> /* Core Function Access */
MACRUM	6:40e873bbc5f7	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
MACRUM	6:40e873bbc5f7	191
MACRUM	6:40e873bbc5f7	192	#ifdef __cplusplus
MACRUM	6:40e873bbc5f7	193	}
MACRUM	6:40e873bbc5f7	194	#endif
MACRUM	6:40e873bbc5f7	195
MACRUM	6:40e873bbc5f7	196	#endif /* __CORE_CM4_H_GENERIC */
MACRUM	6:40e873bbc5f7	197
MACRUM	6:40e873bbc5f7	198	#ifndef __CMSIS_GENERIC
MACRUM	6:40e873bbc5f7	199
MACRUM	6:40e873bbc5f7	200	#ifndef __CORE_CM4_H_DEPENDANT
MACRUM	6:40e873bbc5f7	201	#define __CORE_CM4_H_DEPENDANT
MACRUM	6:40e873bbc5f7	202
MACRUM	6:40e873bbc5f7	203	#ifdef __cplusplus
MACRUM	6:40e873bbc5f7	204	extern "C" {
MACRUM	6:40e873bbc5f7	205	#endif
MACRUM	6:40e873bbc5f7	206
MACRUM	6:40e873bbc5f7	207	/* check device defines and use defaults */
MACRUM	6:40e873bbc5f7	208	#if defined __CHECK_DEVICE_DEFINES
MACRUM	6:40e873bbc5f7	209	#ifndef __CM4_REV
MACRUM	6:40e873bbc5f7	210	#define __CM4_REV 0x0000
MACRUM	6:40e873bbc5f7	211	#warning "__CM4_REV not defined in device header file; using default!"
MACRUM	6:40e873bbc5f7	212	#endif
MACRUM	6:40e873bbc5f7	213
MACRUM	6:40e873bbc5f7	214	#ifndef __FPU_PRESENT
MACRUM	6:40e873bbc5f7	215	#define __FPU_PRESENT 0
MACRUM	6:40e873bbc5f7	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
MACRUM	6:40e873bbc5f7	217	#endif
MACRUM	6:40e873bbc5f7	218
MACRUM	6:40e873bbc5f7	219	#ifndef __MPU_PRESENT
MACRUM	6:40e873bbc5f7	220	#define __MPU_PRESENT 0
MACRUM	6:40e873bbc5f7	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
MACRUM	6:40e873bbc5f7	222	#endif
MACRUM	6:40e873bbc5f7	223
MACRUM	6:40e873bbc5f7	224	#ifndef __NVIC_PRIO_BITS
MACRUM	6:40e873bbc5f7	225	#define __NVIC_PRIO_BITS 4
MACRUM	6:40e873bbc5f7	226	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
MACRUM	6:40e873bbc5f7	227	#endif
MACRUM	6:40e873bbc5f7	228
MACRUM	6:40e873bbc5f7	229	#ifndef __Vendor_SysTickConfig
MACRUM	6:40e873bbc5f7	230	#define __Vendor_SysTickConfig 0
MACRUM	6:40e873bbc5f7	231	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
MACRUM	6:40e873bbc5f7	232	#endif
MACRUM	6:40e873bbc5f7	233	#endif
MACRUM	6:40e873bbc5f7	234
MACRUM	6:40e873bbc5f7	235	/* IO definitions (access restrictions to peripheral registers) */
MACRUM	6:40e873bbc5f7	236	/**
MACRUM	6:40e873bbc5f7	237	\defgroup CMSIS_glob_defs CMSIS Global Defines
MACRUM	6:40e873bbc5f7	238
MACRUM	6:40e873bbc5f7	239	<strong>IO Type Qualifiers</strong> are used
MACRUM	6:40e873bbc5f7	240	\li to specify the access to peripheral variables.
MACRUM	6:40e873bbc5f7	241	\li for automatic generation of peripheral register debug information.
MACRUM	6:40e873bbc5f7	242	*/
MACRUM	6:40e873bbc5f7	243	#ifdef __cplusplus
MACRUM	6:40e873bbc5f7	244	#define __I volatile /!< Defines 'read only' permissions /
MACRUM	6:40e873bbc5f7	245	#else
MACRUM	6:40e873bbc5f7	246	#define __I volatile const /!< Defines 'read only' permissions /
MACRUM	6:40e873bbc5f7	247	#endif
MACRUM	6:40e873bbc5f7	248	#define __O volatile /!< Defines 'write only' permissions /
MACRUM	6:40e873bbc5f7	249	#define __IO volatile /!< Defines 'read / write' permissions /
MACRUM	6:40e873bbc5f7	250
MACRUM	6:40e873bbc5f7	251	#ifdef __cplusplus
MACRUM	6:40e873bbc5f7	252	#define __IM volatile /!< Defines 'read only' permissions /
MACRUM	6:40e873bbc5f7	253	#else
MACRUM	6:40e873bbc5f7	254	#define __IM volatile const /!< Defines 'read only' permissions /
MACRUM	6:40e873bbc5f7	255	#endif
MACRUM	6:40e873bbc5f7	256	#define __OM volatile /!< Defines 'write only' permissions /
MACRUM	6:40e873bbc5f7	257	#define __IOM volatile /!< Defines 'read / write' permissions /
MACRUM	6:40e873bbc5f7	258
MACRUM	6:40e873bbc5f7	259	/@} end of group Cortex_M4 /
MACRUM	6:40e873bbc5f7	260
MACRUM	6:40e873bbc5f7	261
MACRUM	6:40e873bbc5f7	262
MACRUM	6:40e873bbc5f7	263	/*******************************************************************************
MACRUM	6:40e873bbc5f7	264	* Register Abstraction
MACRUM	6:40e873bbc5f7	265	Core Register contain:
MACRUM	6:40e873bbc5f7	266	- Core Register
MACRUM	6:40e873bbc5f7	267	- Core NVIC Register
MACRUM	6:40e873bbc5f7	268	- Core SCB Register
MACRUM	6:40e873bbc5f7	269	- Core SysTick Register
MACRUM	6:40e873bbc5f7	270	- Core Debug Register
MACRUM	6:40e873bbc5f7	271	- Core MPU Register
MACRUM	6:40e873bbc5f7	272	- Core FPU Register
MACRUM	6:40e873bbc5f7	273	******************************************************************************/
MACRUM	6:40e873bbc5f7	274	/** \defgroup CMSIS_core_register Defines and Type Definitions
MACRUM	6:40e873bbc5f7	275	\brief Type definitions and defines for Cortex-M processor based devices.
MACRUM	6:40e873bbc5f7	276	*/
MACRUM	6:40e873bbc5f7	277
MACRUM	6:40e873bbc5f7	278	/** \ingroup CMSIS_core_register
MACRUM	6:40e873bbc5f7	279	\defgroup CMSIS_CORE Status and Control Registers
MACRUM	6:40e873bbc5f7	280	\brief Core Register type definitions.
MACRUM	6:40e873bbc5f7	281	@{
MACRUM	6:40e873bbc5f7	282	*/
MACRUM	6:40e873bbc5f7	283
MACRUM	6:40e873bbc5f7	284	/** \brief Union type to access the Application Program Status Register (APSR).
MACRUM	6:40e873bbc5f7	285	*/
MACRUM	6:40e873bbc5f7	286	typedef union
MACRUM	6:40e873bbc5f7	287	{
MACRUM	6:40e873bbc5f7	288	struct
MACRUM	6:40e873bbc5f7	289	{
MACRUM	6:40e873bbc5f7	290	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
MACRUM	6:40e873bbc5f7	291	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
MACRUM	6:40e873bbc5f7	292	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
MACRUM	6:40e873bbc5f7	293	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
MACRUM	6:40e873bbc5f7	294	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
MACRUM	6:40e873bbc5f7	295	uint32_t C:1; /!< bit: 29 Carry condition code flag /
MACRUM	6:40e873bbc5f7	296	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
MACRUM	6:40e873bbc5f7	297	uint32_t N:1; /!< bit: 31 Negative condition code flag /
MACRUM	6:40e873bbc5f7	298	} b; /!< Structure used for bit access /
MACRUM	6:40e873bbc5f7	299	uint32_t w; /!< Type used for word access /
MACRUM	6:40e873bbc5f7	300	} APSR_Type;
MACRUM	6:40e873bbc5f7	301
MACRUM	6:40e873bbc5f7	302	/* APSR Register Definitions */
MACRUM	6:40e873bbc5f7	303	#define APSR_N_Pos 31 /!< APSR: N Position /
MACRUM	6:40e873bbc5f7	304	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
MACRUM	6:40e873bbc5f7	305
MACRUM	6:40e873bbc5f7	306	#define APSR_Z_Pos 30 /!< APSR: Z Position /
MACRUM	6:40e873bbc5f7	307	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
MACRUM	6:40e873bbc5f7	308
MACRUM	6:40e873bbc5f7	309	#define APSR_C_Pos 29 /!< APSR: C Position /
MACRUM	6:40e873bbc5f7	310	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
MACRUM	6:40e873bbc5f7	311
MACRUM	6:40e873bbc5f7	312	#define APSR_V_Pos 28 /!< APSR: V Position /
MACRUM	6:40e873bbc5f7	313	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
MACRUM	6:40e873bbc5f7	314
MACRUM	6:40e873bbc5f7	315	#define APSR_Q_Pos 27 /!< APSR: Q Position /
MACRUM	6:40e873bbc5f7	316	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
MACRUM	6:40e873bbc5f7	317
MACRUM	6:40e873bbc5f7	318	#define APSR_GE_Pos 16 /!< APSR: GE Position /
MACRUM	6:40e873bbc5f7	319	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
MACRUM	6:40e873bbc5f7	320
MACRUM	6:40e873bbc5f7	321
MACRUM	6:40e873bbc5f7	322	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
MACRUM	6:40e873bbc5f7	323	*/
MACRUM	6:40e873bbc5f7	324	typedef union
MACRUM	6:40e873bbc5f7	325	{
MACRUM	6:40e873bbc5f7	326	struct
MACRUM	6:40e873bbc5f7	327	{
MACRUM	6:40e873bbc5f7	328	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
MACRUM	6:40e873bbc5f7	329	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
MACRUM	6:40e873bbc5f7	330	} b; /!< Structure used for bit access /
MACRUM	6:40e873bbc5f7	331	uint32_t w; /!< Type used for word access /
MACRUM	6:40e873bbc5f7	332	} IPSR_Type;
MACRUM	6:40e873bbc5f7	333
MACRUM	6:40e873bbc5f7	334	/* IPSR Register Definitions */
MACRUM	6:40e873bbc5f7	335	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
MACRUM	6:40e873bbc5f7	336	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
MACRUM	6:40e873bbc5f7	337
MACRUM	6:40e873bbc5f7	338
MACRUM	6:40e873bbc5f7	339	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
MACRUM	6:40e873bbc5f7	340	*/
MACRUM	6:40e873bbc5f7	341	typedef union
MACRUM	6:40e873bbc5f7	342	{
MACRUM	6:40e873bbc5f7	343	struct
MACRUM	6:40e873bbc5f7	344	{
MACRUM	6:40e873bbc5f7	345	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
MACRUM	6:40e873bbc5f7	346	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
MACRUM	6:40e873bbc5f7	347	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
MACRUM	6:40e873bbc5f7	348	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
MACRUM	6:40e873bbc5f7	349	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
MACRUM	6:40e873bbc5f7	350	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
MACRUM	6:40e873bbc5f7	351	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
MACRUM	6:40e873bbc5f7	352	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
MACRUM	6:40e873bbc5f7	353	uint32_t C:1; /!< bit: 29 Carry condition code flag /
MACRUM	6:40e873bbc5f7	354	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
MACRUM	6:40e873bbc5f7	355	uint32_t N:1; /!< bit: 31 Negative condition code flag /
MACRUM	6:40e873bbc5f7	356	} b; /!< Structure used for bit access /
MACRUM	6:40e873bbc5f7	357	uint32_t w; /!< Type used for word access /
MACRUM	6:40e873bbc5f7	358	} xPSR_Type;
MACRUM	6:40e873bbc5f7	359
MACRUM	6:40e873bbc5f7	360	/* xPSR Register Definitions */
MACRUM	6:40e873bbc5f7	361	#define xPSR_N_Pos 31 /!< xPSR: N Position /
MACRUM	6:40e873bbc5f7	362	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
MACRUM	6:40e873bbc5f7	363
MACRUM	6:40e873bbc5f7	364	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
MACRUM	6:40e873bbc5f7	365	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
MACRUM	6:40e873bbc5f7	366
MACRUM	6:40e873bbc5f7	367	#define xPSR_C_Pos 29 /!< xPSR: C Position /
MACRUM	6:40e873bbc5f7	368	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
MACRUM	6:40e873bbc5f7	369
MACRUM	6:40e873bbc5f7	370	#define xPSR_V_Pos 28 /!< xPSR: V Position /
MACRUM	6:40e873bbc5f7	371	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
MACRUM	6:40e873bbc5f7	372
MACRUM	6:40e873bbc5f7	373	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
MACRUM	6:40e873bbc5f7	374	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
MACRUM	6:40e873bbc5f7	375
MACRUM	6:40e873bbc5f7	376	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
MACRUM	6:40e873bbc5f7	377	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
MACRUM	6:40e873bbc5f7	378
MACRUM	6:40e873bbc5f7	379	#define xPSR_T_Pos 24 /!< xPSR: T Position /
MACRUM	6:40e873bbc5f7	380	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
MACRUM	6:40e873bbc5f7	381
MACRUM	6:40e873bbc5f7	382	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
MACRUM	6:40e873bbc5f7	383	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
MACRUM	6:40e873bbc5f7	384
MACRUM	6:40e873bbc5f7	385	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
MACRUM	6:40e873bbc5f7	386	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
MACRUM	6:40e873bbc5f7	387
MACRUM	6:40e873bbc5f7	388
MACRUM	6:40e873bbc5f7	389	/** \brief Union type to access the Control Registers (CONTROL).
MACRUM	6:40e873bbc5f7	390	*/
MACRUM	6:40e873bbc5f7	391	typedef union
MACRUM	6:40e873bbc5f7	392	{
MACRUM	6:40e873bbc5f7	393	struct
MACRUM	6:40e873bbc5f7	394	{
MACRUM	6:40e873bbc5f7	395	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
MACRUM	6:40e873bbc5f7	396	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
MACRUM	6:40e873bbc5f7	397	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
MACRUM	6:40e873bbc5f7	398	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
MACRUM	6:40e873bbc5f7	399	} b; /!< Structure used for bit access /
MACRUM	6:40e873bbc5f7	400	uint32_t w; /!< Type used for word access /
MACRUM	6:40e873bbc5f7	401	} CONTROL_Type;
MACRUM	6:40e873bbc5f7	402
MACRUM	6:40e873bbc5f7	403	/* CONTROL Register Definitions */
MACRUM	6:40e873bbc5f7	404	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
MACRUM	6:40e873bbc5f7	405	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
MACRUM	6:40e873bbc5f7	406
MACRUM	6:40e873bbc5f7	407	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
MACRUM	6:40e873bbc5f7	408	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
MACRUM	6:40e873bbc5f7	409
MACRUM	6:40e873bbc5f7	410	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
MACRUM	6:40e873bbc5f7	411	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
MACRUM	6:40e873bbc5f7	412
MACRUM	6:40e873bbc5f7	413	/@} end of group CMSIS_CORE /
MACRUM	6:40e873bbc5f7	414
MACRUM	6:40e873bbc5f7	415
MACRUM	6:40e873bbc5f7	416	/** \ingroup CMSIS_core_register
MACRUM	6:40e873bbc5f7	417	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
MACRUM	6:40e873bbc5f7	418	\brief Type definitions for the NVIC Registers
MACRUM	6:40e873bbc5f7	419	@{
MACRUM	6:40e873bbc5f7	420	*/
MACRUM	6:40e873bbc5f7	421
MACRUM	6:40e873bbc5f7	422	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
MACRUM	6:40e873bbc5f7	423	*/
MACRUM	6:40e873bbc5f7	424	typedef struct
MACRUM	6:40e873bbc5f7	425	{
MACRUM	6:40e873bbc5f7	426	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
MACRUM	6:40e873bbc5f7	427	uint32_t RESERVED0[24];
MACRUM	6:40e873bbc5f7	428	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
MACRUM	6:40e873bbc5f7	429	uint32_t RSERVED1[24];
MACRUM	6:40e873bbc5f7	430	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
MACRUM	6:40e873bbc5f7	431	uint32_t RESERVED2[24];
MACRUM	6:40e873bbc5f7	432	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
MACRUM	6:40e873bbc5f7	433	uint32_t RESERVED3[24];
MACRUM	6:40e873bbc5f7	434	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
MACRUM	6:40e873bbc5f7	435	uint32_t RESERVED4[56];
MACRUM	6:40e873bbc5f7	436	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
MACRUM	6:40e873bbc5f7	437	uint32_t RESERVED5[644];
MACRUM	6:40e873bbc5f7	438	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
MACRUM	6:40e873bbc5f7	439	} NVIC_Type;
MACRUM	6:40e873bbc5f7	440
MACRUM	6:40e873bbc5f7	441	/* Software Triggered Interrupt Register Definitions */
MACRUM	6:40e873bbc5f7	442	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
MACRUM	6:40e873bbc5f7	443	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
MACRUM	6:40e873bbc5f7	444
MACRUM	6:40e873bbc5f7	445	/@} end of group CMSIS_NVIC /
MACRUM	6:40e873bbc5f7	446
MACRUM	6:40e873bbc5f7	447
MACRUM	6:40e873bbc5f7	448	/** \ingroup CMSIS_core_register
MACRUM	6:40e873bbc5f7	449	\defgroup CMSIS_SCB System Control Block (SCB)
MACRUM	6:40e873bbc5f7	450	\brief Type definitions for the System Control Block Registers
MACRUM	6:40e873bbc5f7	451	@{
MACRUM	6:40e873bbc5f7	452	*/
MACRUM	6:40e873bbc5f7	453
MACRUM	6:40e873bbc5f7	454	/** \brief Structure type to access the System Control Block (SCB).
MACRUM	6:40e873bbc5f7	455	*/
MACRUM	6:40e873bbc5f7	456	typedef struct
MACRUM	6:40e873bbc5f7	457	{
MACRUM	6:40e873bbc5f7	458	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
MACRUM	6:40e873bbc5f7	459	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
MACRUM	6:40e873bbc5f7	460	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
MACRUM	6:40e873bbc5f7	461	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
MACRUM	6:40e873bbc5f7	462	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
MACRUM	6:40e873bbc5f7	463	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
MACRUM	6:40e873bbc5f7	464	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
MACRUM	6:40e873bbc5f7	465	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
MACRUM	6:40e873bbc5f7	466	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
MACRUM	6:40e873bbc5f7	467	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
MACRUM	6:40e873bbc5f7	468	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
MACRUM	6:40e873bbc5f7	469	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
MACRUM	6:40e873bbc5f7	470	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
MACRUM	6:40e873bbc5f7	471	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
MACRUM	6:40e873bbc5f7	472	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
MACRUM	6:40e873bbc5f7	473	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
MACRUM	6:40e873bbc5f7	474	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
MACRUM	6:40e873bbc5f7	475	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
MACRUM	6:40e873bbc5f7	476	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
MACRUM	6:40e873bbc5f7	477	uint32_t RESERVED0[5];
MACRUM	6:40e873bbc5f7	478	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
MACRUM	6:40e873bbc5f7	479	} SCB_Type;
MACRUM	6:40e873bbc5f7	480
MACRUM	6:40e873bbc5f7	481	/* SCB CPUID Register Definitions */
MACRUM	6:40e873bbc5f7	482	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
MACRUM	6:40e873bbc5f7	483	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
MACRUM	6:40e873bbc5f7	484
MACRUM	6:40e873bbc5f7	485	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
MACRUM	6:40e873bbc5f7	486	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
MACRUM	6:40e873bbc5f7	487
MACRUM	6:40e873bbc5f7	488	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
MACRUM	6:40e873bbc5f7	489	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
MACRUM	6:40e873bbc5f7	490
MACRUM	6:40e873bbc5f7	491	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
MACRUM	6:40e873bbc5f7	492	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
MACRUM	6:40e873bbc5f7	493
MACRUM	6:40e873bbc5f7	494	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
MACRUM	6:40e873bbc5f7	495	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
MACRUM	6:40e873bbc5f7	496
MACRUM	6:40e873bbc5f7	497	/* SCB Interrupt Control State Register Definitions */
MACRUM	6:40e873bbc5f7	498	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
MACRUM	6:40e873bbc5f7	499	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
MACRUM	6:40e873bbc5f7	500
MACRUM	6:40e873bbc5f7	501	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
MACRUM	6:40e873bbc5f7	502	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
MACRUM	6:40e873bbc5f7	503
MACRUM	6:40e873bbc5f7	504	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
MACRUM	6:40e873bbc5f7	505	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
MACRUM	6:40e873bbc5f7	506
MACRUM	6:40e873bbc5f7	507	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
MACRUM	6:40e873bbc5f7	508	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
MACRUM	6:40e873bbc5f7	509
MACRUM	6:40e873bbc5f7	510	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
MACRUM	6:40e873bbc5f7	511	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
MACRUM	6:40e873bbc5f7	512
MACRUM	6:40e873bbc5f7	513	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
MACRUM	6:40e873bbc5f7	514	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
MACRUM	6:40e873bbc5f7	515
MACRUM	6:40e873bbc5f7	516	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
MACRUM	6:40e873bbc5f7	517	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
MACRUM	6:40e873bbc5f7	518
MACRUM	6:40e873bbc5f7	519	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
MACRUM	6:40e873bbc5f7	520	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
MACRUM	6:40e873bbc5f7	521
MACRUM	6:40e873bbc5f7	522	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
MACRUM	6:40e873bbc5f7	523	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
MACRUM	6:40e873bbc5f7	524
MACRUM	6:40e873bbc5f7	525	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
MACRUM	6:40e873bbc5f7	526	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
MACRUM	6:40e873bbc5f7	527
MACRUM	6:40e873bbc5f7	528	/* SCB Vector Table Offset Register Definitions */
MACRUM	6:40e873bbc5f7	529	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
MACRUM	6:40e873bbc5f7	530	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
MACRUM	6:40e873bbc5f7	531
MACRUM	6:40e873bbc5f7	532	/* SCB Application Interrupt and Reset Control Register Definitions */
MACRUM	6:40e873bbc5f7	533	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
MACRUM	6:40e873bbc5f7	534	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
MACRUM	6:40e873bbc5f7	535
MACRUM	6:40e873bbc5f7	536	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
MACRUM	6:40e873bbc5f7	537	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
MACRUM	6:40e873bbc5f7	538
MACRUM	6:40e873bbc5f7	539	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
MACRUM	6:40e873bbc5f7	540	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
MACRUM	6:40e873bbc5f7	541
MACRUM	6:40e873bbc5f7	542	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
MACRUM	6:40e873bbc5f7	543	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
MACRUM	6:40e873bbc5f7	544
MACRUM	6:40e873bbc5f7	545	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
MACRUM	6:40e873bbc5f7	546	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
MACRUM	6:40e873bbc5f7	547
MACRUM	6:40e873bbc5f7	548	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
MACRUM	6:40e873bbc5f7	549	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
MACRUM	6:40e873bbc5f7	550
MACRUM	6:40e873bbc5f7	551	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
MACRUM	6:40e873bbc5f7	552	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
MACRUM	6:40e873bbc5f7	553
MACRUM	6:40e873bbc5f7	554	/* SCB System Control Register Definitions */
MACRUM	6:40e873bbc5f7	555	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
MACRUM	6:40e873bbc5f7	556	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
MACRUM	6:40e873bbc5f7	557
MACRUM	6:40e873bbc5f7	558	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
MACRUM	6:40e873bbc5f7	559	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
MACRUM	6:40e873bbc5f7	560
MACRUM	6:40e873bbc5f7	561	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
MACRUM	6:40e873bbc5f7	562	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
MACRUM	6:40e873bbc5f7	563
MACRUM	6:40e873bbc5f7	564	/* SCB Configuration Control Register Definitions */
MACRUM	6:40e873bbc5f7	565	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
MACRUM	6:40e873bbc5f7	566	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
MACRUM	6:40e873bbc5f7	567
MACRUM	6:40e873bbc5f7	568	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
MACRUM	6:40e873bbc5f7	569	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
MACRUM	6:40e873bbc5f7	570
MACRUM	6:40e873bbc5f7	571	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
MACRUM	6:40e873bbc5f7	572	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
MACRUM	6:40e873bbc5f7	573
MACRUM	6:40e873bbc5f7	574	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
MACRUM	6:40e873bbc5f7	575	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
MACRUM	6:40e873bbc5f7	576
MACRUM	6:40e873bbc5f7	577	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
MACRUM	6:40e873bbc5f7	578	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
MACRUM	6:40e873bbc5f7	579
MACRUM	6:40e873bbc5f7	580	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
MACRUM	6:40e873bbc5f7	581	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
MACRUM	6:40e873bbc5f7	582
MACRUM	6:40e873bbc5f7	583	/* SCB System Handler Control and State Register Definitions */
MACRUM	6:40e873bbc5f7	584	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
MACRUM	6:40e873bbc5f7	585	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
MACRUM	6:40e873bbc5f7	586
MACRUM	6:40e873bbc5f7	587	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
MACRUM	6:40e873bbc5f7	588	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
MACRUM	6:40e873bbc5f7	589
MACRUM	6:40e873bbc5f7	590	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
MACRUM	6:40e873bbc5f7	591	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
MACRUM	6:40e873bbc5f7	592
MACRUM	6:40e873bbc5f7	593	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
MACRUM	6:40e873bbc5f7	594	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
MACRUM	6:40e873bbc5f7	595
MACRUM	6:40e873bbc5f7	596	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
MACRUM	6:40e873bbc5f7	597	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
MACRUM	6:40e873bbc5f7	598
MACRUM	6:40e873bbc5f7	599	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
MACRUM	6:40e873bbc5f7	600	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
MACRUM	6:40e873bbc5f7	601
MACRUM	6:40e873bbc5f7	602	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
MACRUM	6:40e873bbc5f7	603	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
MACRUM	6:40e873bbc5f7	604
MACRUM	6:40e873bbc5f7	605	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
MACRUM	6:40e873bbc5f7	606	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
MACRUM	6:40e873bbc5f7	607
MACRUM	6:40e873bbc5f7	608	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
MACRUM	6:40e873bbc5f7	609	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
MACRUM	6:40e873bbc5f7	610
MACRUM	6:40e873bbc5f7	611	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
MACRUM	6:40e873bbc5f7	612	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
MACRUM	6:40e873bbc5f7	613
MACRUM	6:40e873bbc5f7	614	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
MACRUM	6:40e873bbc5f7	615	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
MACRUM	6:40e873bbc5f7	616
MACRUM	6:40e873bbc5f7	617	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
MACRUM	6:40e873bbc5f7	618	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
MACRUM	6:40e873bbc5f7	619
MACRUM	6:40e873bbc5f7	620	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
MACRUM	6:40e873bbc5f7	621	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
MACRUM	6:40e873bbc5f7	622
MACRUM	6:40e873bbc5f7	623	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
MACRUM	6:40e873bbc5f7	624	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
MACRUM	6:40e873bbc5f7	625
MACRUM	6:40e873bbc5f7	626	/* SCB Configurable Fault Status Registers Definitions */
MACRUM	6:40e873bbc5f7	627	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
MACRUM	6:40e873bbc5f7	628	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
MACRUM	6:40e873bbc5f7	629
MACRUM	6:40e873bbc5f7	630	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
MACRUM	6:40e873bbc5f7	631	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
MACRUM	6:40e873bbc5f7	632
MACRUM	6:40e873bbc5f7	633	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
MACRUM	6:40e873bbc5f7	634	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
MACRUM	6:40e873bbc5f7	635
MACRUM	6:40e873bbc5f7	636	/* SCB Hard Fault Status Registers Definitions */
MACRUM	6:40e873bbc5f7	637	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
MACRUM	6:40e873bbc5f7	638	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
MACRUM	6:40e873bbc5f7	639
MACRUM	6:40e873bbc5f7	640	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
MACRUM	6:40e873bbc5f7	641	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
MACRUM	6:40e873bbc5f7	642
MACRUM	6:40e873bbc5f7	643	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
MACRUM	6:40e873bbc5f7	644	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
MACRUM	6:40e873bbc5f7	645
MACRUM	6:40e873bbc5f7	646	/* SCB Debug Fault Status Register Definitions */
MACRUM	6:40e873bbc5f7	647	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
MACRUM	6:40e873bbc5f7	648	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
MACRUM	6:40e873bbc5f7	649
MACRUM	6:40e873bbc5f7	650	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
MACRUM	6:40e873bbc5f7	651	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
MACRUM	6:40e873bbc5f7	652
MACRUM	6:40e873bbc5f7	653	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
MACRUM	6:40e873bbc5f7	654	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
MACRUM	6:40e873bbc5f7	655
MACRUM	6:40e873bbc5f7	656	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
MACRUM	6:40e873bbc5f7	657	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
MACRUM	6:40e873bbc5f7	658
MACRUM	6:40e873bbc5f7	659	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
MACRUM	6:40e873bbc5f7	660	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
MACRUM	6:40e873bbc5f7	661
MACRUM	6:40e873bbc5f7	662	/@} end of group CMSIS_SCB /
MACRUM	6:40e873bbc5f7	663
MACRUM	6:40e873bbc5f7	664
MACRUM	6:40e873bbc5f7	665	/** \ingroup CMSIS_core_register
MACRUM	6:40e873bbc5f7	666	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
MACRUM	6:40e873bbc5f7	667	\brief Type definitions for the System Control and ID Register not in the SCB
MACRUM	6:40e873bbc5f7	668	@{
MACRUM	6:40e873bbc5f7	669	*/
MACRUM	6:40e873bbc5f7	670
MACRUM	6:40e873bbc5f7	671	/** \brief Structure type to access the System Control and ID Register not in the SCB.
MACRUM	6:40e873bbc5f7	672	*/
MACRUM	6:40e873bbc5f7	673	typedef struct
MACRUM	6:40e873bbc5f7	674	{
MACRUM	6:40e873bbc5f7	675	uint32_t RESERVED0[1];
MACRUM	6:40e873bbc5f7	676	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
MACRUM	6:40e873bbc5f7	677	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
MACRUM	6:40e873bbc5f7	678	} SCnSCB_Type;
MACRUM	6:40e873bbc5f7	679
MACRUM	6:40e873bbc5f7	680	/* Interrupt Controller Type Register Definitions */
MACRUM	6:40e873bbc5f7	681	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
MACRUM	6:40e873bbc5f7	682	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
MACRUM	6:40e873bbc5f7	683
MACRUM	6:40e873bbc5f7	684	/* Auxiliary Control Register Definitions */
MACRUM	6:40e873bbc5f7	685	#define SCnSCB_ACTLR_DISOOFP_Pos 9 /!< ACTLR: DISOOFP Position /
MACRUM	6:40e873bbc5f7	686	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
MACRUM	6:40e873bbc5f7	687
MACRUM	6:40e873bbc5f7	688	#define SCnSCB_ACTLR_DISFPCA_Pos 8 /!< ACTLR: DISFPCA Position /
MACRUM	6:40e873bbc5f7	689	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
MACRUM	6:40e873bbc5f7	690
MACRUM	6:40e873bbc5f7	691	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
MACRUM	6:40e873bbc5f7	692	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
MACRUM	6:40e873bbc5f7	693
MACRUM	6:40e873bbc5f7	694	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
MACRUM	6:40e873bbc5f7	695	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
MACRUM	6:40e873bbc5f7	696
MACRUM	6:40e873bbc5f7	697	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
MACRUM	6:40e873bbc5f7	698	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
MACRUM	6:40e873bbc5f7	699
MACRUM	6:40e873bbc5f7	700	/@} end of group CMSIS_SCnotSCB /
MACRUM	6:40e873bbc5f7	701
MACRUM	6:40e873bbc5f7	702
MACRUM	6:40e873bbc5f7	703	/** \ingroup CMSIS_core_register
MACRUM	6:40e873bbc5f7	704	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
MACRUM	6:40e873bbc5f7	705	\brief Type definitions for the System Timer Registers.
MACRUM	6:40e873bbc5f7	706	@{
MACRUM	6:40e873bbc5f7	707	*/
MACRUM	6:40e873bbc5f7	708
MACRUM	6:40e873bbc5f7	709	/** \brief Structure type to access the System Timer (SysTick).
MACRUM	6:40e873bbc5f7	710	*/
MACRUM	6:40e873bbc5f7	711	typedef struct
MACRUM	6:40e873bbc5f7	712	{
MACRUM	6:40e873bbc5f7	713	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
MACRUM	6:40e873bbc5f7	714	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
MACRUM	6:40e873bbc5f7	715	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
MACRUM	6:40e873bbc5f7	716	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
MACRUM	6:40e873bbc5f7	717	} SysTick_Type;
MACRUM	6:40e873bbc5f7	718
MACRUM	6:40e873bbc5f7	719	/* SysTick Control / Status Register Definitions */
MACRUM	6:40e873bbc5f7	720	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
MACRUM	6:40e873bbc5f7	721	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
MACRUM	6:40e873bbc5f7	722
MACRUM	6:40e873bbc5f7	723	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
MACRUM	6:40e873bbc5f7	724	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
MACRUM	6:40e873bbc5f7	725
MACRUM	6:40e873bbc5f7	726	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
MACRUM	6:40e873bbc5f7	727	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
MACRUM	6:40e873bbc5f7	728
MACRUM	6:40e873bbc5f7	729	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
MACRUM	6:40e873bbc5f7	730	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
MACRUM	6:40e873bbc5f7	731
MACRUM	6:40e873bbc5f7	732	/* SysTick Reload Register Definitions */
MACRUM	6:40e873bbc5f7	733	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
MACRUM	6:40e873bbc5f7	734	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
MACRUM	6:40e873bbc5f7	735
MACRUM	6:40e873bbc5f7	736	/* SysTick Current Register Definitions */
MACRUM	6:40e873bbc5f7	737	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
MACRUM	6:40e873bbc5f7	738	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
MACRUM	6:40e873bbc5f7	739
MACRUM	6:40e873bbc5f7	740	/* SysTick Calibration Register Definitions */
MACRUM	6:40e873bbc5f7	741	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
MACRUM	6:40e873bbc5f7	742	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
MACRUM	6:40e873bbc5f7	743
MACRUM	6:40e873bbc5f7	744	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
MACRUM	6:40e873bbc5f7	745	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
MACRUM	6:40e873bbc5f7	746
MACRUM	6:40e873bbc5f7	747	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
MACRUM	6:40e873bbc5f7	748	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
MACRUM	6:40e873bbc5f7	749
MACRUM	6:40e873bbc5f7	750	/@} end of group CMSIS_SysTick /
MACRUM	6:40e873bbc5f7	751
MACRUM	6:40e873bbc5f7	752
MACRUM	6:40e873bbc5f7	753	/** \ingroup CMSIS_core_register
MACRUM	6:40e873bbc5f7	754	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
MACRUM	6:40e873bbc5f7	755	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
MACRUM	6:40e873bbc5f7	756	@{
MACRUM	6:40e873bbc5f7	757	*/
MACRUM	6:40e873bbc5f7	758
MACRUM	6:40e873bbc5f7	759	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
MACRUM	6:40e873bbc5f7	760	*/
MACRUM	6:40e873bbc5f7	761	typedef struct
MACRUM	6:40e873bbc5f7	762	{
MACRUM	6:40e873bbc5f7	763	__O union
MACRUM	6:40e873bbc5f7	764	{
MACRUM	6:40e873bbc5f7	765	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
MACRUM	6:40e873bbc5f7	766	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
MACRUM	6:40e873bbc5f7	767	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
MACRUM	6:40e873bbc5f7	768	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
MACRUM	6:40e873bbc5f7	769	uint32_t RESERVED0[864];
MACRUM	6:40e873bbc5f7	770	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
MACRUM	6:40e873bbc5f7	771	uint32_t RESERVED1[15];
MACRUM	6:40e873bbc5f7	772	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
MACRUM	6:40e873bbc5f7	773	uint32_t RESERVED2[15];
MACRUM	6:40e873bbc5f7	774	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
MACRUM	6:40e873bbc5f7	775	uint32_t RESERVED3[29];
MACRUM	6:40e873bbc5f7	776	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
MACRUM	6:40e873bbc5f7	777	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
MACRUM	6:40e873bbc5f7	778	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
MACRUM	6:40e873bbc5f7	779	uint32_t RESERVED4[43];
MACRUM	6:40e873bbc5f7	780	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
MACRUM	6:40e873bbc5f7	781	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
MACRUM	6:40e873bbc5f7	782	uint32_t RESERVED5[6];
MACRUM	6:40e873bbc5f7	783	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
MACRUM	6:40e873bbc5f7	784	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
MACRUM	6:40e873bbc5f7	785	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
MACRUM	6:40e873bbc5f7	786	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
MACRUM	6:40e873bbc5f7	787	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
MACRUM	6:40e873bbc5f7	788	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
MACRUM	6:40e873bbc5f7	789	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
MACRUM	6:40e873bbc5f7	790	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
MACRUM	6:40e873bbc5f7	791	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
MACRUM	6:40e873bbc5f7	792	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
MACRUM	6:40e873bbc5f7	793	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
MACRUM	6:40e873bbc5f7	794	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
MACRUM	6:40e873bbc5f7	795	} ITM_Type;
MACRUM	6:40e873bbc5f7	796
MACRUM	6:40e873bbc5f7	797	/* ITM Trace Privilege Register Definitions */
MACRUM	6:40e873bbc5f7	798	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
MACRUM	6:40e873bbc5f7	799	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
MACRUM	6:40e873bbc5f7	800
MACRUM	6:40e873bbc5f7	801	/* ITM Trace Control Register Definitions */
MACRUM	6:40e873bbc5f7	802	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
MACRUM	6:40e873bbc5f7	803	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
MACRUM	6:40e873bbc5f7	804
MACRUM	6:40e873bbc5f7	805	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
MACRUM	6:40e873bbc5f7	806	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
MACRUM	6:40e873bbc5f7	807
MACRUM	6:40e873bbc5f7	808	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
MACRUM	6:40e873bbc5f7	809	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
MACRUM	6:40e873bbc5f7	810
MACRUM	6:40e873bbc5f7	811	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
MACRUM	6:40e873bbc5f7	812	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
MACRUM	6:40e873bbc5f7	813
MACRUM	6:40e873bbc5f7	814	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
MACRUM	6:40e873bbc5f7	815	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
MACRUM	6:40e873bbc5f7	816
MACRUM	6:40e873bbc5f7	817	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
MACRUM	6:40e873bbc5f7	818	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
MACRUM	6:40e873bbc5f7	819
MACRUM	6:40e873bbc5f7	820	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
MACRUM	6:40e873bbc5f7	821	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
MACRUM	6:40e873bbc5f7	822
MACRUM	6:40e873bbc5f7	823	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
MACRUM	6:40e873bbc5f7	824	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
MACRUM	6:40e873bbc5f7	825
MACRUM	6:40e873bbc5f7	826	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
MACRUM	6:40e873bbc5f7	827	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
MACRUM	6:40e873bbc5f7	828
MACRUM	6:40e873bbc5f7	829	/* ITM Integration Write Register Definitions */
MACRUM	6:40e873bbc5f7	830	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
MACRUM	6:40e873bbc5f7	831	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
MACRUM	6:40e873bbc5f7	832
MACRUM	6:40e873bbc5f7	833	/* ITM Integration Read Register Definitions */
MACRUM	6:40e873bbc5f7	834	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
MACRUM	6:40e873bbc5f7	835	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
MACRUM	6:40e873bbc5f7	836
MACRUM	6:40e873bbc5f7	837	/* ITM Integration Mode Control Register Definitions */
MACRUM	6:40e873bbc5f7	838	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
MACRUM	6:40e873bbc5f7	839	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
MACRUM	6:40e873bbc5f7	840
MACRUM	6:40e873bbc5f7	841	/* ITM Lock Status Register Definitions */
MACRUM	6:40e873bbc5f7	842	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
MACRUM	6:40e873bbc5f7	843	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
MACRUM	6:40e873bbc5f7	844
MACRUM	6:40e873bbc5f7	845	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
MACRUM	6:40e873bbc5f7	846	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
MACRUM	6:40e873bbc5f7	847
MACRUM	6:40e873bbc5f7	848	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
MACRUM	6:40e873bbc5f7	849	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
MACRUM	6:40e873bbc5f7	850
MACRUM	6:40e873bbc5f7	851	/@}/ /* end of group CMSIS_ITM */
MACRUM	6:40e873bbc5f7	852
MACRUM	6:40e873bbc5f7	853
MACRUM	6:40e873bbc5f7	854	/** \ingroup CMSIS_core_register
MACRUM	6:40e873bbc5f7	855	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
MACRUM	6:40e873bbc5f7	856	\brief Type definitions for the Data Watchpoint and Trace (DWT)
MACRUM	6:40e873bbc5f7	857	@{
MACRUM	6:40e873bbc5f7	858	*/
MACRUM	6:40e873bbc5f7	859
MACRUM	6:40e873bbc5f7	860	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
MACRUM	6:40e873bbc5f7	861	*/
MACRUM	6:40e873bbc5f7	862	typedef struct
MACRUM	6:40e873bbc5f7	863	{
MACRUM	6:40e873bbc5f7	864	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
MACRUM	6:40e873bbc5f7	865	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
MACRUM	6:40e873bbc5f7	866	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
MACRUM	6:40e873bbc5f7	867	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
MACRUM	6:40e873bbc5f7	868	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
MACRUM	6:40e873bbc5f7	869	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
MACRUM	6:40e873bbc5f7	870	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
MACRUM	6:40e873bbc5f7	871	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
MACRUM	6:40e873bbc5f7	872	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
MACRUM	6:40e873bbc5f7	873	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
MACRUM	6:40e873bbc5f7	874	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
MACRUM	6:40e873bbc5f7	875	uint32_t RESERVED0[1];
MACRUM	6:40e873bbc5f7	876	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
MACRUM	6:40e873bbc5f7	877	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
MACRUM	6:40e873bbc5f7	878	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
MACRUM	6:40e873bbc5f7	879	uint32_t RESERVED1[1];
MACRUM	6:40e873bbc5f7	880	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
MACRUM	6:40e873bbc5f7	881	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
MACRUM	6:40e873bbc5f7	882	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
MACRUM	6:40e873bbc5f7	883	uint32_t RESERVED2[1];
MACRUM	6:40e873bbc5f7	884	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
MACRUM	6:40e873bbc5f7	885	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
MACRUM	6:40e873bbc5f7	886	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
MACRUM	6:40e873bbc5f7	887	} DWT_Type;
MACRUM	6:40e873bbc5f7	888
MACRUM	6:40e873bbc5f7	889	/* DWT Control Register Definitions */
MACRUM	6:40e873bbc5f7	890	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
MACRUM	6:40e873bbc5f7	891	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
MACRUM	6:40e873bbc5f7	892
MACRUM	6:40e873bbc5f7	893	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
MACRUM	6:40e873bbc5f7	894	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
MACRUM	6:40e873bbc5f7	895
MACRUM	6:40e873bbc5f7	896	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
MACRUM	6:40e873bbc5f7	897	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
MACRUM	6:40e873bbc5f7	898
MACRUM	6:40e873bbc5f7	899	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
MACRUM	6:40e873bbc5f7	900	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
MACRUM	6:40e873bbc5f7	901
MACRUM	6:40e873bbc5f7	902	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
MACRUM	6:40e873bbc5f7	903	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
MACRUM	6:40e873bbc5f7	904
MACRUM	6:40e873bbc5f7	905	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
MACRUM	6:40e873bbc5f7	906	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
MACRUM	6:40e873bbc5f7	907
MACRUM	6:40e873bbc5f7	908	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
MACRUM	6:40e873bbc5f7	909	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
MACRUM	6:40e873bbc5f7	910
MACRUM	6:40e873bbc5f7	911	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
MACRUM	6:40e873bbc5f7	912	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
MACRUM	6:40e873bbc5f7	913
MACRUM	6:40e873bbc5f7	914	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
MACRUM	6:40e873bbc5f7	915	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
MACRUM	6:40e873bbc5f7	916
MACRUM	6:40e873bbc5f7	917	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
MACRUM	6:40e873bbc5f7	918	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
MACRUM	6:40e873bbc5f7	919
MACRUM	6:40e873bbc5f7	920	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
MACRUM	6:40e873bbc5f7	921	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
MACRUM	6:40e873bbc5f7	922
MACRUM	6:40e873bbc5f7	923	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
MACRUM	6:40e873bbc5f7	924	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
MACRUM	6:40e873bbc5f7	925
MACRUM	6:40e873bbc5f7	926	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
MACRUM	6:40e873bbc5f7	927	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
MACRUM	6:40e873bbc5f7	928
MACRUM	6:40e873bbc5f7	929	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
MACRUM	6:40e873bbc5f7	930	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
MACRUM	6:40e873bbc5f7	931
MACRUM	6:40e873bbc5f7	932	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
MACRUM	6:40e873bbc5f7	933	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
MACRUM	6:40e873bbc5f7	934
MACRUM	6:40e873bbc5f7	935	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
MACRUM	6:40e873bbc5f7	936	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
MACRUM	6:40e873bbc5f7	937
MACRUM	6:40e873bbc5f7	938	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
MACRUM	6:40e873bbc5f7	939	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
MACRUM	6:40e873bbc5f7	940
MACRUM	6:40e873bbc5f7	941	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
MACRUM	6:40e873bbc5f7	942	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
MACRUM	6:40e873bbc5f7	943
MACRUM	6:40e873bbc5f7	944	/* DWT CPI Count Register Definitions */
MACRUM	6:40e873bbc5f7	945	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
MACRUM	6:40e873bbc5f7	946	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
MACRUM	6:40e873bbc5f7	947
MACRUM	6:40e873bbc5f7	948	/* DWT Exception Overhead Count Register Definitions */
MACRUM	6:40e873bbc5f7	949	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
MACRUM	6:40e873bbc5f7	950	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
MACRUM	6:40e873bbc5f7	951
MACRUM	6:40e873bbc5f7	952	/* DWT Sleep Count Register Definitions */
MACRUM	6:40e873bbc5f7	953	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
MACRUM	6:40e873bbc5f7	954	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
MACRUM	6:40e873bbc5f7	955
MACRUM	6:40e873bbc5f7	956	/* DWT LSU Count Register Definitions */
MACRUM	6:40e873bbc5f7	957	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
MACRUM	6:40e873bbc5f7	958	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
MACRUM	6:40e873bbc5f7	959
MACRUM	6:40e873bbc5f7	960	/* DWT Folded-instruction Count Register Definitions */
MACRUM	6:40e873bbc5f7	961	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
MACRUM	6:40e873bbc5f7	962	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
MACRUM	6:40e873bbc5f7	963
MACRUM	6:40e873bbc5f7	964	/* DWT Comparator Mask Register Definitions */
MACRUM	6:40e873bbc5f7	965	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
MACRUM	6:40e873bbc5f7	966	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
MACRUM	6:40e873bbc5f7	967
MACRUM	6:40e873bbc5f7	968	/* DWT Comparator Function Register Definitions */
MACRUM	6:40e873bbc5f7	969	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
MACRUM	6:40e873bbc5f7	970	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
MACRUM	6:40e873bbc5f7	971
MACRUM	6:40e873bbc5f7	972	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
MACRUM	6:40e873bbc5f7	973	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
MACRUM	6:40e873bbc5f7	974
MACRUM	6:40e873bbc5f7	975	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
MACRUM	6:40e873bbc5f7	976	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
MACRUM	6:40e873bbc5f7	977
MACRUM	6:40e873bbc5f7	978	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
MACRUM	6:40e873bbc5f7	979	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
MACRUM	6:40e873bbc5f7	980
MACRUM	6:40e873bbc5f7	981	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
MACRUM	6:40e873bbc5f7	982	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
MACRUM	6:40e873bbc5f7	983
MACRUM	6:40e873bbc5f7	984	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
MACRUM	6:40e873bbc5f7	985	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
MACRUM	6:40e873bbc5f7	986
MACRUM	6:40e873bbc5f7	987	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
MACRUM	6:40e873bbc5f7	988	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
MACRUM	6:40e873bbc5f7	989
MACRUM	6:40e873bbc5f7	990	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
MACRUM	6:40e873bbc5f7	991	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
MACRUM	6:40e873bbc5f7	992
MACRUM	6:40e873bbc5f7	993	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
MACRUM	6:40e873bbc5f7	994	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
MACRUM	6:40e873bbc5f7	995
MACRUM	6:40e873bbc5f7	996	/@}/ /* end of group CMSIS_DWT */
MACRUM	6:40e873bbc5f7	997
MACRUM	6:40e873bbc5f7	998
MACRUM	6:40e873bbc5f7	999	/** \ingroup CMSIS_core_register
MACRUM	6:40e873bbc5f7	1000	\defgroup CMSIS_TPI Trace Port Interface (TPI)
MACRUM	6:40e873bbc5f7	1001	\brief Type definitions for the Trace Port Interface (TPI)
MACRUM	6:40e873bbc5f7	1002	@{
MACRUM	6:40e873bbc5f7	1003	*/
MACRUM	6:40e873bbc5f7	1004
MACRUM	6:40e873bbc5f7	1005	/** \brief Structure type to access the Trace Port Interface Register (TPI).
MACRUM	6:40e873bbc5f7	1006	*/
MACRUM	6:40e873bbc5f7	1007	typedef struct
MACRUM	6:40e873bbc5f7	1008	{
MACRUM	6:40e873bbc5f7	1009	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
MACRUM	6:40e873bbc5f7	1010	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
MACRUM	6:40e873bbc5f7	1011	uint32_t RESERVED0[2];
MACRUM	6:40e873bbc5f7	1012	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
MACRUM	6:40e873bbc5f7	1013	uint32_t RESERVED1[55];
MACRUM	6:40e873bbc5f7	1014	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
MACRUM	6:40e873bbc5f7	1015	uint32_t RESERVED2[131];
MACRUM	6:40e873bbc5f7	1016	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
MACRUM	6:40e873bbc5f7	1017	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
MACRUM	6:40e873bbc5f7	1018	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
MACRUM	6:40e873bbc5f7	1019	uint32_t RESERVED3[759];
MACRUM	6:40e873bbc5f7	1020	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
MACRUM	6:40e873bbc5f7	1021	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
MACRUM	6:40e873bbc5f7	1022	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
MACRUM	6:40e873bbc5f7	1023	uint32_t RESERVED4[1];
MACRUM	6:40e873bbc5f7	1024	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
MACRUM	6:40e873bbc5f7	1025	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
MACRUM	6:40e873bbc5f7	1026	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
MACRUM	6:40e873bbc5f7	1027	uint32_t RESERVED5[39];
MACRUM	6:40e873bbc5f7	1028	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
MACRUM	6:40e873bbc5f7	1029	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
MACRUM	6:40e873bbc5f7	1030	uint32_t RESERVED7[8];
MACRUM	6:40e873bbc5f7	1031	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
MACRUM	6:40e873bbc5f7	1032	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
MACRUM	6:40e873bbc5f7	1033	} TPI_Type;
MACRUM	6:40e873bbc5f7	1034
MACRUM	6:40e873bbc5f7	1035	/* TPI Asynchronous Clock Prescaler Register Definitions */
MACRUM	6:40e873bbc5f7	1036	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
MACRUM	6:40e873bbc5f7	1037	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
MACRUM	6:40e873bbc5f7	1038
MACRUM	6:40e873bbc5f7	1039	/* TPI Selected Pin Protocol Register Definitions */
MACRUM	6:40e873bbc5f7	1040	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
MACRUM	6:40e873bbc5f7	1041	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
MACRUM	6:40e873bbc5f7	1042
MACRUM	6:40e873bbc5f7	1043	/* TPI Formatter and Flush Status Register Definitions */
MACRUM	6:40e873bbc5f7	1044	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
MACRUM	6:40e873bbc5f7	1045	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
MACRUM	6:40e873bbc5f7	1046
MACRUM	6:40e873bbc5f7	1047	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
MACRUM	6:40e873bbc5f7	1048	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
MACRUM	6:40e873bbc5f7	1049
MACRUM	6:40e873bbc5f7	1050	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
MACRUM	6:40e873bbc5f7	1051	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
MACRUM	6:40e873bbc5f7	1052
MACRUM	6:40e873bbc5f7	1053	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
MACRUM	6:40e873bbc5f7	1054	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
MACRUM	6:40e873bbc5f7	1055
MACRUM	6:40e873bbc5f7	1056	/* TPI Formatter and Flush Control Register Definitions */
MACRUM	6:40e873bbc5f7	1057	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
MACRUM	6:40e873bbc5f7	1058	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
MACRUM	6:40e873bbc5f7	1059
MACRUM	6:40e873bbc5f7	1060	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
MACRUM	6:40e873bbc5f7	1061	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
MACRUM	6:40e873bbc5f7	1062
MACRUM	6:40e873bbc5f7	1063	/* TPI TRIGGER Register Definitions */
MACRUM	6:40e873bbc5f7	1064	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
MACRUM	6:40e873bbc5f7	1065	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
MACRUM	6:40e873bbc5f7	1066
MACRUM	6:40e873bbc5f7	1067	/* TPI Integration ETM Data Register Definitions (FIFO0) */
MACRUM	6:40e873bbc5f7	1068	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
MACRUM	6:40e873bbc5f7	1069	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
MACRUM	6:40e873bbc5f7	1070
MACRUM	6:40e873bbc5f7	1071	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
MACRUM	6:40e873bbc5f7	1072	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
MACRUM	6:40e873bbc5f7	1073
MACRUM	6:40e873bbc5f7	1074	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
MACRUM	6:40e873bbc5f7	1075	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
MACRUM	6:40e873bbc5f7	1076
MACRUM	6:40e873bbc5f7	1077	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
MACRUM	6:40e873bbc5f7	1078	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
MACRUM	6:40e873bbc5f7	1079
MACRUM	6:40e873bbc5f7	1080	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
MACRUM	6:40e873bbc5f7	1081	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
MACRUM	6:40e873bbc5f7	1082
MACRUM	6:40e873bbc5f7	1083	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
MACRUM	6:40e873bbc5f7	1084	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
MACRUM	6:40e873bbc5f7	1085
MACRUM	6:40e873bbc5f7	1086	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
MACRUM	6:40e873bbc5f7	1087	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
MACRUM	6:40e873bbc5f7	1088
MACRUM	6:40e873bbc5f7	1089	/* TPI ITATBCTR2 Register Definitions */
MACRUM	6:40e873bbc5f7	1090	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
MACRUM	6:40e873bbc5f7	1091	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
MACRUM	6:40e873bbc5f7	1092
MACRUM	6:40e873bbc5f7	1093	/* TPI Integration ITM Data Register Definitions (FIFO1) */
MACRUM	6:40e873bbc5f7	1094	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
MACRUM	6:40e873bbc5f7	1095	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
MACRUM	6:40e873bbc5f7	1096
MACRUM	6:40e873bbc5f7	1097	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
MACRUM	6:40e873bbc5f7	1098	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
MACRUM	6:40e873bbc5f7	1099
MACRUM	6:40e873bbc5f7	1100	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
MACRUM	6:40e873bbc5f7	1101	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
MACRUM	6:40e873bbc5f7	1102
MACRUM	6:40e873bbc5f7	1103	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
MACRUM	6:40e873bbc5f7	1104	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
MACRUM	6:40e873bbc5f7	1105
MACRUM	6:40e873bbc5f7	1106	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
MACRUM	6:40e873bbc5f7	1107	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
MACRUM	6:40e873bbc5f7	1108
MACRUM	6:40e873bbc5f7	1109	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
MACRUM	6:40e873bbc5f7	1110	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
MACRUM	6:40e873bbc5f7	1111
MACRUM	6:40e873bbc5f7	1112	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
MACRUM	6:40e873bbc5f7	1113	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
MACRUM	6:40e873bbc5f7	1114
MACRUM	6:40e873bbc5f7	1115	/* TPI ITATBCTR0 Register Definitions */
MACRUM	6:40e873bbc5f7	1116	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
MACRUM	6:40e873bbc5f7	1117	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
MACRUM	6:40e873bbc5f7	1118
MACRUM	6:40e873bbc5f7	1119	/* TPI Integration Mode Control Register Definitions */
MACRUM	6:40e873bbc5f7	1120	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
MACRUM	6:40e873bbc5f7	1121	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
MACRUM	6:40e873bbc5f7	1122
MACRUM	6:40e873bbc5f7	1123	/* TPI DEVID Register Definitions */
MACRUM	6:40e873bbc5f7	1124	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
MACRUM	6:40e873bbc5f7	1125	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
MACRUM	6:40e873bbc5f7	1126
MACRUM	6:40e873bbc5f7	1127	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
MACRUM	6:40e873bbc5f7	1128	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
MACRUM	6:40e873bbc5f7	1129
MACRUM	6:40e873bbc5f7	1130	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
MACRUM	6:40e873bbc5f7	1131	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
MACRUM	6:40e873bbc5f7	1132
MACRUM	6:40e873bbc5f7	1133	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
MACRUM	6:40e873bbc5f7	1134	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
MACRUM	6:40e873bbc5f7	1135
MACRUM	6:40e873bbc5f7	1136	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
MACRUM	6:40e873bbc5f7	1137	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
MACRUM	6:40e873bbc5f7	1138
MACRUM	6:40e873bbc5f7	1139	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
MACRUM	6:40e873bbc5f7	1140	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
MACRUM	6:40e873bbc5f7	1141
MACRUM	6:40e873bbc5f7	1142	/* TPI DEVTYPE Register Definitions */
MACRUM	6:40e873bbc5f7	1143	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
MACRUM	6:40e873bbc5f7	1144	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
MACRUM	6:40e873bbc5f7	1145
MACRUM	6:40e873bbc5f7	1146	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
MACRUM	6:40e873bbc5f7	1147	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
MACRUM	6:40e873bbc5f7	1148
MACRUM	6:40e873bbc5f7	1149	/@}/ /* end of group CMSIS_TPI */
MACRUM	6:40e873bbc5f7	1150
MACRUM	6:40e873bbc5f7	1151
MACRUM	6:40e873bbc5f7	1152	#if (__MPU_PRESENT == 1)
MACRUM	6:40e873bbc5f7	1153	/** \ingroup CMSIS_core_register
MACRUM	6:40e873bbc5f7	1154	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
MACRUM	6:40e873bbc5f7	1155	\brief Type definitions for the Memory Protection Unit (MPU)
MACRUM	6:40e873bbc5f7	1156	@{
MACRUM	6:40e873bbc5f7	1157	*/
MACRUM	6:40e873bbc5f7	1158
MACRUM	6:40e873bbc5f7	1159	/** \brief Structure type to access the Memory Protection Unit (MPU).
MACRUM	6:40e873bbc5f7	1160	*/
MACRUM	6:40e873bbc5f7	1161	typedef struct
MACRUM	6:40e873bbc5f7	1162	{
MACRUM	6:40e873bbc5f7	1163	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
MACRUM	6:40e873bbc5f7	1164	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
MACRUM	6:40e873bbc5f7	1165	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
MACRUM	6:40e873bbc5f7	1166	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
MACRUM	6:40e873bbc5f7	1167	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
MACRUM	6:40e873bbc5f7	1168	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
MACRUM	6:40e873bbc5f7	1169	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
MACRUM	6:40e873bbc5f7	1170	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
MACRUM	6:40e873bbc5f7	1171	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
MACRUM	6:40e873bbc5f7	1172	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
MACRUM	6:40e873bbc5f7	1173	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
MACRUM	6:40e873bbc5f7	1174	} MPU_Type;
MACRUM	6:40e873bbc5f7	1175
MACRUM	6:40e873bbc5f7	1176	/* MPU Type Register */
MACRUM	6:40e873bbc5f7	1177	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
MACRUM	6:40e873bbc5f7	1178	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
MACRUM	6:40e873bbc5f7	1179
MACRUM	6:40e873bbc5f7	1180	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
MACRUM	6:40e873bbc5f7	1181	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
MACRUM	6:40e873bbc5f7	1182
MACRUM	6:40e873bbc5f7	1183	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
MACRUM	6:40e873bbc5f7	1184	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
MACRUM	6:40e873bbc5f7	1185
MACRUM	6:40e873bbc5f7	1186	/* MPU Control Register */
MACRUM	6:40e873bbc5f7	1187	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
MACRUM	6:40e873bbc5f7	1188	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
MACRUM	6:40e873bbc5f7	1189
MACRUM	6:40e873bbc5f7	1190	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
MACRUM	6:40e873bbc5f7	1191	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
MACRUM	6:40e873bbc5f7	1192
MACRUM	6:40e873bbc5f7	1193	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
MACRUM	6:40e873bbc5f7	1194	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
MACRUM	6:40e873bbc5f7	1195
MACRUM	6:40e873bbc5f7	1196	/* MPU Region Number Register */
MACRUM	6:40e873bbc5f7	1197	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
MACRUM	6:40e873bbc5f7	1198	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
MACRUM	6:40e873bbc5f7	1199
MACRUM	6:40e873bbc5f7	1200	/* MPU Region Base Address Register */
MACRUM	6:40e873bbc5f7	1201	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
MACRUM	6:40e873bbc5f7	1202	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
MACRUM	6:40e873bbc5f7	1203
MACRUM	6:40e873bbc5f7	1204	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
MACRUM	6:40e873bbc5f7	1205	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
MACRUM	6:40e873bbc5f7	1206
MACRUM	6:40e873bbc5f7	1207	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
MACRUM	6:40e873bbc5f7	1208	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
MACRUM	6:40e873bbc5f7	1209
MACRUM	6:40e873bbc5f7	1210	/* MPU Region Attribute and Size Register */
MACRUM	6:40e873bbc5f7	1211	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
MACRUM	6:40e873bbc5f7	1212	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
MACRUM	6:40e873bbc5f7	1213
MACRUM	6:40e873bbc5f7	1214	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
MACRUM	6:40e873bbc5f7	1215	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
MACRUM	6:40e873bbc5f7	1216
MACRUM	6:40e873bbc5f7	1217	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
MACRUM	6:40e873bbc5f7	1218	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
MACRUM	6:40e873bbc5f7	1219
MACRUM	6:40e873bbc5f7	1220	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
MACRUM	6:40e873bbc5f7	1221	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
MACRUM	6:40e873bbc5f7	1222
MACRUM	6:40e873bbc5f7	1223	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
MACRUM	6:40e873bbc5f7	1224	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
MACRUM	6:40e873bbc5f7	1225
MACRUM	6:40e873bbc5f7	1226	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
MACRUM	6:40e873bbc5f7	1227	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
MACRUM	6:40e873bbc5f7	1228
MACRUM	6:40e873bbc5f7	1229	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
MACRUM	6:40e873bbc5f7	1230	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
MACRUM	6:40e873bbc5f7	1231
MACRUM	6:40e873bbc5f7	1232	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
MACRUM	6:40e873bbc5f7	1233	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
MACRUM	6:40e873bbc5f7	1234
MACRUM	6:40e873bbc5f7	1235	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
MACRUM	6:40e873bbc5f7	1236	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
MACRUM	6:40e873bbc5f7	1237
MACRUM	6:40e873bbc5f7	1238	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
MACRUM	6:40e873bbc5f7	1239	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
MACRUM	6:40e873bbc5f7	1240
MACRUM	6:40e873bbc5f7	1241	/@} end of group CMSIS_MPU /
MACRUM	6:40e873bbc5f7	1242	#endif
MACRUM	6:40e873bbc5f7	1243
MACRUM	6:40e873bbc5f7	1244
MACRUM	6:40e873bbc5f7	1245	#if (__FPU_PRESENT == 1)
MACRUM	6:40e873bbc5f7	1246	/** \ingroup CMSIS_core_register
MACRUM	6:40e873bbc5f7	1247	\defgroup CMSIS_FPU Floating Point Unit (FPU)
MACRUM	6:40e873bbc5f7	1248	\brief Type definitions for the Floating Point Unit (FPU)
MACRUM	6:40e873bbc5f7	1249	@{
MACRUM	6:40e873bbc5f7	1250	*/
MACRUM	6:40e873bbc5f7	1251
MACRUM	6:40e873bbc5f7	1252	/** \brief Structure type to access the Floating Point Unit (FPU).
MACRUM	6:40e873bbc5f7	1253	*/
MACRUM	6:40e873bbc5f7	1254	typedef struct
MACRUM	6:40e873bbc5f7	1255	{
MACRUM	6:40e873bbc5f7	1256	uint32_t RESERVED0[1];
MACRUM	6:40e873bbc5f7	1257	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
MACRUM	6:40e873bbc5f7	1258	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
MACRUM	6:40e873bbc5f7	1259	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
MACRUM	6:40e873bbc5f7	1260	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
MACRUM	6:40e873bbc5f7	1261	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
MACRUM	6:40e873bbc5f7	1262	} FPU_Type;
MACRUM	6:40e873bbc5f7	1263
MACRUM	6:40e873bbc5f7	1264	/* Floating-Point Context Control Register */
MACRUM	6:40e873bbc5f7	1265	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
MACRUM	6:40e873bbc5f7	1266	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
MACRUM	6:40e873bbc5f7	1267
MACRUM	6:40e873bbc5f7	1268	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
MACRUM	6:40e873bbc5f7	1269	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
MACRUM	6:40e873bbc5f7	1270
MACRUM	6:40e873bbc5f7	1271	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
MACRUM	6:40e873bbc5f7	1272	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
MACRUM	6:40e873bbc5f7	1273
MACRUM	6:40e873bbc5f7	1274	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
MACRUM	6:40e873bbc5f7	1275	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
MACRUM	6:40e873bbc5f7	1276
MACRUM	6:40e873bbc5f7	1277	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
MACRUM	6:40e873bbc5f7	1278	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
MACRUM	6:40e873bbc5f7	1279
MACRUM	6:40e873bbc5f7	1280	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
MACRUM	6:40e873bbc5f7	1281	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
MACRUM	6:40e873bbc5f7	1282
MACRUM	6:40e873bbc5f7	1283	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
MACRUM	6:40e873bbc5f7	1284	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
MACRUM	6:40e873bbc5f7	1285
MACRUM	6:40e873bbc5f7	1286	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
MACRUM	6:40e873bbc5f7	1287	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
MACRUM	6:40e873bbc5f7	1288
MACRUM	6:40e873bbc5f7	1289	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
MACRUM	6:40e873bbc5f7	1290	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
MACRUM	6:40e873bbc5f7	1291
MACRUM	6:40e873bbc5f7	1292	/* Floating-Point Context Address Register */
MACRUM	6:40e873bbc5f7	1293	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
MACRUM	6:40e873bbc5f7	1294	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
MACRUM	6:40e873bbc5f7	1295
MACRUM	6:40e873bbc5f7	1296	/* Floating-Point Default Status Control Register */
MACRUM	6:40e873bbc5f7	1297	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
MACRUM	6:40e873bbc5f7	1298	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
MACRUM	6:40e873bbc5f7	1299
MACRUM	6:40e873bbc5f7	1300	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
MACRUM	6:40e873bbc5f7	1301	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
MACRUM	6:40e873bbc5f7	1302
MACRUM	6:40e873bbc5f7	1303	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
MACRUM	6:40e873bbc5f7	1304	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
MACRUM	6:40e873bbc5f7	1305
MACRUM	6:40e873bbc5f7	1306	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
MACRUM	6:40e873bbc5f7	1307	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
MACRUM	6:40e873bbc5f7	1308
MACRUM	6:40e873bbc5f7	1309	/* Media and FP Feature Register 0 */
MACRUM	6:40e873bbc5f7	1310	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
MACRUM	6:40e873bbc5f7	1311	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
MACRUM	6:40e873bbc5f7	1312
MACRUM	6:40e873bbc5f7	1313	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
MACRUM	6:40e873bbc5f7	1314	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
MACRUM	6:40e873bbc5f7	1315
MACRUM	6:40e873bbc5f7	1316	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
MACRUM	6:40e873bbc5f7	1317	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
MACRUM	6:40e873bbc5f7	1318
MACRUM	6:40e873bbc5f7	1319	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
MACRUM	6:40e873bbc5f7	1320	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
MACRUM	6:40e873bbc5f7	1321
MACRUM	6:40e873bbc5f7	1322	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
MACRUM	6:40e873bbc5f7	1323	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
MACRUM	6:40e873bbc5f7	1324
MACRUM	6:40e873bbc5f7	1325	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
MACRUM	6:40e873bbc5f7	1326	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
MACRUM	6:40e873bbc5f7	1327
MACRUM	6:40e873bbc5f7	1328	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
MACRUM	6:40e873bbc5f7	1329	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
MACRUM	6:40e873bbc5f7	1330
MACRUM	6:40e873bbc5f7	1331	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
MACRUM	6:40e873bbc5f7	1332	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
MACRUM	6:40e873bbc5f7	1333
MACRUM	6:40e873bbc5f7	1334	/* Media and FP Feature Register 1 */
MACRUM	6:40e873bbc5f7	1335	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
MACRUM	6:40e873bbc5f7	1336	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
MACRUM	6:40e873bbc5f7	1337
MACRUM	6:40e873bbc5f7	1338	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
MACRUM	6:40e873bbc5f7	1339	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
MACRUM	6:40e873bbc5f7	1340
MACRUM	6:40e873bbc5f7	1341	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
MACRUM	6:40e873bbc5f7	1342	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
MACRUM	6:40e873bbc5f7	1343
MACRUM	6:40e873bbc5f7	1344	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
MACRUM	6:40e873bbc5f7	1345	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
MACRUM	6:40e873bbc5f7	1346
MACRUM	6:40e873bbc5f7	1347	/@} end of group CMSIS_FPU /
MACRUM	6:40e873bbc5f7	1348	#endif
MACRUM	6:40e873bbc5f7	1349
MACRUM	6:40e873bbc5f7	1350
MACRUM	6:40e873bbc5f7	1351	/** \ingroup CMSIS_core_register
MACRUM	6:40e873bbc5f7	1352	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
MACRUM	6:40e873bbc5f7	1353	\brief Type definitions for the Core Debug Registers
MACRUM	6:40e873bbc5f7	1354	@{
MACRUM	6:40e873bbc5f7	1355	*/
MACRUM	6:40e873bbc5f7	1356
MACRUM	6:40e873bbc5f7	1357	/** \brief Structure type to access the Core Debug Register (CoreDebug).
MACRUM	6:40e873bbc5f7	1358	*/
MACRUM	6:40e873bbc5f7	1359	typedef struct
MACRUM	6:40e873bbc5f7	1360	{
MACRUM	6:40e873bbc5f7	1361	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
MACRUM	6:40e873bbc5f7	1362	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
MACRUM	6:40e873bbc5f7	1363	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
MACRUM	6:40e873bbc5f7	1364	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
MACRUM	6:40e873bbc5f7	1365	} CoreDebug_Type;
MACRUM	6:40e873bbc5f7	1366
MACRUM	6:40e873bbc5f7	1367	/* Debug Halting Control and Status Register */
MACRUM	6:40e873bbc5f7	1368	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
MACRUM	6:40e873bbc5f7	1369	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
MACRUM	6:40e873bbc5f7	1370
MACRUM	6:40e873bbc5f7	1371	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
MACRUM	6:40e873bbc5f7	1372	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
MACRUM	6:40e873bbc5f7	1373
MACRUM	6:40e873bbc5f7	1374	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
MACRUM	6:40e873bbc5f7	1375	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
MACRUM	6:40e873bbc5f7	1376
MACRUM	6:40e873bbc5f7	1377	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
MACRUM	6:40e873bbc5f7	1378	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
MACRUM	6:40e873bbc5f7	1379
MACRUM	6:40e873bbc5f7	1380	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
MACRUM	6:40e873bbc5f7	1381	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
MACRUM	6:40e873bbc5f7	1382
MACRUM	6:40e873bbc5f7	1383	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
MACRUM	6:40e873bbc5f7	1384	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
MACRUM	6:40e873bbc5f7	1385
MACRUM	6:40e873bbc5f7	1386	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
MACRUM	6:40e873bbc5f7	1387	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
MACRUM	6:40e873bbc5f7	1388
MACRUM	6:40e873bbc5f7	1389	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
MACRUM	6:40e873bbc5f7	1390	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
MACRUM	6:40e873bbc5f7	1391
MACRUM	6:40e873bbc5f7	1392	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
MACRUM	6:40e873bbc5f7	1393	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
MACRUM	6:40e873bbc5f7	1394
MACRUM	6:40e873bbc5f7	1395	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
MACRUM	6:40e873bbc5f7	1396	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
MACRUM	6:40e873bbc5f7	1397
MACRUM	6:40e873bbc5f7	1398	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
MACRUM	6:40e873bbc5f7	1399	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
MACRUM	6:40e873bbc5f7	1400
MACRUM	6:40e873bbc5f7	1401	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
MACRUM	6:40e873bbc5f7	1402	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
MACRUM	6:40e873bbc5f7	1403
MACRUM	6:40e873bbc5f7	1404	/* Debug Core Register Selector Register */
MACRUM	6:40e873bbc5f7	1405	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
MACRUM	6:40e873bbc5f7	1406	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
MACRUM	6:40e873bbc5f7	1407
MACRUM	6:40e873bbc5f7	1408	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
MACRUM	6:40e873bbc5f7	1409	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
MACRUM	6:40e873bbc5f7	1410
MACRUM	6:40e873bbc5f7	1411	/* Debug Exception and Monitor Control Register */
MACRUM	6:40e873bbc5f7	1412	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
MACRUM	6:40e873bbc5f7	1413	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
MACRUM	6:40e873bbc5f7	1414
MACRUM	6:40e873bbc5f7	1415	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
MACRUM	6:40e873bbc5f7	1416	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
MACRUM	6:40e873bbc5f7	1417
MACRUM	6:40e873bbc5f7	1418	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
MACRUM	6:40e873bbc5f7	1419	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
MACRUM	6:40e873bbc5f7	1420
MACRUM	6:40e873bbc5f7	1421	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
MACRUM	6:40e873bbc5f7	1422	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
MACRUM	6:40e873bbc5f7	1423
MACRUM	6:40e873bbc5f7	1424	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
MACRUM	6:40e873bbc5f7	1425	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
MACRUM	6:40e873bbc5f7	1426
MACRUM	6:40e873bbc5f7	1427	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
MACRUM	6:40e873bbc5f7	1428	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
MACRUM	6:40e873bbc5f7	1429
MACRUM	6:40e873bbc5f7	1430	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
MACRUM	6:40e873bbc5f7	1431	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
MACRUM	6:40e873bbc5f7	1432
MACRUM	6:40e873bbc5f7	1433	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
MACRUM	6:40e873bbc5f7	1434	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
MACRUM	6:40e873bbc5f7	1435
MACRUM	6:40e873bbc5f7	1436	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
MACRUM	6:40e873bbc5f7	1437	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
MACRUM	6:40e873bbc5f7	1438
MACRUM	6:40e873bbc5f7	1439	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
MACRUM	6:40e873bbc5f7	1440	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
MACRUM	6:40e873bbc5f7	1441
MACRUM	6:40e873bbc5f7	1442	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
MACRUM	6:40e873bbc5f7	1443	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
MACRUM	6:40e873bbc5f7	1444
MACRUM	6:40e873bbc5f7	1445	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
MACRUM	6:40e873bbc5f7	1446	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
MACRUM	6:40e873bbc5f7	1447
MACRUM	6:40e873bbc5f7	1448	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
MACRUM	6:40e873bbc5f7	1449	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
MACRUM	6:40e873bbc5f7	1450
MACRUM	6:40e873bbc5f7	1451	/@} end of group CMSIS_CoreDebug /
MACRUM	6:40e873bbc5f7	1452
MACRUM	6:40e873bbc5f7	1453
MACRUM	6:40e873bbc5f7	1454	/** \ingroup CMSIS_core_register
MACRUM	6:40e873bbc5f7	1455	\defgroup CMSIS_core_base Core Definitions
MACRUM	6:40e873bbc5f7	1456	\brief Definitions for base addresses, unions, and structures.
MACRUM	6:40e873bbc5f7	1457	@{
MACRUM	6:40e873bbc5f7	1458	*/
MACRUM	6:40e873bbc5f7	1459
MACRUM	6:40e873bbc5f7	1460	/* Memory mapping of Cortex-M4 Hardware */
MACRUM	6:40e873bbc5f7	1461	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
MACRUM	6:40e873bbc5f7	1462	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
MACRUM	6:40e873bbc5f7	1463	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
MACRUM	6:40e873bbc5f7	1464	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
MACRUM	6:40e873bbc5f7	1465	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
MACRUM	6:40e873bbc5f7	1466	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
MACRUM	6:40e873bbc5f7	1467	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
MACRUM	6:40e873bbc5f7	1468	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
MACRUM	6:40e873bbc5f7	1469
MACRUM	6:40e873bbc5f7	1470	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
MACRUM	6:40e873bbc5f7	1471	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
MACRUM	6:40e873bbc5f7	1472	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
MACRUM	6:40e873bbc5f7	1473	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
MACRUM	6:40e873bbc5f7	1474	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
MACRUM	6:40e873bbc5f7	1475	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
MACRUM	6:40e873bbc5f7	1476	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
MACRUM	6:40e873bbc5f7	1477	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
MACRUM	6:40e873bbc5f7	1478
MACRUM	6:40e873bbc5f7	1479	#if (__MPU_PRESENT == 1)
MACRUM	6:40e873bbc5f7	1480	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
MACRUM	6:40e873bbc5f7	1481	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
MACRUM	6:40e873bbc5f7	1482	#endif
MACRUM	6:40e873bbc5f7	1483
MACRUM	6:40e873bbc5f7	1484	#if (__FPU_PRESENT == 1)
MACRUM	6:40e873bbc5f7	1485	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
MACRUM	6:40e873bbc5f7	1486	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
MACRUM	6:40e873bbc5f7	1487	#endif
MACRUM	6:40e873bbc5f7	1488
MACRUM	6:40e873bbc5f7	1489	/@} /
MACRUM	6:40e873bbc5f7	1490
MACRUM	6:40e873bbc5f7	1491
MACRUM	6:40e873bbc5f7	1492
MACRUM	6:40e873bbc5f7	1493	/*******************************************************************************
MACRUM	6:40e873bbc5f7	1494	* Hardware Abstraction Layer
MACRUM	6:40e873bbc5f7	1495	Core Function Interface contains:
MACRUM	6:40e873bbc5f7	1496	- Core NVIC Functions
MACRUM	6:40e873bbc5f7	1497	- Core SysTick Functions
MACRUM	6:40e873bbc5f7	1498	- Core Debug Functions
MACRUM	6:40e873bbc5f7	1499	- Core Register Access Functions
MACRUM	6:40e873bbc5f7	1500	******************************************************************************/
MACRUM	6:40e873bbc5f7	1501	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
MACRUM	6:40e873bbc5f7	1502	*/
MACRUM	6:40e873bbc5f7	1503
MACRUM	6:40e873bbc5f7	1504
MACRUM	6:40e873bbc5f7	1505
MACRUM	6:40e873bbc5f7	1506	/* ########################## NVIC functions #################################### */
MACRUM	6:40e873bbc5f7	1507	/** \ingroup CMSIS_Core_FunctionInterface
MACRUM	6:40e873bbc5f7	1508	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
MACRUM	6:40e873bbc5f7	1509	\brief Functions that manage interrupts and exceptions via the NVIC.
MACRUM	6:40e873bbc5f7	1510	@{
MACRUM	6:40e873bbc5f7	1511	*/
MACRUM	6:40e873bbc5f7	1512
MACRUM	6:40e873bbc5f7	1513	#ifdef CMSIS_NVIC_VIRTUAL
MACRUM	6:40e873bbc5f7	1514	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
MACRUM	6:40e873bbc5f7	1515	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
MACRUM	6:40e873bbc5f7	1516	#endif
MACRUM	6:40e873bbc5f7	1517	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
MACRUM	6:40e873bbc5f7	1518	#else
MACRUM	6:40e873bbc5f7	1519	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
MACRUM	6:40e873bbc5f7	1520	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
MACRUM	6:40e873bbc5f7	1521	#define NVIC_EnableIRQ __NVIC_EnableIRQ
MACRUM	6:40e873bbc5f7	1522	#define NVIC_DisableIRQ __NVIC_DisableIRQ
MACRUM	6:40e873bbc5f7	1523	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
MACRUM	6:40e873bbc5f7	1524	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
MACRUM	6:40e873bbc5f7	1525	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
MACRUM	6:40e873bbc5f7	1526	#define NVIC_GetActive __NVIC_GetActive
MACRUM	6:40e873bbc5f7	1527	#define NVIC_SetPriority __NVIC_SetPriority
MACRUM	6:40e873bbc5f7	1528	#define NVIC_GetPriority __NVIC_GetPriority
MACRUM	6:40e873bbc5f7	1529	#define NVIC_SystemReset __NVIC_SystemReset
MACRUM	6:40e873bbc5f7	1530	#endif /* CMSIS_NVIC_VIRTUAL */
MACRUM	6:40e873bbc5f7	1531
MACRUM	6:40e873bbc5f7	1532	#ifdef CMSIS_VECTAB_VIRTUAL
MACRUM	6:40e873bbc5f7	1533	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
MACRUM	6:40e873bbc5f7	1534	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
MACRUM	6:40e873bbc5f7	1535	#endif
MACRUM	6:40e873bbc5f7	1536	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
MACRUM	6:40e873bbc5f7	1537	#else
MACRUM	6:40e873bbc5f7	1538	#define NVIC_SetVector __NVIC_SetVector
MACRUM	6:40e873bbc5f7	1539	#define NVIC_GetVector __NVIC_GetVector
MACRUM	6:40e873bbc5f7	1540	#endif /* CMSIS_VECTAB_VIRTUAL */
MACRUM	6:40e873bbc5f7	1541
MACRUM	6:40e873bbc5f7	1542
MACRUM	6:40e873bbc5f7	1543	/** \brief Set Priority Grouping
MACRUM	6:40e873bbc5f7	1544
MACRUM	6:40e873bbc5f7	1545	The function sets the priority grouping field using the required unlock sequence.
MACRUM	6:40e873bbc5f7	1546	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
MACRUM	6:40e873bbc5f7	1547	Only values from 0..7 are used.
MACRUM	6:40e873bbc5f7	1548	In case of a conflict between priority grouping and available
MACRUM	6:40e873bbc5f7	1549	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
MACRUM	6:40e873bbc5f7	1550
MACRUM	6:40e873bbc5f7	1551	\param [in] PriorityGroup Priority grouping field.
MACRUM	6:40e873bbc5f7	1552	*/
MACRUM	6:40e873bbc5f7	1553	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
MACRUM	6:40e873bbc5f7	1554	{
MACRUM	6:40e873bbc5f7	1555	uint32_t reg_value;
MACRUM	6:40e873bbc5f7	1556	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MACRUM	6:40e873bbc5f7	1557
MACRUM	6:40e873bbc5f7	1558	reg_value = SCB->AIRCR; /* read old register configuration */
MACRUM	6:40e873bbc5f7	1559	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
MACRUM	6:40e873bbc5f7	1560	reg_value = (reg_value \|
MACRUM	6:40e873bbc5f7	1561	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
MACRUM	6:40e873bbc5f7	1562	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
MACRUM	6:40e873bbc5f7	1563	SCB->AIRCR = reg_value;
MACRUM	6:40e873bbc5f7	1564	}
MACRUM	6:40e873bbc5f7	1565
MACRUM	6:40e873bbc5f7	1566
MACRUM	6:40e873bbc5f7	1567	/** \brief Get Priority Grouping
MACRUM	6:40e873bbc5f7	1568
MACRUM	6:40e873bbc5f7	1569	The function reads the priority grouping field from the NVIC Interrupt Controller.
MACRUM	6:40e873bbc5f7	1570
MACRUM	6:40e873bbc5f7	1571	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
MACRUM	6:40e873bbc5f7	1572	*/
MACRUM	6:40e873bbc5f7	1573	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
MACRUM	6:40e873bbc5f7	1574	{
MACRUM	6:40e873bbc5f7	1575	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
MACRUM	6:40e873bbc5f7	1576	}
MACRUM	6:40e873bbc5f7	1577
MACRUM	6:40e873bbc5f7	1578
MACRUM	6:40e873bbc5f7	1579	/** \brief Enable External Interrupt
MACRUM	6:40e873bbc5f7	1580
MACRUM	6:40e873bbc5f7	1581	The function enables a device-specific interrupt in the NVIC interrupt controller.
MACRUM	6:40e873bbc5f7	1582
MACRUM	6:40e873bbc5f7	1583	\param [in] IRQn External interrupt number. Value cannot be negative.
MACRUM	6:40e873bbc5f7	1584	*/
MACRUM	6:40e873bbc5f7	1585	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
MACRUM	6:40e873bbc5f7	1586	{
MACRUM	6:40e873bbc5f7	1587	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MACRUM	6:40e873bbc5f7	1588	}
MACRUM	6:40e873bbc5f7	1589
MACRUM	6:40e873bbc5f7	1590
MACRUM	6:40e873bbc5f7	1591	/** \brief Disable External Interrupt
MACRUM	6:40e873bbc5f7	1592
MACRUM	6:40e873bbc5f7	1593	The function disables a device-specific interrupt in the NVIC interrupt controller.
MACRUM	6:40e873bbc5f7	1594
MACRUM	6:40e873bbc5f7	1595	\param [in] IRQn External interrupt number. Value cannot be negative.
MACRUM	6:40e873bbc5f7	1596	*/
MACRUM	6:40e873bbc5f7	1597	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
MACRUM	6:40e873bbc5f7	1598	{
MACRUM	6:40e873bbc5f7	1599	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MACRUM	6:40e873bbc5f7	1600	__DSB();
MACRUM	6:40e873bbc5f7	1601	__ISB();
MACRUM	6:40e873bbc5f7	1602	}
MACRUM	6:40e873bbc5f7	1603
MACRUM	6:40e873bbc5f7	1604
MACRUM	6:40e873bbc5f7	1605	/** \brief Get Pending Interrupt
MACRUM	6:40e873bbc5f7	1606
MACRUM	6:40e873bbc5f7	1607	The function reads the pending register in the NVIC and returns the pending bit
MACRUM	6:40e873bbc5f7	1608	for the specified interrupt.
MACRUM	6:40e873bbc5f7	1609
MACRUM	6:40e873bbc5f7	1610	\param [in] IRQn Interrupt number.
MACRUM	6:40e873bbc5f7	1611
MACRUM	6:40e873bbc5f7	1612	\return 0 Interrupt status is not pending.
MACRUM	6:40e873bbc5f7	1613	\return 1 Interrupt status is pending.
MACRUM	6:40e873bbc5f7	1614	*/
MACRUM	6:40e873bbc5f7	1615	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
MACRUM	6:40e873bbc5f7	1616	{
MACRUM	6:40e873bbc5f7	1617	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MACRUM	6:40e873bbc5f7	1618	}
MACRUM	6:40e873bbc5f7	1619
MACRUM	6:40e873bbc5f7	1620
MACRUM	6:40e873bbc5f7	1621	/** \brief Set Pending Interrupt
MACRUM	6:40e873bbc5f7	1622
MACRUM	6:40e873bbc5f7	1623	The function sets the pending bit of an external interrupt.
MACRUM	6:40e873bbc5f7	1624
MACRUM	6:40e873bbc5f7	1625	\param [in] IRQn Interrupt number. Value cannot be negative.
MACRUM	6:40e873bbc5f7	1626	*/
MACRUM	6:40e873bbc5f7	1627	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
MACRUM	6:40e873bbc5f7	1628	{
MACRUM	6:40e873bbc5f7	1629	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MACRUM	6:40e873bbc5f7	1630	}
MACRUM	6:40e873bbc5f7	1631
MACRUM	6:40e873bbc5f7	1632
MACRUM	6:40e873bbc5f7	1633	/** \brief Clear Pending Interrupt
MACRUM	6:40e873bbc5f7	1634
MACRUM	6:40e873bbc5f7	1635	The function clears the pending bit of an external interrupt.
MACRUM	6:40e873bbc5f7	1636
MACRUM	6:40e873bbc5f7	1637	\param [in] IRQn External interrupt number. Value cannot be negative.
MACRUM	6:40e873bbc5f7	1638	*/
MACRUM	6:40e873bbc5f7	1639	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
MACRUM	6:40e873bbc5f7	1640	{
MACRUM	6:40e873bbc5f7	1641	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MACRUM	6:40e873bbc5f7	1642	}
MACRUM	6:40e873bbc5f7	1643
MACRUM	6:40e873bbc5f7	1644
MACRUM	6:40e873bbc5f7	1645	/** \brief Get Active Interrupt
MACRUM	6:40e873bbc5f7	1646
MACRUM	6:40e873bbc5f7	1647	The function reads the active register in NVIC and returns the active bit.
MACRUM	6:40e873bbc5f7	1648
MACRUM	6:40e873bbc5f7	1649	\param [in] IRQn Interrupt number.
MACRUM	6:40e873bbc5f7	1650
MACRUM	6:40e873bbc5f7	1651	\return 0 Interrupt status is not active.
MACRUM	6:40e873bbc5f7	1652	\return 1 Interrupt status is active.
MACRUM	6:40e873bbc5f7	1653	*/
MACRUM	6:40e873bbc5f7	1654	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
MACRUM	6:40e873bbc5f7	1655	{
MACRUM	6:40e873bbc5f7	1656	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MACRUM	6:40e873bbc5f7	1657	}
MACRUM	6:40e873bbc5f7	1658
MACRUM	6:40e873bbc5f7	1659
MACRUM	6:40e873bbc5f7	1660	/** \brief Set Interrupt Priority
MACRUM	6:40e873bbc5f7	1661
MACRUM	6:40e873bbc5f7	1662	The function sets the priority of an interrupt.
MACRUM	6:40e873bbc5f7	1663
MACRUM	6:40e873bbc5f7	1664	\note The priority cannot be set for every core interrupt.
MACRUM	6:40e873bbc5f7	1665
MACRUM	6:40e873bbc5f7	1666	\param [in] IRQn Interrupt number.
MACRUM	6:40e873bbc5f7	1667	\param [in] priority Priority to set.
MACRUM	6:40e873bbc5f7	1668	*/
MACRUM	6:40e873bbc5f7	1669	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
MACRUM	6:40e873bbc5f7	1670	{
MACRUM	6:40e873bbc5f7	1671	if((int32_t)IRQn < 0) {
MACRUM	6:40e873bbc5f7	1672	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
MACRUM	6:40e873bbc5f7	1673	}
MACRUM	6:40e873bbc5f7	1674	else {
MACRUM	6:40e873bbc5f7	1675	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
MACRUM	6:40e873bbc5f7	1676	}
MACRUM	6:40e873bbc5f7	1677	}
MACRUM	6:40e873bbc5f7	1678
MACRUM	6:40e873bbc5f7	1679
MACRUM	6:40e873bbc5f7	1680	/** \brief Get Interrupt Priority
MACRUM	6:40e873bbc5f7	1681
MACRUM	6:40e873bbc5f7	1682	The function reads the priority of an interrupt. The interrupt
MACRUM	6:40e873bbc5f7	1683	number can be positive to specify an external (device specific)
MACRUM	6:40e873bbc5f7	1684	interrupt, or negative to specify an internal (core) interrupt.
MACRUM	6:40e873bbc5f7	1685
MACRUM	6:40e873bbc5f7	1686
MACRUM	6:40e873bbc5f7	1687	\param [in] IRQn Interrupt number.
MACRUM	6:40e873bbc5f7	1688	\return Interrupt Priority. Value is aligned automatically to the implemented
MACRUM	6:40e873bbc5f7	1689	priority bits of the microcontroller.
MACRUM	6:40e873bbc5f7	1690	*/
MACRUM	6:40e873bbc5f7	1691	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
MACRUM	6:40e873bbc5f7	1692	{
MACRUM	6:40e873bbc5f7	1693
MACRUM	6:40e873bbc5f7	1694	if((int32_t)IRQn < 0) {
MACRUM	6:40e873bbc5f7	1695	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
MACRUM	6:40e873bbc5f7	1696	}
MACRUM	6:40e873bbc5f7	1697	else {
MACRUM	6:40e873bbc5f7	1698	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
MACRUM	6:40e873bbc5f7	1699	}
MACRUM	6:40e873bbc5f7	1700	}
MACRUM	6:40e873bbc5f7	1701
MACRUM	6:40e873bbc5f7	1702
MACRUM	6:40e873bbc5f7	1703	/** \brief Encode Priority
MACRUM	6:40e873bbc5f7	1704
MACRUM	6:40e873bbc5f7	1705	The function encodes the priority for an interrupt with the given priority group,
MACRUM	6:40e873bbc5f7	1706	preemptive priority value, and subpriority value.
MACRUM	6:40e873bbc5f7	1707	In case of a conflict between priority grouping and available
MACRUM	6:40e873bbc5f7	1708	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
MACRUM	6:40e873bbc5f7	1709
MACRUM	6:40e873bbc5f7	1710	\param [in] PriorityGroup Used priority group.
MACRUM	6:40e873bbc5f7	1711	\param [in] PreemptPriority Preemptive priority value (starting from 0).
MACRUM	6:40e873bbc5f7	1712	\param [in] SubPriority Subpriority value (starting from 0).
MACRUM	6:40e873bbc5f7	1713	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
MACRUM	6:40e873bbc5f7	1714	*/
MACRUM	6:40e873bbc5f7	1715	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
MACRUM	6:40e873bbc5f7	1716	{
MACRUM	6:40e873bbc5f7	1717	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MACRUM	6:40e873bbc5f7	1718	uint32_t PreemptPriorityBits;
MACRUM	6:40e873bbc5f7	1719	uint32_t SubPriorityBits;
MACRUM	6:40e873bbc5f7	1720
MACRUM	6:40e873bbc5f7	1721	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
MACRUM	6:40e873bbc5f7	1722	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
MACRUM	6:40e873bbc5f7	1723
MACRUM	6:40e873bbc5f7	1724	return (
MACRUM	6:40e873bbc5f7	1725	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
MACRUM	6:40e873bbc5f7	1726	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
MACRUM	6:40e873bbc5f7	1727	);
MACRUM	6:40e873bbc5f7	1728	}
MACRUM	6:40e873bbc5f7	1729
MACRUM	6:40e873bbc5f7	1730
MACRUM	6:40e873bbc5f7	1731	/** \brief Decode Priority
MACRUM	6:40e873bbc5f7	1732
MACRUM	6:40e873bbc5f7	1733	The function decodes an interrupt priority value with a given priority group to
MACRUM	6:40e873bbc5f7	1734	preemptive priority value and subpriority value.
MACRUM	6:40e873bbc5f7	1735	In case of a conflict between priority grouping and available
MACRUM	6:40e873bbc5f7	1736	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
MACRUM	6:40e873bbc5f7	1737
MACRUM	6:40e873bbc5f7	1738	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
MACRUM	6:40e873bbc5f7	1739	\param [in] PriorityGroup Used priority group.
MACRUM	6:40e873bbc5f7	1740	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
MACRUM	6:40e873bbc5f7	1741	\param [out] pSubPriority Subpriority value (starting from 0).
MACRUM	6:40e873bbc5f7	1742	*/
MACRUM	6:40e873bbc5f7	1743	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
MACRUM	6:40e873bbc5f7	1744	{
MACRUM	6:40e873bbc5f7	1745	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MACRUM	6:40e873bbc5f7	1746	uint32_t PreemptPriorityBits;
MACRUM	6:40e873bbc5f7	1747	uint32_t SubPriorityBits;
MACRUM	6:40e873bbc5f7	1748
MACRUM	6:40e873bbc5f7	1749	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
MACRUM	6:40e873bbc5f7	1750	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
MACRUM	6:40e873bbc5f7	1751
MACRUM	6:40e873bbc5f7	1752	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
MACRUM	6:40e873bbc5f7	1753	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
MACRUM	6:40e873bbc5f7	1754	}
MACRUM	6:40e873bbc5f7	1755
MACRUM	6:40e873bbc5f7	1756
MACRUM	6:40e873bbc5f7	1757	/** \brief System Reset
MACRUM	6:40e873bbc5f7	1758
MACRUM	6:40e873bbc5f7	1759	The function initiates a system reset request to reset the MCU.
MACRUM	6:40e873bbc5f7	1760	*/
MACRUM	6:40e873bbc5f7	1761	__STATIC_INLINE void __NVIC_SystemReset(void)
MACRUM	6:40e873bbc5f7	1762	{
MACRUM	6:40e873bbc5f7	1763	__DSB(); /* Ensure all outstanding memory accesses included
MACRUM	6:40e873bbc5f7	1764	buffered write are completed before reset */
MACRUM	6:40e873bbc5f7	1765	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
MACRUM	6:40e873bbc5f7	1766	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
MACRUM	6:40e873bbc5f7	1767	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
MACRUM	6:40e873bbc5f7	1768	__DSB(); /* Ensure completion of memory access */
MACRUM	6:40e873bbc5f7	1769	while(1) { __NOP(); } /* wait until reset */
MACRUM	6:40e873bbc5f7	1770	}
MACRUM	6:40e873bbc5f7	1771
MACRUM	6:40e873bbc5f7	1772	/@} end of CMSIS_Core_NVICFunctions /
MACRUM	6:40e873bbc5f7	1773
MACRUM	6:40e873bbc5f7	1774
MACRUM	6:40e873bbc5f7	1775
MACRUM	6:40e873bbc5f7	1776	/* ################################## SysTick function ############################################ */
MACRUM	6:40e873bbc5f7	1777	/** \ingroup CMSIS_Core_FunctionInterface
MACRUM	6:40e873bbc5f7	1778	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
MACRUM	6:40e873bbc5f7	1779	\brief Functions that configure the System.
MACRUM	6:40e873bbc5f7	1780	@{
MACRUM	6:40e873bbc5f7	1781	*/
MACRUM	6:40e873bbc5f7	1782
MACRUM	6:40e873bbc5f7	1783	#if (__Vendor_SysTickConfig == 0)
MACRUM	6:40e873bbc5f7	1784
MACRUM	6:40e873bbc5f7	1785	/** \brief System Tick Configuration
MACRUM	6:40e873bbc5f7	1786
MACRUM	6:40e873bbc5f7	1787	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
MACRUM	6:40e873bbc5f7	1788	Counter is in free running mode to generate periodic interrupts.
MACRUM	6:40e873bbc5f7	1789
MACRUM	6:40e873bbc5f7	1790	\param [in] ticks Number of ticks between two interrupts.
MACRUM	6:40e873bbc5f7	1791
MACRUM	6:40e873bbc5f7	1792	\return 0 Function succeeded.
MACRUM	6:40e873bbc5f7	1793	\return 1 Function failed.
MACRUM	6:40e873bbc5f7	1794
MACRUM	6:40e873bbc5f7	1795	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
MACRUM	6:40e873bbc5f7	1796	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
MACRUM	6:40e873bbc5f7	1797	must contain a vendor-specific implementation of this function.
MACRUM	6:40e873bbc5f7	1798
MACRUM	6:40e873bbc5f7	1799	*/
MACRUM	6:40e873bbc5f7	1800	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
MACRUM	6:40e873bbc5f7	1801	{
MACRUM	6:40e873bbc5f7	1802	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
MACRUM	6:40e873bbc5f7	1803
MACRUM	6:40e873bbc5f7	1804	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
MACRUM	6:40e873bbc5f7	1805	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
MACRUM	6:40e873bbc5f7	1806	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
MACRUM	6:40e873bbc5f7	1807	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
MACRUM	6:40e873bbc5f7	1808	SysTick_CTRL_TICKINT_Msk \|
MACRUM	6:40e873bbc5f7	1809	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
MACRUM	6:40e873bbc5f7	1810	return (0UL); /* Function successful */
MACRUM	6:40e873bbc5f7	1811	}
MACRUM	6:40e873bbc5f7	1812
MACRUM	6:40e873bbc5f7	1813	#endif
MACRUM	6:40e873bbc5f7	1814
MACRUM	6:40e873bbc5f7	1815	/@} end of CMSIS_Core_SysTickFunctions /
MACRUM	6:40e873bbc5f7	1816
MACRUM	6:40e873bbc5f7	1817
MACRUM	6:40e873bbc5f7	1818
MACRUM	6:40e873bbc5f7	1819	/* ##################################### Debug In/Output function ########################################### */
MACRUM	6:40e873bbc5f7	1820	/** \ingroup CMSIS_Core_FunctionInterface
MACRUM	6:40e873bbc5f7	1821	\defgroup CMSIS_core_DebugFunctions ITM Functions
MACRUM	6:40e873bbc5f7	1822	\brief Functions that access the ITM debug interface.
MACRUM	6:40e873bbc5f7	1823	@{
MACRUM	6:40e873bbc5f7	1824	*/
MACRUM	6:40e873bbc5f7	1825
MACRUM	6:40e873bbc5f7	1826	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
MACRUM	6:40e873bbc5f7	1827	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
MACRUM	6:40e873bbc5f7	1828
MACRUM	6:40e873bbc5f7	1829
MACRUM	6:40e873bbc5f7	1830	/** \brief ITM Send Character
MACRUM	6:40e873bbc5f7	1831
MACRUM	6:40e873bbc5f7	1832	The function transmits a character via the ITM channel 0, and
MACRUM	6:40e873bbc5f7	1833	\li Just returns when no debugger is connected that has booked the output.
MACRUM	6:40e873bbc5f7	1834	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
MACRUM	6:40e873bbc5f7	1835
MACRUM	6:40e873bbc5f7	1836	\param [in] ch Character to transmit.
MACRUM	6:40e873bbc5f7	1837
MACRUM	6:40e873bbc5f7	1838	\returns Character to transmit.
MACRUM	6:40e873bbc5f7	1839	*/
MACRUM	6:40e873bbc5f7	1840	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
MACRUM	6:40e873bbc5f7	1841	{
MACRUM	6:40e873bbc5f7	1842	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
MACRUM	6:40e873bbc5f7	1843	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
MACRUM	6:40e873bbc5f7	1844	{
MACRUM	6:40e873bbc5f7	1845	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
MACRUM	6:40e873bbc5f7	1846	ITM->PORT[0].u8 = (uint8_t)ch;
MACRUM	6:40e873bbc5f7	1847	}
MACRUM	6:40e873bbc5f7	1848	return (ch);
MACRUM	6:40e873bbc5f7	1849	}
MACRUM	6:40e873bbc5f7	1850
MACRUM	6:40e873bbc5f7	1851
MACRUM	6:40e873bbc5f7	1852	/** \brief ITM Receive Character
MACRUM	6:40e873bbc5f7	1853
MACRUM	6:40e873bbc5f7	1854	The function inputs a character via the external variable \ref ITM_RxBuffer.
MACRUM	6:40e873bbc5f7	1855
MACRUM	6:40e873bbc5f7	1856	\return Received character.
MACRUM	6:40e873bbc5f7	1857	\return -1 No character pending.
MACRUM	6:40e873bbc5f7	1858	*/
MACRUM	6:40e873bbc5f7	1859	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
MACRUM	6:40e873bbc5f7	1860	int32_t ch = -1; /* no character available */
MACRUM	6:40e873bbc5f7	1861
MACRUM	6:40e873bbc5f7	1862	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
MACRUM	6:40e873bbc5f7	1863	ch = ITM_RxBuffer;
MACRUM	6:40e873bbc5f7	1864	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
MACRUM	6:40e873bbc5f7	1865	}
MACRUM	6:40e873bbc5f7	1866
MACRUM	6:40e873bbc5f7	1867	return (ch);
MACRUM	6:40e873bbc5f7	1868	}
MACRUM	6:40e873bbc5f7	1869
MACRUM	6:40e873bbc5f7	1870
MACRUM	6:40e873bbc5f7	1871	/** \brief ITM Check Character
MACRUM	6:40e873bbc5f7	1872
MACRUM	6:40e873bbc5f7	1873	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
MACRUM	6:40e873bbc5f7	1874
MACRUM	6:40e873bbc5f7	1875	\return 0 No character available.
MACRUM	6:40e873bbc5f7	1876	\return 1 Character available.
MACRUM	6:40e873bbc5f7	1877	*/
MACRUM	6:40e873bbc5f7	1878	__STATIC_INLINE int32_t ITM_CheckChar (void) {
MACRUM	6:40e873bbc5f7	1879
MACRUM	6:40e873bbc5f7	1880	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
MACRUM	6:40e873bbc5f7	1881	return (0); /* no character available */
MACRUM	6:40e873bbc5f7	1882	} else {
MACRUM	6:40e873bbc5f7	1883	return (1); /* character available */
MACRUM	6:40e873bbc5f7	1884	}
MACRUM	6:40e873bbc5f7	1885	}
MACRUM	6:40e873bbc5f7	1886
MACRUM	6:40e873bbc5f7	1887	/@} end of CMSIS_core_DebugFunctions /
MACRUM	6:40e873bbc5f7	1888
MACRUM	6:40e873bbc5f7	1889
MACRUM	6:40e873bbc5f7	1890
MACRUM	6:40e873bbc5f7	1891
MACRUM	6:40e873bbc5f7	1892	#ifdef __cplusplus
MACRUM	6:40e873bbc5f7	1893	}
MACRUM	6:40e873bbc5f7	1894	#endif
MACRUM	6:40e873bbc5f7	1895
MACRUM	6:40e873bbc5f7	1896	#endif /* __CORE_CM4_H_DEPENDANT */
MACRUM	6:40e873bbc5f7	1897
MACRUM	6:40e873bbc5f7	1898	#endif /* __CMSIS_GENERIC */

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Type:	Program
Mbed OS support:	Mbed OS
Created:	10 Nov 2014
Imports:	18
Forks:	0
Commits:	12
Dependents:	0
Dependencies:	0
Followers:	2

The code in this repository is Apache licensed.

mbed/TARGET_LPC1114/core_cm4.h@6:40e873bbc5f7, 2017-03-16 (annotated)

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