Toyomasa Watarai / Mbed OS armcc_info

Describes predefine macros for mbed online compiler (armcc)

mbed/TARGET_LPC1114/core_caFunc.h@6:40e873bbc5f7, 2017-03-16 (annotated)

Committer:
MACRUM
Date:
Thu Mar 16 21:58:09 2017 +0900
Revision:
6:40e873bbc5f7
Add licence header info

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MACRUM 6:40e873bbc5f7 1 /**************************************************************************//**
MACRUM 6:40e873bbc5f7 2 * @file core_caFunc.h
MACRUM 6:40e873bbc5f7 3 * @brief CMSIS Cortex-A Core Function Access Header File
MACRUM 6:40e873bbc5f7 4 * @version V3.10
MACRUM 6:40e873bbc5f7 5 * @date 30 Oct 2013
MACRUM 6:40e873bbc5f7 6 *
MACRUM 6:40e873bbc5f7 7 * @note
MACRUM 6:40e873bbc5f7 8 *
MACRUM 6:40e873bbc5f7 9 ******************************************************************************/
MACRUM 6:40e873bbc5f7 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
MACRUM 6:40e873bbc5f7 11
MACRUM 6:40e873bbc5f7 12 All rights reserved.
MACRUM 6:40e873bbc5f7 13 Redistribution and use in source and binary forms, with or without
MACRUM 6:40e873bbc5f7 14 modification, are permitted provided that the following conditions are met:
MACRUM 6:40e873bbc5f7 15 - Redistributions of source code must retain the above copyright
MACRUM 6:40e873bbc5f7 16 notice, this list of conditions and the following disclaimer.
MACRUM 6:40e873bbc5f7 17 - Redistributions in binary form must reproduce the above copyright
MACRUM 6:40e873bbc5f7 18 notice, this list of conditions and the following disclaimer in the
MACRUM 6:40e873bbc5f7 19 documentation and/or other materials provided with the distribution.
MACRUM 6:40e873bbc5f7 20 - Neither the name of ARM nor the names of its contributors may be used
MACRUM 6:40e873bbc5f7 21 to endorse or promote products derived from this software without
MACRUM 6:40e873bbc5f7 22 specific prior written permission.
MACRUM 6:40e873bbc5f7 23 *
MACRUM 6:40e873bbc5f7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MACRUM 6:40e873bbc5f7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MACRUM 6:40e873bbc5f7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MACRUM 6:40e873bbc5f7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MACRUM 6:40e873bbc5f7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MACRUM 6:40e873bbc5f7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MACRUM 6:40e873bbc5f7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MACRUM 6:40e873bbc5f7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MACRUM 6:40e873bbc5f7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MACRUM 6:40e873bbc5f7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MACRUM 6:40e873bbc5f7 34 POSSIBILITY OF SUCH DAMAGE.
MACRUM 6:40e873bbc5f7 35 ---------------------------------------------------------------------------*/
MACRUM 6:40e873bbc5f7 36
MACRUM 6:40e873bbc5f7 37
MACRUM 6:40e873bbc5f7 38 #ifndef __CORE_CAFUNC_H__
MACRUM 6:40e873bbc5f7 39 #define __CORE_CAFUNC_H__
MACRUM 6:40e873bbc5f7 40
MACRUM 6:40e873bbc5f7 41
MACRUM 6:40e873bbc5f7 42 /* ########################### Core Function Access ########################### */
MACRUM 6:40e873bbc5f7 43 /** \ingroup CMSIS_Core_FunctionInterface
MACRUM 6:40e873bbc5f7 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
MACRUM 6:40e873bbc5f7 45 @{
MACRUM 6:40e873bbc5f7 46 */
MACRUM 6:40e873bbc5f7 47
MACRUM 6:40e873bbc5f7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MACRUM 6:40e873bbc5f7 49 /* ARM armcc specific functions */
MACRUM 6:40e873bbc5f7 50
MACRUM 6:40e873bbc5f7 51 #if (__ARMCC_VERSION < 400677)
MACRUM 6:40e873bbc5f7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
MACRUM 6:40e873bbc5f7 53 #endif
MACRUM 6:40e873bbc5f7 54
MACRUM 6:40e873bbc5f7 55 #define MODE_USR 0x10
MACRUM 6:40e873bbc5f7 56 #define MODE_FIQ 0x11
MACRUM 6:40e873bbc5f7 57 #define MODE_IRQ 0x12
MACRUM 6:40e873bbc5f7 58 #define MODE_SVC 0x13
MACRUM 6:40e873bbc5f7 59 #define MODE_MON 0x16
MACRUM 6:40e873bbc5f7 60 #define MODE_ABT 0x17
MACRUM 6:40e873bbc5f7 61 #define MODE_HYP 0x1A
MACRUM 6:40e873bbc5f7 62 #define MODE_UND 0x1B
MACRUM 6:40e873bbc5f7 63 #define MODE_SYS 0x1F
MACRUM 6:40e873bbc5f7 64
MACRUM 6:40e873bbc5f7 65 /** \brief Get APSR Register
MACRUM 6:40e873bbc5f7 66
MACRUM 6:40e873bbc5f7 67 This function returns the content of the APSR Register.
MACRUM 6:40e873bbc5f7 68
MACRUM 6:40e873bbc5f7 69 \return APSR Register value
MACRUM 6:40e873bbc5f7 70 */
MACRUM 6:40e873bbc5f7 71 __STATIC_INLINE uint32_t __get_APSR(void)
MACRUM 6:40e873bbc5f7 72 {
MACRUM 6:40e873bbc5f7 73 register uint32_t __regAPSR __ASM("apsr");
MACRUM 6:40e873bbc5f7 74 return(__regAPSR);
MACRUM 6:40e873bbc5f7 75 }
MACRUM 6:40e873bbc5f7 76
MACRUM 6:40e873bbc5f7 77
MACRUM 6:40e873bbc5f7 78 /** \brief Get CPSR Register
MACRUM 6:40e873bbc5f7 79
MACRUM 6:40e873bbc5f7 80 This function returns the content of the CPSR Register.
MACRUM 6:40e873bbc5f7 81
MACRUM 6:40e873bbc5f7 82 \return CPSR Register value
MACRUM 6:40e873bbc5f7 83 */
MACRUM 6:40e873bbc5f7 84 __STATIC_INLINE uint32_t __get_CPSR(void)
MACRUM 6:40e873bbc5f7 85 {
MACRUM 6:40e873bbc5f7 86 register uint32_t __regCPSR __ASM("cpsr");
MACRUM 6:40e873bbc5f7 87 return(__regCPSR);
MACRUM 6:40e873bbc5f7 88 }
MACRUM 6:40e873bbc5f7 89
MACRUM 6:40e873bbc5f7 90 /** \brief Set Stack Pointer
MACRUM 6:40e873bbc5f7 91
MACRUM 6:40e873bbc5f7 92 This function assigns the given value to the current stack pointer.
MACRUM 6:40e873bbc5f7 93
MACRUM 6:40e873bbc5f7 94 \param [in] topOfStack Stack Pointer value to set
MACRUM 6:40e873bbc5f7 95 */
MACRUM 6:40e873bbc5f7 96 register uint32_t __regSP __ASM("sp");
MACRUM 6:40e873bbc5f7 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
MACRUM 6:40e873bbc5f7 98 {
MACRUM 6:40e873bbc5f7 99 __regSP = topOfStack;
MACRUM 6:40e873bbc5f7 100 }
MACRUM 6:40e873bbc5f7 101
MACRUM 6:40e873bbc5f7 102
MACRUM 6:40e873bbc5f7 103 /** \brief Get link register
MACRUM 6:40e873bbc5f7 104
MACRUM 6:40e873bbc5f7 105 This function returns the value of the link register
MACRUM 6:40e873bbc5f7 106
MACRUM 6:40e873bbc5f7 107 \return Value of link register
MACRUM 6:40e873bbc5f7 108 */
MACRUM 6:40e873bbc5f7 109 register uint32_t __reglr __ASM("lr");
MACRUM 6:40e873bbc5f7 110 __STATIC_INLINE uint32_t __get_LR(void)
MACRUM 6:40e873bbc5f7 111 {
MACRUM 6:40e873bbc5f7 112 return(__reglr);
MACRUM 6:40e873bbc5f7 113 }
MACRUM 6:40e873bbc5f7 114
MACRUM 6:40e873bbc5f7 115 /** \brief Set link register
MACRUM 6:40e873bbc5f7 116
MACRUM 6:40e873bbc5f7 117 This function sets the value of the link register
MACRUM 6:40e873bbc5f7 118
MACRUM 6:40e873bbc5f7 119 \param [in] lr LR value to set
MACRUM 6:40e873bbc5f7 120 */
MACRUM 6:40e873bbc5f7 121 __STATIC_INLINE void __set_LR(uint32_t lr)
MACRUM 6:40e873bbc5f7 122 {
MACRUM 6:40e873bbc5f7 123 __reglr = lr;
MACRUM 6:40e873bbc5f7 124 }
MACRUM 6:40e873bbc5f7 125
MACRUM 6:40e873bbc5f7 126 /** \brief Set Process Stack Pointer
MACRUM 6:40e873bbc5f7 127
MACRUM 6:40e873bbc5f7 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
MACRUM 6:40e873bbc5f7 129
MACRUM 6:40e873bbc5f7 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
MACRUM 6:40e873bbc5f7 131 */
MACRUM 6:40e873bbc5f7 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
MACRUM 6:40e873bbc5f7 133 {
MACRUM 6:40e873bbc5f7 134 ARM
MACRUM 6:40e873bbc5f7 135 PRESERVE8
MACRUM 6:40e873bbc5f7 136
MACRUM 6:40e873bbc5f7 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
MACRUM 6:40e873bbc5f7 138 MRS R1, CPSR
MACRUM 6:40e873bbc5f7 139 CPS #MODE_SYS ;no effect in USR mode
MACRUM 6:40e873bbc5f7 140 MOV SP, R0
MACRUM 6:40e873bbc5f7 141 MSR CPSR_c, R1 ;no effect in USR mode
MACRUM 6:40e873bbc5f7 142 ISB
MACRUM 6:40e873bbc5f7 143 BX LR
MACRUM 6:40e873bbc5f7 144
MACRUM 6:40e873bbc5f7 145 }
MACRUM 6:40e873bbc5f7 146
MACRUM 6:40e873bbc5f7 147 /** \brief Set User Mode
MACRUM 6:40e873bbc5f7 148
MACRUM 6:40e873bbc5f7 149 This function changes the processor state to User Mode
MACRUM 6:40e873bbc5f7 150 */
MACRUM 6:40e873bbc5f7 151 __STATIC_ASM void __set_CPS_USR(void)
MACRUM 6:40e873bbc5f7 152 {
MACRUM 6:40e873bbc5f7 153 ARM
MACRUM 6:40e873bbc5f7 154
MACRUM 6:40e873bbc5f7 155 CPS #MODE_USR
MACRUM 6:40e873bbc5f7 156 BX LR
MACRUM 6:40e873bbc5f7 157 }
MACRUM 6:40e873bbc5f7 158
MACRUM 6:40e873bbc5f7 159
MACRUM 6:40e873bbc5f7 160 /** \brief Enable FIQ
MACRUM 6:40e873bbc5f7 161
MACRUM 6:40e873bbc5f7 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MACRUM 6:40e873bbc5f7 163 Can only be executed in Privileged modes.
MACRUM 6:40e873bbc5f7 164 */
MACRUM 6:40e873bbc5f7 165 #define __enable_fault_irq __enable_fiq
MACRUM 6:40e873bbc5f7 166
MACRUM 6:40e873bbc5f7 167
MACRUM 6:40e873bbc5f7 168 /** \brief Disable FIQ
MACRUM 6:40e873bbc5f7 169
MACRUM 6:40e873bbc5f7 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MACRUM 6:40e873bbc5f7 171 Can only be executed in Privileged modes.
MACRUM 6:40e873bbc5f7 172 */
MACRUM 6:40e873bbc5f7 173 #define __disable_fault_irq __disable_fiq
MACRUM 6:40e873bbc5f7 174
MACRUM 6:40e873bbc5f7 175
MACRUM 6:40e873bbc5f7 176 /** \brief Get FPSCR
MACRUM 6:40e873bbc5f7 177
MACRUM 6:40e873bbc5f7 178 This function returns the current value of the Floating Point Status/Control register.
MACRUM 6:40e873bbc5f7 179
MACRUM 6:40e873bbc5f7 180 \return Floating Point Status/Control register value
MACRUM 6:40e873bbc5f7 181 */
MACRUM 6:40e873bbc5f7 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
MACRUM 6:40e873bbc5f7 183 {
MACRUM 6:40e873bbc5f7 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MACRUM 6:40e873bbc5f7 185 register uint32_t __regfpscr __ASM("fpscr");
MACRUM 6:40e873bbc5f7 186 return(__regfpscr);
MACRUM 6:40e873bbc5f7 187 #else
MACRUM 6:40e873bbc5f7 188 return(0);
MACRUM 6:40e873bbc5f7 189 #endif
MACRUM 6:40e873bbc5f7 190 }
MACRUM 6:40e873bbc5f7 191
MACRUM 6:40e873bbc5f7 192
MACRUM 6:40e873bbc5f7 193 /** \brief Set FPSCR
MACRUM 6:40e873bbc5f7 194
MACRUM 6:40e873bbc5f7 195 This function assigns the given value to the Floating Point Status/Control register.
MACRUM 6:40e873bbc5f7 196
MACRUM 6:40e873bbc5f7 197 \param [in] fpscr Floating Point Status/Control value to set
MACRUM 6:40e873bbc5f7 198 */
MACRUM 6:40e873bbc5f7 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MACRUM 6:40e873bbc5f7 200 {
MACRUM 6:40e873bbc5f7 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MACRUM 6:40e873bbc5f7 202 register uint32_t __regfpscr __ASM("fpscr");
MACRUM 6:40e873bbc5f7 203 __regfpscr = (fpscr);
MACRUM 6:40e873bbc5f7 204 #endif
MACRUM 6:40e873bbc5f7 205 }
MACRUM 6:40e873bbc5f7 206
MACRUM 6:40e873bbc5f7 207 /** \brief Get FPEXC
MACRUM 6:40e873bbc5f7 208
MACRUM 6:40e873bbc5f7 209 This function returns the current value of the Floating Point Exception Control register.
MACRUM 6:40e873bbc5f7 210
MACRUM 6:40e873bbc5f7 211 \return Floating Point Exception Control register value
MACRUM 6:40e873bbc5f7 212 */
MACRUM 6:40e873bbc5f7 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
MACRUM 6:40e873bbc5f7 214 {
MACRUM 6:40e873bbc5f7 215 #if (__FPU_PRESENT == 1)
MACRUM 6:40e873bbc5f7 216 register uint32_t __regfpexc __ASM("fpexc");
MACRUM 6:40e873bbc5f7 217 return(__regfpexc);
MACRUM 6:40e873bbc5f7 218 #else
MACRUM 6:40e873bbc5f7 219 return(0);
MACRUM 6:40e873bbc5f7 220 #endif
MACRUM 6:40e873bbc5f7 221 }
MACRUM 6:40e873bbc5f7 222
MACRUM 6:40e873bbc5f7 223
MACRUM 6:40e873bbc5f7 224 /** \brief Set FPEXC
MACRUM 6:40e873bbc5f7 225
MACRUM 6:40e873bbc5f7 226 This function assigns the given value to the Floating Point Exception Control register.
MACRUM 6:40e873bbc5f7 227
MACRUM 6:40e873bbc5f7 228 \param [in] fpscr Floating Point Exception Control value to set
MACRUM 6:40e873bbc5f7 229 */
MACRUM 6:40e873bbc5f7 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
MACRUM 6:40e873bbc5f7 231 {
MACRUM 6:40e873bbc5f7 232 #if (__FPU_PRESENT == 1)
MACRUM 6:40e873bbc5f7 233 register uint32_t __regfpexc __ASM("fpexc");
MACRUM 6:40e873bbc5f7 234 __regfpexc = (fpexc);
MACRUM 6:40e873bbc5f7 235 #endif
MACRUM 6:40e873bbc5f7 236 }
MACRUM 6:40e873bbc5f7 237
MACRUM 6:40e873bbc5f7 238 /** \brief Get CPACR
MACRUM 6:40e873bbc5f7 239
MACRUM 6:40e873bbc5f7 240 This function returns the current value of the Coprocessor Access Control register.
MACRUM 6:40e873bbc5f7 241
MACRUM 6:40e873bbc5f7 242 \return Coprocessor Access Control register value
MACRUM 6:40e873bbc5f7 243 */
MACRUM 6:40e873bbc5f7 244 __STATIC_INLINE uint32_t __get_CPACR(void)
MACRUM 6:40e873bbc5f7 245 {
MACRUM 6:40e873bbc5f7 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
MACRUM 6:40e873bbc5f7 247 return __regCPACR;
MACRUM 6:40e873bbc5f7 248 }
MACRUM 6:40e873bbc5f7 249
MACRUM 6:40e873bbc5f7 250 /** \brief Set CPACR
MACRUM 6:40e873bbc5f7 251
MACRUM 6:40e873bbc5f7 252 This function assigns the given value to the Coprocessor Access Control register.
MACRUM 6:40e873bbc5f7 253
MACRUM 6:40e873bbc5f7 254 \param [in] cpacr Coprocessor Acccess Control value to set
MACRUM 6:40e873bbc5f7 255 */
MACRUM 6:40e873bbc5f7 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
MACRUM 6:40e873bbc5f7 257 {
MACRUM 6:40e873bbc5f7 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
MACRUM 6:40e873bbc5f7 259 __regCPACR = cpacr;
MACRUM 6:40e873bbc5f7 260 __ISB();
MACRUM 6:40e873bbc5f7 261 }
MACRUM 6:40e873bbc5f7 262
MACRUM 6:40e873bbc5f7 263 /** \brief Get CBAR
MACRUM 6:40e873bbc5f7 264
MACRUM 6:40e873bbc5f7 265 This function returns the value of the Configuration Base Address register.
MACRUM 6:40e873bbc5f7 266
MACRUM 6:40e873bbc5f7 267 \return Configuration Base Address register value
MACRUM 6:40e873bbc5f7 268 */
MACRUM 6:40e873bbc5f7 269 __STATIC_INLINE uint32_t __get_CBAR() {
MACRUM 6:40e873bbc5f7 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
MACRUM 6:40e873bbc5f7 271 return(__regCBAR);
MACRUM 6:40e873bbc5f7 272 }
MACRUM 6:40e873bbc5f7 273
MACRUM 6:40e873bbc5f7 274 /** \brief Get TTBR0
MACRUM 6:40e873bbc5f7 275
MACRUM 6:40e873bbc5f7 276 This function returns the value of the Translation Table Base Register 0.
MACRUM 6:40e873bbc5f7 277
MACRUM 6:40e873bbc5f7 278 \return Translation Table Base Register 0 value
MACRUM 6:40e873bbc5f7 279 */
MACRUM 6:40e873bbc5f7 280 __STATIC_INLINE uint32_t __get_TTBR0() {
MACRUM 6:40e873bbc5f7 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
MACRUM 6:40e873bbc5f7 282 return(__regTTBR0);
MACRUM 6:40e873bbc5f7 283 }
MACRUM 6:40e873bbc5f7 284
MACRUM 6:40e873bbc5f7 285 /** \brief Set TTBR0
MACRUM 6:40e873bbc5f7 286
MACRUM 6:40e873bbc5f7 287 This function assigns the given value to the Translation Table Base Register 0.
MACRUM 6:40e873bbc5f7 288
MACRUM 6:40e873bbc5f7 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
MACRUM 6:40e873bbc5f7 290 */
MACRUM 6:40e873bbc5f7 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
MACRUM 6:40e873bbc5f7 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
MACRUM 6:40e873bbc5f7 293 __regTTBR0 = ttbr0;
MACRUM 6:40e873bbc5f7 294 __ISB();
MACRUM 6:40e873bbc5f7 295 }
MACRUM 6:40e873bbc5f7 296
MACRUM 6:40e873bbc5f7 297 /** \brief Get DACR
MACRUM 6:40e873bbc5f7 298
MACRUM 6:40e873bbc5f7 299 This function returns the value of the Domain Access Control Register.
MACRUM 6:40e873bbc5f7 300
MACRUM 6:40e873bbc5f7 301 \return Domain Access Control Register value
MACRUM 6:40e873bbc5f7 302 */
MACRUM 6:40e873bbc5f7 303 __STATIC_INLINE uint32_t __get_DACR() {
MACRUM 6:40e873bbc5f7 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
MACRUM 6:40e873bbc5f7 305 return(__regDACR);
MACRUM 6:40e873bbc5f7 306 }
MACRUM 6:40e873bbc5f7 307
MACRUM 6:40e873bbc5f7 308 /** \brief Set DACR
MACRUM 6:40e873bbc5f7 309
MACRUM 6:40e873bbc5f7 310 This function assigns the given value to the Domain Access Control Register.
MACRUM 6:40e873bbc5f7 311
MACRUM 6:40e873bbc5f7 312 \param [in] dacr Domain Access Control Register value to set
MACRUM 6:40e873bbc5f7 313 */
MACRUM 6:40e873bbc5f7 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
MACRUM 6:40e873bbc5f7 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
MACRUM 6:40e873bbc5f7 316 __regDACR = dacr;
MACRUM 6:40e873bbc5f7 317 __ISB();
MACRUM 6:40e873bbc5f7 318 }
MACRUM 6:40e873bbc5f7 319
MACRUM 6:40e873bbc5f7 320 /******************************** Cache and BTAC enable ****************************************************/
MACRUM 6:40e873bbc5f7 321
MACRUM 6:40e873bbc5f7 322 /** \brief Set SCTLR
MACRUM 6:40e873bbc5f7 323
MACRUM 6:40e873bbc5f7 324 This function assigns the given value to the System Control Register.
MACRUM 6:40e873bbc5f7 325
MACRUM 6:40e873bbc5f7 326 \param [in] sctlr System Control Register value to set
MACRUM 6:40e873bbc5f7 327 */
MACRUM 6:40e873bbc5f7 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
MACRUM 6:40e873bbc5f7 329 {
MACRUM 6:40e873bbc5f7 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
MACRUM 6:40e873bbc5f7 331 __regSCTLR = sctlr;
MACRUM 6:40e873bbc5f7 332 }
MACRUM 6:40e873bbc5f7 333
MACRUM 6:40e873bbc5f7 334 /** \brief Get SCTLR
MACRUM 6:40e873bbc5f7 335
MACRUM 6:40e873bbc5f7 336 This function returns the value of the System Control Register.
MACRUM 6:40e873bbc5f7 337
MACRUM 6:40e873bbc5f7 338 \return System Control Register value
MACRUM 6:40e873bbc5f7 339 */
MACRUM 6:40e873bbc5f7 340 __STATIC_INLINE uint32_t __get_SCTLR() {
MACRUM 6:40e873bbc5f7 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
MACRUM 6:40e873bbc5f7 342 return(__regSCTLR);
MACRUM 6:40e873bbc5f7 343 }
MACRUM 6:40e873bbc5f7 344
MACRUM 6:40e873bbc5f7 345 /** \brief Enable Caches
MACRUM 6:40e873bbc5f7 346
MACRUM 6:40e873bbc5f7 347 Enable Caches
MACRUM 6:40e873bbc5f7 348 */
MACRUM 6:40e873bbc5f7 349 __STATIC_INLINE void __enable_caches(void) {
MACRUM 6:40e873bbc5f7 350 // Set I bit 12 to enable I Cache
MACRUM 6:40e873bbc5f7 351 // Set C bit 2 to enable D Cache
MACRUM 6:40e873bbc5f7 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
MACRUM 6:40e873bbc5f7 353 }
MACRUM 6:40e873bbc5f7 354
MACRUM 6:40e873bbc5f7 355 /** \brief Disable Caches
MACRUM 6:40e873bbc5f7 356
MACRUM 6:40e873bbc5f7 357 Disable Caches
MACRUM 6:40e873bbc5f7 358 */
MACRUM 6:40e873bbc5f7 359 __STATIC_INLINE void __disable_caches(void) {
MACRUM 6:40e873bbc5f7 360 // Clear I bit 12 to disable I Cache
MACRUM 6:40e873bbc5f7 361 // Clear C bit 2 to disable D Cache
MACRUM 6:40e873bbc5f7 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
MACRUM 6:40e873bbc5f7 363 __ISB();
MACRUM 6:40e873bbc5f7 364 }
MACRUM 6:40e873bbc5f7 365
MACRUM 6:40e873bbc5f7 366 /** \brief Enable BTAC
MACRUM 6:40e873bbc5f7 367
MACRUM 6:40e873bbc5f7 368 Enable BTAC
MACRUM 6:40e873bbc5f7 369 */
MACRUM 6:40e873bbc5f7 370 __STATIC_INLINE void __enable_btac(void) {
MACRUM 6:40e873bbc5f7 371 // Set Z bit 11 to enable branch prediction
MACRUM 6:40e873bbc5f7 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
MACRUM 6:40e873bbc5f7 373 __ISB();
MACRUM 6:40e873bbc5f7 374 }
MACRUM 6:40e873bbc5f7 375
MACRUM 6:40e873bbc5f7 376 /** \brief Disable BTAC
MACRUM 6:40e873bbc5f7 377
MACRUM 6:40e873bbc5f7 378 Disable BTAC
MACRUM 6:40e873bbc5f7 379 */
MACRUM 6:40e873bbc5f7 380 __STATIC_INLINE void __disable_btac(void) {
MACRUM 6:40e873bbc5f7 381 // Clear Z bit 11 to disable branch prediction
MACRUM 6:40e873bbc5f7 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
MACRUM 6:40e873bbc5f7 383 }
MACRUM 6:40e873bbc5f7 384
MACRUM 6:40e873bbc5f7 385
MACRUM 6:40e873bbc5f7 386 /** \brief Enable MMU
MACRUM 6:40e873bbc5f7 387
MACRUM 6:40e873bbc5f7 388 Enable MMU
MACRUM 6:40e873bbc5f7 389 */
MACRUM 6:40e873bbc5f7 390 __STATIC_INLINE void __enable_mmu(void) {
MACRUM 6:40e873bbc5f7 391 // Set M bit 0 to enable the MMU
MACRUM 6:40e873bbc5f7 392 // Set AFE bit to enable simplified access permissions model
MACRUM 6:40e873bbc5f7 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
MACRUM 6:40e873bbc5f7 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
MACRUM 6:40e873bbc5f7 395 __ISB();
MACRUM 6:40e873bbc5f7 396 }
MACRUM 6:40e873bbc5f7 397
MACRUM 6:40e873bbc5f7 398 /** \brief Disable MMU
MACRUM 6:40e873bbc5f7 399
MACRUM 6:40e873bbc5f7 400 Disable MMU
MACRUM 6:40e873bbc5f7 401 */
MACRUM 6:40e873bbc5f7 402 __STATIC_INLINE void __disable_mmu(void) {
MACRUM 6:40e873bbc5f7 403 // Clear M bit 0 to disable the MMU
MACRUM 6:40e873bbc5f7 404 __set_SCTLR( __get_SCTLR() & ~1);
MACRUM 6:40e873bbc5f7 405 __ISB();
MACRUM 6:40e873bbc5f7 406 }
MACRUM 6:40e873bbc5f7 407
MACRUM 6:40e873bbc5f7 408 /******************************** TLB maintenance operations ************************************************/
MACRUM 6:40e873bbc5f7 409 /** \brief Invalidate the whole tlb
MACRUM 6:40e873bbc5f7 410
MACRUM 6:40e873bbc5f7 411 TLBIALL. Invalidate the whole tlb
MACRUM 6:40e873bbc5f7 412 */
MACRUM 6:40e873bbc5f7 413
MACRUM 6:40e873bbc5f7 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
MACRUM 6:40e873bbc5f7 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
MACRUM 6:40e873bbc5f7 416 __TLBIALL = 0;
MACRUM 6:40e873bbc5f7 417 __DSB();
MACRUM 6:40e873bbc5f7 418 __ISB();
MACRUM 6:40e873bbc5f7 419 }
MACRUM 6:40e873bbc5f7 420
MACRUM 6:40e873bbc5f7 421 /******************************** BTB maintenance operations ************************************************/
MACRUM 6:40e873bbc5f7 422 /** \brief Invalidate entire branch predictor array
MACRUM 6:40e873bbc5f7 423
MACRUM 6:40e873bbc5f7 424 BPIALL. Branch Predictor Invalidate All.
MACRUM 6:40e873bbc5f7 425 */
MACRUM 6:40e873bbc5f7 426
MACRUM 6:40e873bbc5f7 427 __STATIC_INLINE void __v7_inv_btac(void) {
MACRUM 6:40e873bbc5f7 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
MACRUM 6:40e873bbc5f7 429 __BPIALL = 0;
MACRUM 6:40e873bbc5f7 430 __DSB(); //ensure completion of the invalidation
MACRUM 6:40e873bbc5f7 431 __ISB(); //ensure instruction fetch path sees new state
MACRUM 6:40e873bbc5f7 432 }
MACRUM 6:40e873bbc5f7 433
MACRUM 6:40e873bbc5f7 434
MACRUM 6:40e873bbc5f7 435 /******************************** L1 cache operations ******************************************************/
MACRUM 6:40e873bbc5f7 436
MACRUM 6:40e873bbc5f7 437 /** \brief Invalidate the whole I$
MACRUM 6:40e873bbc5f7 438
MACRUM 6:40e873bbc5f7 439 ICIALLU. Instruction Cache Invalidate All to PoU
MACRUM 6:40e873bbc5f7 440 */
MACRUM 6:40e873bbc5f7 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
MACRUM 6:40e873bbc5f7 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
MACRUM 6:40e873bbc5f7 443 __ICIALLU = 0;
MACRUM 6:40e873bbc5f7 444 __DSB(); //ensure completion of the invalidation
MACRUM 6:40e873bbc5f7 445 __ISB(); //ensure instruction fetch path sees new I cache state
MACRUM 6:40e873bbc5f7 446 }
MACRUM 6:40e873bbc5f7 447
MACRUM 6:40e873bbc5f7 448 /** \brief Clean D$ by MVA
MACRUM 6:40e873bbc5f7 449
MACRUM 6:40e873bbc5f7 450 DCCMVAC. Data cache clean by MVA to PoC
MACRUM 6:40e873bbc5f7 451 */
MACRUM 6:40e873bbc5f7 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
MACRUM 6:40e873bbc5f7 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
MACRUM 6:40e873bbc5f7 454 __DCCMVAC = (uint32_t)va;
MACRUM 6:40e873bbc5f7 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MACRUM 6:40e873bbc5f7 456 }
MACRUM 6:40e873bbc5f7 457
MACRUM 6:40e873bbc5f7 458 /** \brief Invalidate D$ by MVA
MACRUM 6:40e873bbc5f7 459
MACRUM 6:40e873bbc5f7 460 DCIMVAC. Data cache invalidate by MVA to PoC
MACRUM 6:40e873bbc5f7 461 */
MACRUM 6:40e873bbc5f7 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
MACRUM 6:40e873bbc5f7 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
MACRUM 6:40e873bbc5f7 464 __DCIMVAC = (uint32_t)va;
MACRUM 6:40e873bbc5f7 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MACRUM 6:40e873bbc5f7 466 }
MACRUM 6:40e873bbc5f7 467
MACRUM 6:40e873bbc5f7 468 /** \brief Clean and Invalidate D$ by MVA
MACRUM 6:40e873bbc5f7 469
MACRUM 6:40e873bbc5f7 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
MACRUM 6:40e873bbc5f7 471 */
MACRUM 6:40e873bbc5f7 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
MACRUM 6:40e873bbc5f7 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
MACRUM 6:40e873bbc5f7 474 __DCCIMVAC = (uint32_t)va;
MACRUM 6:40e873bbc5f7 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MACRUM 6:40e873bbc5f7 476 }
MACRUM 6:40e873bbc5f7 477
MACRUM 6:40e873bbc5f7 478 /** \brief Clean and Invalidate the entire data or unified cache
MACRUM 6:40e873bbc5f7 479
MACRUM 6:40e873bbc5f7 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
MACRUM 6:40e873bbc5f7 481 */
MACRUM 6:40e873bbc5f7 482 #pragma push
MACRUM 6:40e873bbc5f7 483 #pragma arm
MACRUM 6:40e873bbc5f7 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
MACRUM 6:40e873bbc5f7 485 ARM
MACRUM 6:40e873bbc5f7 486
MACRUM 6:40e873bbc5f7 487 PUSH {R4-R11}
MACRUM 6:40e873bbc5f7 488
MACRUM 6:40e873bbc5f7 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
MACRUM 6:40e873bbc5f7 490 ANDS R3, R6, #0x07000000 // Extract coherency level
MACRUM 6:40e873bbc5f7 491 MOV R3, R3, LSR #23 // Total cache levels << 1
MACRUM 6:40e873bbc5f7 492 BEQ Finished // If 0, no need to clean
MACRUM 6:40e873bbc5f7 493
MACRUM 6:40e873bbc5f7 494 MOV R10, #0 // R10 holds current cache level << 1
MACRUM 6:40e873bbc5f7 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
MACRUM 6:40e873bbc5f7 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
MACRUM 6:40e873bbc5f7 497 AND R1, R1, #7 // Isolate those lower 3 bits
MACRUM 6:40e873bbc5f7 498 CMP R1, #2
MACRUM 6:40e873bbc5f7 499 BLT Skip // No cache or only instruction cache at this level
MACRUM 6:40e873bbc5f7 500
MACRUM 6:40e873bbc5f7 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
MACRUM 6:40e873bbc5f7 502 ISB // ISB to sync the change to the CacheSizeID reg
MACRUM 6:40e873bbc5f7 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
MACRUM 6:40e873bbc5f7 504 AND R2, R1, #7 // Extract the line length field
MACRUM 6:40e873bbc5f7 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
MACRUM 6:40e873bbc5f7 506 LDR R4, =0x3FF
MACRUM 6:40e873bbc5f7 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
MACRUM 6:40e873bbc5f7 508 CLZ R5, R4 // R5 is the bit position of the way size increment
MACRUM 6:40e873bbc5f7 509 LDR R7, =0x7FFF
MACRUM 6:40e873bbc5f7 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
MACRUM 6:40e873bbc5f7 511
MACRUM 6:40e873bbc5f7 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
MACRUM 6:40e873bbc5f7 513
MACRUM 6:40e873bbc5f7 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
MACRUM 6:40e873bbc5f7 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
MACRUM 6:40e873bbc5f7 516 CMP R0, #0
MACRUM 6:40e873bbc5f7 517 BNE Dccsw
MACRUM 6:40e873bbc5f7 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
MACRUM 6:40e873bbc5f7 519 B cont
MACRUM 6:40e873bbc5f7 520 Dccsw CMP R0, #1
MACRUM 6:40e873bbc5f7 521 BNE Dccisw
MACRUM 6:40e873bbc5f7 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
MACRUM 6:40e873bbc5f7 523 B cont
MACRUM 6:40e873bbc5f7 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
MACRUM 6:40e873bbc5f7 525 cont SUBS R9, R9, #1 // Decrement the Way number
MACRUM 6:40e873bbc5f7 526 BGE Loop3
MACRUM 6:40e873bbc5f7 527 SUBS R7, R7, #1 // Decrement the Set number
MACRUM 6:40e873bbc5f7 528 BGE Loop2
MACRUM 6:40e873bbc5f7 529 Skip ADD R10, R10, #2 // Increment the cache number
MACRUM 6:40e873bbc5f7 530 CMP R3, R10
MACRUM 6:40e873bbc5f7 531 BGT Loop1
MACRUM 6:40e873bbc5f7 532
MACRUM 6:40e873bbc5f7 533 Finished
MACRUM 6:40e873bbc5f7 534 DSB
MACRUM 6:40e873bbc5f7 535 POP {R4-R11}
MACRUM 6:40e873bbc5f7 536 BX lr
MACRUM 6:40e873bbc5f7 537
MACRUM 6:40e873bbc5f7 538 }
MACRUM 6:40e873bbc5f7 539 #pragma pop
MACRUM 6:40e873bbc5f7 540
MACRUM 6:40e873bbc5f7 541
MACRUM 6:40e873bbc5f7 542 /** \brief Invalidate the whole D$
MACRUM 6:40e873bbc5f7 543
MACRUM 6:40e873bbc5f7 544 DCISW. Invalidate by Set/Way
MACRUM 6:40e873bbc5f7 545 */
MACRUM 6:40e873bbc5f7 546
MACRUM 6:40e873bbc5f7 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
MACRUM 6:40e873bbc5f7 548 __v7_all_cache(0);
MACRUM 6:40e873bbc5f7 549 }
MACRUM 6:40e873bbc5f7 550
MACRUM 6:40e873bbc5f7 551 /** \brief Clean the whole D$
MACRUM 6:40e873bbc5f7 552
MACRUM 6:40e873bbc5f7 553 DCCSW. Clean by Set/Way
MACRUM 6:40e873bbc5f7 554 */
MACRUM 6:40e873bbc5f7 555
MACRUM 6:40e873bbc5f7 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
MACRUM 6:40e873bbc5f7 557 __v7_all_cache(1);
MACRUM 6:40e873bbc5f7 558 }
MACRUM 6:40e873bbc5f7 559
MACRUM 6:40e873bbc5f7 560 /** \brief Clean and invalidate the whole D$
MACRUM 6:40e873bbc5f7 561
MACRUM 6:40e873bbc5f7 562 DCCISW. Clean and Invalidate by Set/Way
MACRUM 6:40e873bbc5f7 563 */
MACRUM 6:40e873bbc5f7 564
MACRUM 6:40e873bbc5f7 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
MACRUM 6:40e873bbc5f7 566 __v7_all_cache(2);
MACRUM 6:40e873bbc5f7 567 }
MACRUM 6:40e873bbc5f7 568
MACRUM 6:40e873bbc5f7 569 #include "core_ca_mmu.h"
MACRUM 6:40e873bbc5f7 570
MACRUM 6:40e873bbc5f7 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
MACRUM 6:40e873bbc5f7 572
MACRUM 6:40e873bbc5f7 573 #define __inline inline
MACRUM 6:40e873bbc5f7 574
MACRUM 6:40e873bbc5f7 575 inline static uint32_t __disable_irq_iar() {
MACRUM 6:40e873bbc5f7 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
MACRUM 6:40e873bbc5f7 577 __disable_irq();
MACRUM 6:40e873bbc5f7 578 return irq_dis;
MACRUM 6:40e873bbc5f7 579 }
MACRUM 6:40e873bbc5f7 580
MACRUM 6:40e873bbc5f7 581 #define MODE_USR 0x10
MACRUM 6:40e873bbc5f7 582 #define MODE_FIQ 0x11
MACRUM 6:40e873bbc5f7 583 #define MODE_IRQ 0x12
MACRUM 6:40e873bbc5f7 584 #define MODE_SVC 0x13
MACRUM 6:40e873bbc5f7 585 #define MODE_MON 0x16
MACRUM 6:40e873bbc5f7 586 #define MODE_ABT 0x17
MACRUM 6:40e873bbc5f7 587 #define MODE_HYP 0x1A
MACRUM 6:40e873bbc5f7 588 #define MODE_UND 0x1B
MACRUM 6:40e873bbc5f7 589 #define MODE_SYS 0x1F
MACRUM 6:40e873bbc5f7 590
MACRUM 6:40e873bbc5f7 591 /** \brief Set Process Stack Pointer
MACRUM 6:40e873bbc5f7 592
MACRUM 6:40e873bbc5f7 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
MACRUM 6:40e873bbc5f7 594
MACRUM 6:40e873bbc5f7 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
MACRUM 6:40e873bbc5f7 596 */
MACRUM 6:40e873bbc5f7 597 // from rt_CMSIS.c
MACRUM 6:40e873bbc5f7 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
MACRUM 6:40e873bbc5f7 599 __asm(
MACRUM 6:40e873bbc5f7 600 " ARM\n"
MACRUM 6:40e873bbc5f7 601 // " PRESERVE8\n"
MACRUM 6:40e873bbc5f7 602
MACRUM 6:40e873bbc5f7 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
MACRUM 6:40e873bbc5f7 604 " MRS R1, CPSR \n"
MACRUM 6:40e873bbc5f7 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
MACRUM 6:40e873bbc5f7 606 " MOV SP, R0 \n"
MACRUM 6:40e873bbc5f7 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
MACRUM 6:40e873bbc5f7 608 " ISB \n"
MACRUM 6:40e873bbc5f7 609 " BX LR \n");
MACRUM 6:40e873bbc5f7 610 }
MACRUM 6:40e873bbc5f7 611
MACRUM 6:40e873bbc5f7 612 /** \brief Set User Mode
MACRUM 6:40e873bbc5f7 613
MACRUM 6:40e873bbc5f7 614 This function changes the processor state to User Mode
MACRUM 6:40e873bbc5f7 615 */
MACRUM 6:40e873bbc5f7 616 // from rt_CMSIS.c
MACRUM 6:40e873bbc5f7 617 __arm static inline void __set_CPS_USR(void) {
MACRUM 6:40e873bbc5f7 618 __asm(
MACRUM 6:40e873bbc5f7 619 " ARM \n"
MACRUM 6:40e873bbc5f7 620
MACRUM 6:40e873bbc5f7 621 " CPS #0x10 \n" // MODE_USR
MACRUM 6:40e873bbc5f7 622 " BX LR\n");
MACRUM 6:40e873bbc5f7 623 }
MACRUM 6:40e873bbc5f7 624
MACRUM 6:40e873bbc5f7 625 /** \brief Set TTBR0
MACRUM 6:40e873bbc5f7 626
MACRUM 6:40e873bbc5f7 627 This function assigns the given value to the Translation Table Base Register 0.
MACRUM 6:40e873bbc5f7 628
MACRUM 6:40e873bbc5f7 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
MACRUM 6:40e873bbc5f7 630 */
MACRUM 6:40e873bbc5f7 631 // from mmu_Renesas_RZ_A1.c
MACRUM 6:40e873bbc5f7 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
MACRUM 6:40e873bbc5f7 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
MACRUM 6:40e873bbc5f7 634 __ISB();
MACRUM 6:40e873bbc5f7 635 }
MACRUM 6:40e873bbc5f7 636
MACRUM 6:40e873bbc5f7 637 /** \brief Set DACR
MACRUM 6:40e873bbc5f7 638
MACRUM 6:40e873bbc5f7 639 This function assigns the given value to the Domain Access Control Register.
MACRUM 6:40e873bbc5f7 640
MACRUM 6:40e873bbc5f7 641 \param [in] dacr Domain Access Control Register value to set
MACRUM 6:40e873bbc5f7 642 */
MACRUM 6:40e873bbc5f7 643 // from mmu_Renesas_RZ_A1.c
MACRUM 6:40e873bbc5f7 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
MACRUM 6:40e873bbc5f7 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
MACRUM 6:40e873bbc5f7 646 __ISB();
MACRUM 6:40e873bbc5f7 647 }
MACRUM 6:40e873bbc5f7 648
MACRUM 6:40e873bbc5f7 649
MACRUM 6:40e873bbc5f7 650 /******************************** Cache and BTAC enable ****************************************************/
MACRUM 6:40e873bbc5f7 651 /** \brief Set SCTLR
MACRUM 6:40e873bbc5f7 652
MACRUM 6:40e873bbc5f7 653 This function assigns the given value to the System Control Register.
MACRUM 6:40e873bbc5f7 654
MACRUM 6:40e873bbc5f7 655 \param [in] sctlr System Control Register value to set
MACRUM 6:40e873bbc5f7 656 */
MACRUM 6:40e873bbc5f7 657 // from __enable_mmu()
MACRUM 6:40e873bbc5f7 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
MACRUM 6:40e873bbc5f7 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
MACRUM 6:40e873bbc5f7 660 }
MACRUM 6:40e873bbc5f7 661
MACRUM 6:40e873bbc5f7 662 /** \brief Get SCTLR
MACRUM 6:40e873bbc5f7 663
MACRUM 6:40e873bbc5f7 664 This function returns the value of the System Control Register.
MACRUM 6:40e873bbc5f7 665
MACRUM 6:40e873bbc5f7 666 \return System Control Register value
MACRUM 6:40e873bbc5f7 667 */
MACRUM 6:40e873bbc5f7 668 // from __enable_mmu()
MACRUM 6:40e873bbc5f7 669 __STATIC_INLINE uint32_t __get_SCTLR() {
MACRUM 6:40e873bbc5f7 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
MACRUM 6:40e873bbc5f7 671 return __regSCTLR;
MACRUM 6:40e873bbc5f7 672 }
MACRUM 6:40e873bbc5f7 673
MACRUM 6:40e873bbc5f7 674 /** \brief Enable Caches
MACRUM 6:40e873bbc5f7 675
MACRUM 6:40e873bbc5f7 676 Enable Caches
MACRUM 6:40e873bbc5f7 677 */
MACRUM 6:40e873bbc5f7 678 // from system_Renesas_RZ_A1.c
MACRUM 6:40e873bbc5f7 679 __STATIC_INLINE void __enable_caches(void) {
MACRUM 6:40e873bbc5f7 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
MACRUM 6:40e873bbc5f7 681 }
MACRUM 6:40e873bbc5f7 682
MACRUM 6:40e873bbc5f7 683 /** \brief Enable BTAC
MACRUM 6:40e873bbc5f7 684
MACRUM 6:40e873bbc5f7 685 Enable BTAC
MACRUM 6:40e873bbc5f7 686 */
MACRUM 6:40e873bbc5f7 687 // from system_Renesas_RZ_A1.c
MACRUM 6:40e873bbc5f7 688 __STATIC_INLINE void __enable_btac(void) {
MACRUM 6:40e873bbc5f7 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
MACRUM 6:40e873bbc5f7 690 __ISB();
MACRUM 6:40e873bbc5f7 691 }
MACRUM 6:40e873bbc5f7 692
MACRUM 6:40e873bbc5f7 693 /** \brief Enable MMU
MACRUM 6:40e873bbc5f7 694
MACRUM 6:40e873bbc5f7 695 Enable MMU
MACRUM 6:40e873bbc5f7 696 */
MACRUM 6:40e873bbc5f7 697 // from system_Renesas_RZ_A1.c
MACRUM 6:40e873bbc5f7 698 __STATIC_INLINE void __enable_mmu(void) {
MACRUM 6:40e873bbc5f7 699 // Set M bit 0 to enable the MMU
MACRUM 6:40e873bbc5f7 700 // Set AFE bit to enable simplified access permissions model
MACRUM 6:40e873bbc5f7 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
MACRUM 6:40e873bbc5f7 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
MACRUM 6:40e873bbc5f7 703 __ISB();
MACRUM 6:40e873bbc5f7 704 }
MACRUM 6:40e873bbc5f7 705
MACRUM 6:40e873bbc5f7 706 /******************************** TLB maintenance operations ************************************************/
MACRUM 6:40e873bbc5f7 707 /** \brief Invalidate the whole tlb
MACRUM 6:40e873bbc5f7 708
MACRUM 6:40e873bbc5f7 709 TLBIALL. Invalidate the whole tlb
MACRUM 6:40e873bbc5f7 710 */
MACRUM 6:40e873bbc5f7 711 // from system_Renesas_RZ_A1.c
MACRUM 6:40e873bbc5f7 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
MACRUM 6:40e873bbc5f7 713 uint32_t val = 0;
MACRUM 6:40e873bbc5f7 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
MACRUM 6:40e873bbc5f7 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
MACRUM 6:40e873bbc5f7 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
MACRUM 6:40e873bbc5f7 717 __DSB();
MACRUM 6:40e873bbc5f7 718 __ISB();
MACRUM 6:40e873bbc5f7 719 }
MACRUM 6:40e873bbc5f7 720
MACRUM 6:40e873bbc5f7 721 /******************************** BTB maintenance operations ************************************************/
MACRUM 6:40e873bbc5f7 722 /** \brief Invalidate entire branch predictor array
MACRUM 6:40e873bbc5f7 723
MACRUM 6:40e873bbc5f7 724 BPIALL. Branch Predictor Invalidate All.
MACRUM 6:40e873bbc5f7 725 */
MACRUM 6:40e873bbc5f7 726 // from system_Renesas_RZ_A1.c
MACRUM 6:40e873bbc5f7 727 __STATIC_INLINE void __v7_inv_btac(void) {
MACRUM 6:40e873bbc5f7 728 uint32_t val = 0;
MACRUM 6:40e873bbc5f7 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
MACRUM 6:40e873bbc5f7 730 __DSB(); //ensure completion of the invalidation
MACRUM 6:40e873bbc5f7 731 __ISB(); //ensure instruction fetch path sees new state
MACRUM 6:40e873bbc5f7 732 }
MACRUM 6:40e873bbc5f7 733
MACRUM 6:40e873bbc5f7 734
MACRUM 6:40e873bbc5f7 735 /******************************** L1 cache operations ******************************************************/
MACRUM 6:40e873bbc5f7 736
MACRUM 6:40e873bbc5f7 737 /** \brief Invalidate the whole I$
MACRUM 6:40e873bbc5f7 738
MACRUM 6:40e873bbc5f7 739 ICIALLU. Instruction Cache Invalidate All to PoU
MACRUM 6:40e873bbc5f7 740 */
MACRUM 6:40e873bbc5f7 741 // from system_Renesas_RZ_A1.c
MACRUM 6:40e873bbc5f7 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
MACRUM 6:40e873bbc5f7 743 uint32_t val = 0;
MACRUM 6:40e873bbc5f7 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
MACRUM 6:40e873bbc5f7 745 __DSB(); //ensure completion of the invalidation
MACRUM 6:40e873bbc5f7 746 __ISB(); //ensure instruction fetch path sees new I cache state
MACRUM 6:40e873bbc5f7 747 }
MACRUM 6:40e873bbc5f7 748
MACRUM 6:40e873bbc5f7 749 // from __v7_inv_dcache_all()
MACRUM 6:40e873bbc5f7 750 __arm static inline void __v7_all_cache(uint32_t op) {
MACRUM 6:40e873bbc5f7 751 __asm(
MACRUM 6:40e873bbc5f7 752 " ARM \n"
MACRUM 6:40e873bbc5f7 753
MACRUM 6:40e873bbc5f7 754 " PUSH {R4-R11} \n"
MACRUM 6:40e873bbc5f7 755
MACRUM 6:40e873bbc5f7 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
MACRUM 6:40e873bbc5f7 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
MACRUM 6:40e873bbc5f7 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
MACRUM 6:40e873bbc5f7 759 " BEQ Finished\n" // If 0, no need to clean
MACRUM 6:40e873bbc5f7 760
MACRUM 6:40e873bbc5f7 761 " MOV R10, #0\n" // R10 holds current cache level << 1
MACRUM 6:40e873bbc5f7 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
MACRUM 6:40e873bbc5f7 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
MACRUM 6:40e873bbc5f7 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
MACRUM 6:40e873bbc5f7 765 " CMP R1, #2 \n"
MACRUM 6:40e873bbc5f7 766 " BLT Skip \n" // No cache or only instruction cache at this level
MACRUM 6:40e873bbc5f7 767
MACRUM 6:40e873bbc5f7 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
MACRUM 6:40e873bbc5f7 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
MACRUM 6:40e873bbc5f7 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
MACRUM 6:40e873bbc5f7 771 " AND R2, R1, #7 \n" // Extract the line length field
MACRUM 6:40e873bbc5f7 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
MACRUM 6:40e873bbc5f7 773 " movw R4, #0x3FF \n"
MACRUM 6:40e873bbc5f7 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
MACRUM 6:40e873bbc5f7 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
MACRUM 6:40e873bbc5f7 776 " movw R7, #0x7FFF \n"
MACRUM 6:40e873bbc5f7 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
MACRUM 6:40e873bbc5f7 778
MACRUM 6:40e873bbc5f7 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
MACRUM 6:40e873bbc5f7 780
MACRUM 6:40e873bbc5f7 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
MACRUM 6:40e873bbc5f7 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
MACRUM 6:40e873bbc5f7 783 " CMP R0, #0 \n"
MACRUM 6:40e873bbc5f7 784 " BNE Dccsw \n"
MACRUM 6:40e873bbc5f7 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
MACRUM 6:40e873bbc5f7 786 " B cont \n"
MACRUM 6:40e873bbc5f7 787 "Dccsw: CMP R0, #1 \n"
MACRUM 6:40e873bbc5f7 788 " BNE Dccisw \n"
MACRUM 6:40e873bbc5f7 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
MACRUM 6:40e873bbc5f7 790 " B cont \n"
MACRUM 6:40e873bbc5f7 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
MACRUM 6:40e873bbc5f7 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
MACRUM 6:40e873bbc5f7 793 " BGE Loop3 \n"
MACRUM 6:40e873bbc5f7 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
MACRUM 6:40e873bbc5f7 795 " BGE Loop2 \n"
MACRUM 6:40e873bbc5f7 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
MACRUM 6:40e873bbc5f7 797 " CMP R3, R10 \n"
MACRUM 6:40e873bbc5f7 798 " BGT Loop1 \n"
MACRUM 6:40e873bbc5f7 799
MACRUM 6:40e873bbc5f7 800 "Finished: \n"
MACRUM 6:40e873bbc5f7 801 " DSB \n"
MACRUM 6:40e873bbc5f7 802 " POP {R4-R11} \n"
MACRUM 6:40e873bbc5f7 803 " BX lr \n" );
MACRUM 6:40e873bbc5f7 804 }
MACRUM 6:40e873bbc5f7 805
MACRUM 6:40e873bbc5f7 806 /** \brief Invalidate the whole D$
MACRUM 6:40e873bbc5f7 807
MACRUM 6:40e873bbc5f7 808 DCISW. Invalidate by Set/Way
MACRUM 6:40e873bbc5f7 809 */
MACRUM 6:40e873bbc5f7 810 // from system_Renesas_RZ_A1.c
MACRUM 6:40e873bbc5f7 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
MACRUM 6:40e873bbc5f7 812 __v7_all_cache(0);
MACRUM 6:40e873bbc5f7 813 }
MACRUM 6:40e873bbc5f7 814 /** \brief Clean the whole D$
MACRUM 6:40e873bbc5f7 815
MACRUM 6:40e873bbc5f7 816 DCCSW. Clean by Set/Way
MACRUM 6:40e873bbc5f7 817 */
MACRUM 6:40e873bbc5f7 818
MACRUM 6:40e873bbc5f7 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
MACRUM 6:40e873bbc5f7 820 __v7_all_cache(1);
MACRUM 6:40e873bbc5f7 821 }
MACRUM 6:40e873bbc5f7 822
MACRUM 6:40e873bbc5f7 823 /** \brief Clean and invalidate the whole D$
MACRUM 6:40e873bbc5f7 824
MACRUM 6:40e873bbc5f7 825 DCCISW. Clean and Invalidate by Set/Way
MACRUM 6:40e873bbc5f7 826 */
MACRUM 6:40e873bbc5f7 827
MACRUM 6:40e873bbc5f7 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
MACRUM 6:40e873bbc5f7 829 __v7_all_cache(2);
MACRUM 6:40e873bbc5f7 830 }
MACRUM 6:40e873bbc5f7 831 /** \brief Clean and Invalidate D$ by MVA
MACRUM 6:40e873bbc5f7 832
MACRUM 6:40e873bbc5f7 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
MACRUM 6:40e873bbc5f7 834 */
MACRUM 6:40e873bbc5f7 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
MACRUM 6:40e873bbc5f7 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
MACRUM 6:40e873bbc5f7 837 __DMB();
MACRUM 6:40e873bbc5f7 838 }
MACRUM 6:40e873bbc5f7 839
MACRUM 6:40e873bbc5f7 840 #include "core_ca_mmu.h"
MACRUM 6:40e873bbc5f7 841
MACRUM 6:40e873bbc5f7 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
MACRUM 6:40e873bbc5f7 843 /* GNU gcc specific functions */
MACRUM 6:40e873bbc5f7 844
MACRUM 6:40e873bbc5f7 845 #define MODE_USR 0x10
MACRUM 6:40e873bbc5f7 846 #define MODE_FIQ 0x11
MACRUM 6:40e873bbc5f7 847 #define MODE_IRQ 0x12
MACRUM 6:40e873bbc5f7 848 #define MODE_SVC 0x13
MACRUM 6:40e873bbc5f7 849 #define MODE_MON 0x16
MACRUM 6:40e873bbc5f7 850 #define MODE_ABT 0x17
MACRUM 6:40e873bbc5f7 851 #define MODE_HYP 0x1A
MACRUM 6:40e873bbc5f7 852 #define MODE_UND 0x1B
MACRUM 6:40e873bbc5f7 853 #define MODE_SYS 0x1F
MACRUM 6:40e873bbc5f7 854
MACRUM 6:40e873bbc5f7 855
MACRUM 6:40e873bbc5f7 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
MACRUM 6:40e873bbc5f7 857 {
MACRUM 6:40e873bbc5f7 858 __ASM volatile ("cpsie i");
MACRUM 6:40e873bbc5f7 859 }
MACRUM 6:40e873bbc5f7 860
MACRUM 6:40e873bbc5f7 861 /** \brief Disable IRQ Interrupts
MACRUM 6:40e873bbc5f7 862
MACRUM 6:40e873bbc5f7 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
MACRUM 6:40e873bbc5f7 864 Can only be executed in Privileged modes.
MACRUM 6:40e873bbc5f7 865 */
MACRUM 6:40e873bbc5f7 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
MACRUM 6:40e873bbc5f7 867 {
MACRUM 6:40e873bbc5f7 868 uint32_t result;
MACRUM 6:40e873bbc5f7 869
MACRUM 6:40e873bbc5f7 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
MACRUM 6:40e873bbc5f7 871 __ASM volatile ("cpsid i");
MACRUM 6:40e873bbc5f7 872 return(result & 0x80);
MACRUM 6:40e873bbc5f7 873 }
MACRUM 6:40e873bbc5f7 874
MACRUM 6:40e873bbc5f7 875
MACRUM 6:40e873bbc5f7 876 /** \brief Get APSR Register
MACRUM 6:40e873bbc5f7 877
MACRUM 6:40e873bbc5f7 878 This function returns the content of the APSR Register.
MACRUM 6:40e873bbc5f7 879
MACRUM 6:40e873bbc5f7 880 \return APSR Register value
MACRUM 6:40e873bbc5f7 881 */
MACRUM 6:40e873bbc5f7 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
MACRUM 6:40e873bbc5f7 883 {
MACRUM 6:40e873bbc5f7 884 #if 1
MACRUM 6:40e873bbc5f7 885 register uint32_t __regAPSR;
MACRUM 6:40e873bbc5f7 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
MACRUM 6:40e873bbc5f7 887 #else
MACRUM 6:40e873bbc5f7 888 register uint32_t __regAPSR __ASM("apsr");
MACRUM 6:40e873bbc5f7 889 #endif
MACRUM 6:40e873bbc5f7 890 return(__regAPSR);
MACRUM 6:40e873bbc5f7 891 }
MACRUM 6:40e873bbc5f7 892
MACRUM 6:40e873bbc5f7 893
MACRUM 6:40e873bbc5f7 894 /** \brief Get CPSR Register
MACRUM 6:40e873bbc5f7 895
MACRUM 6:40e873bbc5f7 896 This function returns the content of the CPSR Register.
MACRUM 6:40e873bbc5f7 897
MACRUM 6:40e873bbc5f7 898 \return CPSR Register value
MACRUM 6:40e873bbc5f7 899 */
MACRUM 6:40e873bbc5f7 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
MACRUM 6:40e873bbc5f7 901 {
MACRUM 6:40e873bbc5f7 902 #if 1
MACRUM 6:40e873bbc5f7 903 register uint32_t __regCPSR;
MACRUM 6:40e873bbc5f7 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
MACRUM 6:40e873bbc5f7 905 #else
MACRUM 6:40e873bbc5f7 906 register uint32_t __regCPSR __ASM("cpsr");
MACRUM 6:40e873bbc5f7 907 #endif
MACRUM 6:40e873bbc5f7 908 return(__regCPSR);
MACRUM 6:40e873bbc5f7 909 }
MACRUM 6:40e873bbc5f7 910
MACRUM 6:40e873bbc5f7 911 #if 0
MACRUM 6:40e873bbc5f7 912 /** \brief Set Stack Pointer
MACRUM 6:40e873bbc5f7 913
MACRUM 6:40e873bbc5f7 914 This function assigns the given value to the current stack pointer.
MACRUM 6:40e873bbc5f7 915
MACRUM 6:40e873bbc5f7 916 \param [in] topOfStack Stack Pointer value to set
MACRUM 6:40e873bbc5f7 917 */
MACRUM 6:40e873bbc5f7 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
MACRUM 6:40e873bbc5f7 919 {
MACRUM 6:40e873bbc5f7 920 register uint32_t __regSP __ASM("sp");
MACRUM 6:40e873bbc5f7 921 __regSP = topOfStack;
MACRUM 6:40e873bbc5f7 922 }
MACRUM 6:40e873bbc5f7 923 #endif
MACRUM 6:40e873bbc5f7 924
MACRUM 6:40e873bbc5f7 925 /** \brief Get link register
MACRUM 6:40e873bbc5f7 926
MACRUM 6:40e873bbc5f7 927 This function returns the value of the link register
MACRUM 6:40e873bbc5f7 928
MACRUM 6:40e873bbc5f7 929 \return Value of link register
MACRUM 6:40e873bbc5f7 930 */
MACRUM 6:40e873bbc5f7 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
MACRUM 6:40e873bbc5f7 932 {
MACRUM 6:40e873bbc5f7 933 register uint32_t __reglr __ASM("lr");
MACRUM 6:40e873bbc5f7 934 return(__reglr);
MACRUM 6:40e873bbc5f7 935 }
MACRUM 6:40e873bbc5f7 936
MACRUM 6:40e873bbc5f7 937 #if 0
MACRUM 6:40e873bbc5f7 938 /** \brief Set link register
MACRUM 6:40e873bbc5f7 939
MACRUM 6:40e873bbc5f7 940 This function sets the value of the link register
MACRUM 6:40e873bbc5f7 941
MACRUM 6:40e873bbc5f7 942 \param [in] lr LR value to set
MACRUM 6:40e873bbc5f7 943 */
MACRUM 6:40e873bbc5f7 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
MACRUM 6:40e873bbc5f7 945 {
MACRUM 6:40e873bbc5f7 946 register uint32_t __reglr __ASM("lr");
MACRUM 6:40e873bbc5f7 947 __reglr = lr;
MACRUM 6:40e873bbc5f7 948 }
MACRUM 6:40e873bbc5f7 949 #endif
MACRUM 6:40e873bbc5f7 950
MACRUM 6:40e873bbc5f7 951 /** \brief Set Process Stack Pointer
MACRUM 6:40e873bbc5f7 952
MACRUM 6:40e873bbc5f7 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
MACRUM 6:40e873bbc5f7 954
MACRUM 6:40e873bbc5f7 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
MACRUM 6:40e873bbc5f7 956 */
MACRUM 6:40e873bbc5f7 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MACRUM 6:40e873bbc5f7 958 {
MACRUM 6:40e873bbc5f7 959 __asm__ volatile (
MACRUM 6:40e873bbc5f7 960 ".ARM;"
MACRUM 6:40e873bbc5f7 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
MACRUM 6:40e873bbc5f7 962
MACRUM 6:40e873bbc5f7 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
MACRUM 6:40e873bbc5f7 964 "MRS R1, CPSR;"
MACRUM 6:40e873bbc5f7 965 "CPS %0;" /* ;no effect in USR mode */
MACRUM 6:40e873bbc5f7 966 "MOV SP, R0;"
MACRUM 6:40e873bbc5f7 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
MACRUM 6:40e873bbc5f7 968 "ISB;"
MACRUM 6:40e873bbc5f7 969 //"BX LR;"
MACRUM 6:40e873bbc5f7 970 :
MACRUM 6:40e873bbc5f7 971 : "i"(MODE_SYS)
MACRUM 6:40e873bbc5f7 972 : "r0", "r1");
MACRUM 6:40e873bbc5f7 973 return;
MACRUM 6:40e873bbc5f7 974 }
MACRUM 6:40e873bbc5f7 975
MACRUM 6:40e873bbc5f7 976 /** \brief Set User Mode
MACRUM 6:40e873bbc5f7 977
MACRUM 6:40e873bbc5f7 978 This function changes the processor state to User Mode
MACRUM 6:40e873bbc5f7 979 */
MACRUM 6:40e873bbc5f7 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
MACRUM 6:40e873bbc5f7 981 {
MACRUM 6:40e873bbc5f7 982 __asm__ volatile (
MACRUM 6:40e873bbc5f7 983 ".ARM;"
MACRUM 6:40e873bbc5f7 984
MACRUM 6:40e873bbc5f7 985 "CPS %0;"
MACRUM 6:40e873bbc5f7 986 //"BX LR;"
MACRUM 6:40e873bbc5f7 987 :
MACRUM 6:40e873bbc5f7 988 : "i"(MODE_USR)
MACRUM 6:40e873bbc5f7 989 : );
MACRUM 6:40e873bbc5f7 990 return;
MACRUM 6:40e873bbc5f7 991 }
MACRUM 6:40e873bbc5f7 992
MACRUM 6:40e873bbc5f7 993
MACRUM 6:40e873bbc5f7 994 /** \brief Enable FIQ
MACRUM 6:40e873bbc5f7 995
MACRUM 6:40e873bbc5f7 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MACRUM 6:40e873bbc5f7 997 Can only be executed in Privileged modes.
MACRUM 6:40e873bbc5f7 998 */
MACRUM 6:40e873bbc5f7 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
MACRUM 6:40e873bbc5f7 1000
MACRUM 6:40e873bbc5f7 1001
MACRUM 6:40e873bbc5f7 1002 /** \brief Disable FIQ
MACRUM 6:40e873bbc5f7 1003
MACRUM 6:40e873bbc5f7 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MACRUM 6:40e873bbc5f7 1005 Can only be executed in Privileged modes.
MACRUM 6:40e873bbc5f7 1006 */
MACRUM 6:40e873bbc5f7 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
MACRUM 6:40e873bbc5f7 1008
MACRUM 6:40e873bbc5f7 1009
MACRUM 6:40e873bbc5f7 1010 /** \brief Get FPSCR
MACRUM 6:40e873bbc5f7 1011
MACRUM 6:40e873bbc5f7 1012 This function returns the current value of the Floating Point Status/Control register.
MACRUM 6:40e873bbc5f7 1013
MACRUM 6:40e873bbc5f7 1014 \return Floating Point Status/Control register value
MACRUM 6:40e873bbc5f7 1015 */
MACRUM 6:40e873bbc5f7 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
MACRUM 6:40e873bbc5f7 1017 {
MACRUM 6:40e873bbc5f7 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MACRUM 6:40e873bbc5f7 1019 #if 1
MACRUM 6:40e873bbc5f7 1020 uint32_t result;
MACRUM 6:40e873bbc5f7 1021
MACRUM 6:40e873bbc5f7 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
MACRUM 6:40e873bbc5f7 1023 return (result);
MACRUM 6:40e873bbc5f7 1024 #else
MACRUM 6:40e873bbc5f7 1025 register uint32_t __regfpscr __ASM("fpscr");
MACRUM 6:40e873bbc5f7 1026 return(__regfpscr);
MACRUM 6:40e873bbc5f7 1027 #endif
MACRUM 6:40e873bbc5f7 1028 #else
MACRUM 6:40e873bbc5f7 1029 return(0);
MACRUM 6:40e873bbc5f7 1030 #endif
MACRUM 6:40e873bbc5f7 1031 }
MACRUM 6:40e873bbc5f7 1032
MACRUM 6:40e873bbc5f7 1033
MACRUM 6:40e873bbc5f7 1034 /** \brief Set FPSCR
MACRUM 6:40e873bbc5f7 1035
MACRUM 6:40e873bbc5f7 1036 This function assigns the given value to the Floating Point Status/Control register.
MACRUM 6:40e873bbc5f7 1037
MACRUM 6:40e873bbc5f7 1038 \param [in] fpscr Floating Point Status/Control value to set
MACRUM 6:40e873bbc5f7 1039 */
MACRUM 6:40e873bbc5f7 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MACRUM 6:40e873bbc5f7 1041 {
MACRUM 6:40e873bbc5f7 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MACRUM 6:40e873bbc5f7 1043 #if 1
MACRUM 6:40e873bbc5f7 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
MACRUM 6:40e873bbc5f7 1045 #else
MACRUM 6:40e873bbc5f7 1046 register uint32_t __regfpscr __ASM("fpscr");
MACRUM 6:40e873bbc5f7 1047 __regfpscr = (fpscr);
MACRUM 6:40e873bbc5f7 1048 #endif
MACRUM 6:40e873bbc5f7 1049 #endif
MACRUM 6:40e873bbc5f7 1050 }
MACRUM 6:40e873bbc5f7 1051
MACRUM 6:40e873bbc5f7 1052 /** \brief Get FPEXC
MACRUM 6:40e873bbc5f7 1053
MACRUM 6:40e873bbc5f7 1054 This function returns the current value of the Floating Point Exception Control register.
MACRUM 6:40e873bbc5f7 1055
MACRUM 6:40e873bbc5f7 1056 \return Floating Point Exception Control register value
MACRUM 6:40e873bbc5f7 1057 */
MACRUM 6:40e873bbc5f7 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
MACRUM 6:40e873bbc5f7 1059 {
MACRUM 6:40e873bbc5f7 1060 #if (__FPU_PRESENT == 1)
MACRUM 6:40e873bbc5f7 1061 #if 1
MACRUM 6:40e873bbc5f7 1062 uint32_t result;
MACRUM 6:40e873bbc5f7 1063
MACRUM 6:40e873bbc5f7 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
MACRUM 6:40e873bbc5f7 1065 return (result);
MACRUM 6:40e873bbc5f7 1066 #else
MACRUM 6:40e873bbc5f7 1067 register uint32_t __regfpexc __ASM("fpexc");
MACRUM 6:40e873bbc5f7 1068 return(__regfpexc);
MACRUM 6:40e873bbc5f7 1069 #endif
MACRUM 6:40e873bbc5f7 1070 #else
MACRUM 6:40e873bbc5f7 1071 return(0);
MACRUM 6:40e873bbc5f7 1072 #endif
MACRUM 6:40e873bbc5f7 1073 }
MACRUM 6:40e873bbc5f7 1074
MACRUM 6:40e873bbc5f7 1075
MACRUM 6:40e873bbc5f7 1076 /** \brief Set FPEXC
MACRUM 6:40e873bbc5f7 1077
MACRUM 6:40e873bbc5f7 1078 This function assigns the given value to the Floating Point Exception Control register.
MACRUM 6:40e873bbc5f7 1079
MACRUM 6:40e873bbc5f7 1080 \param [in] fpscr Floating Point Exception Control value to set
MACRUM 6:40e873bbc5f7 1081 */
MACRUM 6:40e873bbc5f7 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
MACRUM 6:40e873bbc5f7 1083 {
MACRUM 6:40e873bbc5f7 1084 #if (__FPU_PRESENT == 1)
MACRUM 6:40e873bbc5f7 1085 #if 1
MACRUM 6:40e873bbc5f7 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
MACRUM 6:40e873bbc5f7 1087 #else
MACRUM 6:40e873bbc5f7 1088 register uint32_t __regfpexc __ASM("fpexc");
MACRUM 6:40e873bbc5f7 1089 __regfpexc = (fpexc);
MACRUM 6:40e873bbc5f7 1090 #endif
MACRUM 6:40e873bbc5f7 1091 #endif
MACRUM 6:40e873bbc5f7 1092 }
MACRUM 6:40e873bbc5f7 1093
MACRUM 6:40e873bbc5f7 1094 /** \brief Get CPACR
MACRUM 6:40e873bbc5f7 1095
MACRUM 6:40e873bbc5f7 1096 This function returns the current value of the Coprocessor Access Control register.
MACRUM 6:40e873bbc5f7 1097
MACRUM 6:40e873bbc5f7 1098 \return Coprocessor Access Control register value
MACRUM 6:40e873bbc5f7 1099 */
MACRUM 6:40e873bbc5f7 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
MACRUM 6:40e873bbc5f7 1101 {
MACRUM 6:40e873bbc5f7 1102 #if 1
MACRUM 6:40e873bbc5f7 1103 register uint32_t __regCPACR;
MACRUM 6:40e873bbc5f7 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
MACRUM 6:40e873bbc5f7 1105 #else
MACRUM 6:40e873bbc5f7 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
MACRUM 6:40e873bbc5f7 1107 #endif
MACRUM 6:40e873bbc5f7 1108 return __regCPACR;
MACRUM 6:40e873bbc5f7 1109 }
MACRUM 6:40e873bbc5f7 1110
MACRUM 6:40e873bbc5f7 1111 /** \brief Set CPACR
MACRUM 6:40e873bbc5f7 1112
MACRUM 6:40e873bbc5f7 1113 This function assigns the given value to the Coprocessor Access Control register.
MACRUM 6:40e873bbc5f7 1114
MACRUM 6:40e873bbc5f7 1115 \param [in] cpacr Coprocessor Acccess Control value to set
MACRUM 6:40e873bbc5f7 1116 */
MACRUM 6:40e873bbc5f7 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
MACRUM 6:40e873bbc5f7 1118 {
MACRUM 6:40e873bbc5f7 1119 #if 1
MACRUM 6:40e873bbc5f7 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
MACRUM 6:40e873bbc5f7 1121 #else
MACRUM 6:40e873bbc5f7 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
MACRUM 6:40e873bbc5f7 1123 __regCPACR = cpacr;
MACRUM 6:40e873bbc5f7 1124 #endif
MACRUM 6:40e873bbc5f7 1125 __ISB();
MACRUM 6:40e873bbc5f7 1126 }
MACRUM 6:40e873bbc5f7 1127
MACRUM 6:40e873bbc5f7 1128 /** \brief Get CBAR
MACRUM 6:40e873bbc5f7 1129
MACRUM 6:40e873bbc5f7 1130 This function returns the value of the Configuration Base Address register.
MACRUM 6:40e873bbc5f7 1131
MACRUM 6:40e873bbc5f7 1132 \return Configuration Base Address register value
MACRUM 6:40e873bbc5f7 1133 */
MACRUM 6:40e873bbc5f7 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
MACRUM 6:40e873bbc5f7 1135 #if 1
MACRUM 6:40e873bbc5f7 1136 register uint32_t __regCBAR;
MACRUM 6:40e873bbc5f7 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
MACRUM 6:40e873bbc5f7 1138 #else
MACRUM 6:40e873bbc5f7 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
MACRUM 6:40e873bbc5f7 1140 #endif
MACRUM 6:40e873bbc5f7 1141 return(__regCBAR);
MACRUM 6:40e873bbc5f7 1142 }
MACRUM 6:40e873bbc5f7 1143
MACRUM 6:40e873bbc5f7 1144 /** \brief Get TTBR0
MACRUM 6:40e873bbc5f7 1145
MACRUM 6:40e873bbc5f7 1146 This function returns the value of the Translation Table Base Register 0.
MACRUM 6:40e873bbc5f7 1147
MACRUM 6:40e873bbc5f7 1148 \return Translation Table Base Register 0 value
MACRUM 6:40e873bbc5f7 1149 */
MACRUM 6:40e873bbc5f7 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
MACRUM 6:40e873bbc5f7 1151 #if 1
MACRUM 6:40e873bbc5f7 1152 register uint32_t __regTTBR0;
MACRUM 6:40e873bbc5f7 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
MACRUM 6:40e873bbc5f7 1154 #else
MACRUM 6:40e873bbc5f7 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
MACRUM 6:40e873bbc5f7 1156 #endif
MACRUM 6:40e873bbc5f7 1157 return(__regTTBR0);
MACRUM 6:40e873bbc5f7 1158 }
MACRUM 6:40e873bbc5f7 1159
MACRUM 6:40e873bbc5f7 1160 /** \brief Set TTBR0
MACRUM 6:40e873bbc5f7 1161
MACRUM 6:40e873bbc5f7 1162 This function assigns the given value to the Translation Table Base Register 0.
MACRUM 6:40e873bbc5f7 1163
MACRUM 6:40e873bbc5f7 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
MACRUM 6:40e873bbc5f7 1165 */
MACRUM 6:40e873bbc5f7 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
MACRUM 6:40e873bbc5f7 1167 #if 1
MACRUM 6:40e873bbc5f7 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
MACRUM 6:40e873bbc5f7 1169 #else
MACRUM 6:40e873bbc5f7 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
MACRUM 6:40e873bbc5f7 1171 __regTTBR0 = ttbr0;
MACRUM 6:40e873bbc5f7 1172 #endif
MACRUM 6:40e873bbc5f7 1173 __ISB();
MACRUM 6:40e873bbc5f7 1174 }
MACRUM 6:40e873bbc5f7 1175
MACRUM 6:40e873bbc5f7 1176 /** \brief Get DACR
MACRUM 6:40e873bbc5f7 1177
MACRUM 6:40e873bbc5f7 1178 This function returns the value of the Domain Access Control Register.
MACRUM 6:40e873bbc5f7 1179
MACRUM 6:40e873bbc5f7 1180 \return Domain Access Control Register value
MACRUM 6:40e873bbc5f7 1181 */
MACRUM 6:40e873bbc5f7 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
MACRUM 6:40e873bbc5f7 1183 #if 1
MACRUM 6:40e873bbc5f7 1184 register uint32_t __regDACR;
MACRUM 6:40e873bbc5f7 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
MACRUM 6:40e873bbc5f7 1186 #else
MACRUM 6:40e873bbc5f7 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
MACRUM 6:40e873bbc5f7 1188 #endif
MACRUM 6:40e873bbc5f7 1189 return(__regDACR);
MACRUM 6:40e873bbc5f7 1190 }
MACRUM 6:40e873bbc5f7 1191
MACRUM 6:40e873bbc5f7 1192 /** \brief Set DACR
MACRUM 6:40e873bbc5f7 1193
MACRUM 6:40e873bbc5f7 1194 This function assigns the given value to the Domain Access Control Register.
MACRUM 6:40e873bbc5f7 1195
MACRUM 6:40e873bbc5f7 1196 \param [in] dacr Domain Access Control Register value to set
MACRUM 6:40e873bbc5f7 1197 */
MACRUM 6:40e873bbc5f7 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
MACRUM 6:40e873bbc5f7 1199 #if 1
MACRUM 6:40e873bbc5f7 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
MACRUM 6:40e873bbc5f7 1201 #else
MACRUM 6:40e873bbc5f7 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
MACRUM 6:40e873bbc5f7 1203 __regDACR = dacr;
MACRUM 6:40e873bbc5f7 1204 #endif
MACRUM 6:40e873bbc5f7 1205 __ISB();
MACRUM 6:40e873bbc5f7 1206 }
MACRUM 6:40e873bbc5f7 1207
MACRUM 6:40e873bbc5f7 1208 /******************************** Cache and BTAC enable ****************************************************/
MACRUM 6:40e873bbc5f7 1209
MACRUM 6:40e873bbc5f7 1210 /** \brief Set SCTLR
MACRUM 6:40e873bbc5f7 1211
MACRUM 6:40e873bbc5f7 1212 This function assigns the given value to the System Control Register.
MACRUM 6:40e873bbc5f7 1213
MACRUM 6:40e873bbc5f7 1214 \param [in] sctlr System Control Register value to set
MACRUM 6:40e873bbc5f7 1215 */
MACRUM 6:40e873bbc5f7 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
MACRUM 6:40e873bbc5f7 1217 {
MACRUM 6:40e873bbc5f7 1218 #if 1
MACRUM 6:40e873bbc5f7 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
MACRUM 6:40e873bbc5f7 1220 #else
MACRUM 6:40e873bbc5f7 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
MACRUM 6:40e873bbc5f7 1222 __regSCTLR = sctlr;
MACRUM 6:40e873bbc5f7 1223 #endif
MACRUM 6:40e873bbc5f7 1224 }
MACRUM 6:40e873bbc5f7 1225
MACRUM 6:40e873bbc5f7 1226 /** \brief Get SCTLR
MACRUM 6:40e873bbc5f7 1227
MACRUM 6:40e873bbc5f7 1228 This function returns the value of the System Control Register.
MACRUM 6:40e873bbc5f7 1229
MACRUM 6:40e873bbc5f7 1230 \return System Control Register value
MACRUM 6:40e873bbc5f7 1231 */
MACRUM 6:40e873bbc5f7 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
MACRUM 6:40e873bbc5f7 1233 #if 1
MACRUM 6:40e873bbc5f7 1234 register uint32_t __regSCTLR;
MACRUM 6:40e873bbc5f7 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
MACRUM 6:40e873bbc5f7 1236 #else
MACRUM 6:40e873bbc5f7 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
MACRUM 6:40e873bbc5f7 1238 #endif
MACRUM 6:40e873bbc5f7 1239 return(__regSCTLR);
MACRUM 6:40e873bbc5f7 1240 }
MACRUM 6:40e873bbc5f7 1241
MACRUM 6:40e873bbc5f7 1242 /** \brief Enable Caches
MACRUM 6:40e873bbc5f7 1243
MACRUM 6:40e873bbc5f7 1244 Enable Caches
MACRUM 6:40e873bbc5f7 1245 */
MACRUM 6:40e873bbc5f7 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
MACRUM 6:40e873bbc5f7 1247 // Set I bit 12 to enable I Cache
MACRUM 6:40e873bbc5f7 1248 // Set C bit 2 to enable D Cache
MACRUM 6:40e873bbc5f7 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
MACRUM 6:40e873bbc5f7 1250 }
MACRUM 6:40e873bbc5f7 1251
MACRUM 6:40e873bbc5f7 1252 /** \brief Disable Caches
MACRUM 6:40e873bbc5f7 1253
MACRUM 6:40e873bbc5f7 1254 Disable Caches
MACRUM 6:40e873bbc5f7 1255 */
MACRUM 6:40e873bbc5f7 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
MACRUM 6:40e873bbc5f7 1257 // Clear I bit 12 to disable I Cache
MACRUM 6:40e873bbc5f7 1258 // Clear C bit 2 to disable D Cache
MACRUM 6:40e873bbc5f7 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
MACRUM 6:40e873bbc5f7 1260 __ISB();
MACRUM 6:40e873bbc5f7 1261 }
MACRUM 6:40e873bbc5f7 1262
MACRUM 6:40e873bbc5f7 1263 /** \brief Enable BTAC
MACRUM 6:40e873bbc5f7 1264
MACRUM 6:40e873bbc5f7 1265 Enable BTAC
MACRUM 6:40e873bbc5f7 1266 */
MACRUM 6:40e873bbc5f7 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
MACRUM 6:40e873bbc5f7 1268 // Set Z bit 11 to enable branch prediction
MACRUM 6:40e873bbc5f7 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
MACRUM 6:40e873bbc5f7 1270 __ISB();
MACRUM 6:40e873bbc5f7 1271 }
MACRUM 6:40e873bbc5f7 1272
MACRUM 6:40e873bbc5f7 1273 /** \brief Disable BTAC
MACRUM 6:40e873bbc5f7 1274
MACRUM 6:40e873bbc5f7 1275 Disable BTAC
MACRUM 6:40e873bbc5f7 1276 */
MACRUM 6:40e873bbc5f7 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
MACRUM 6:40e873bbc5f7 1278 // Clear Z bit 11 to disable branch prediction
MACRUM 6:40e873bbc5f7 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
MACRUM 6:40e873bbc5f7 1280 }
MACRUM 6:40e873bbc5f7 1281
MACRUM 6:40e873bbc5f7 1282
MACRUM 6:40e873bbc5f7 1283 /** \brief Enable MMU
MACRUM 6:40e873bbc5f7 1284
MACRUM 6:40e873bbc5f7 1285 Enable MMU
MACRUM 6:40e873bbc5f7 1286 */
MACRUM 6:40e873bbc5f7 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
MACRUM 6:40e873bbc5f7 1288 // Set M bit 0 to enable the MMU
MACRUM 6:40e873bbc5f7 1289 // Set AFE bit to enable simplified access permissions model
MACRUM 6:40e873bbc5f7 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
MACRUM 6:40e873bbc5f7 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
MACRUM 6:40e873bbc5f7 1292 __ISB();
MACRUM 6:40e873bbc5f7 1293 }
MACRUM 6:40e873bbc5f7 1294
MACRUM 6:40e873bbc5f7 1295 /** \brief Disable MMU
MACRUM 6:40e873bbc5f7 1296
MACRUM 6:40e873bbc5f7 1297 Disable MMU
MACRUM 6:40e873bbc5f7 1298 */
MACRUM 6:40e873bbc5f7 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
MACRUM 6:40e873bbc5f7 1300 // Clear M bit 0 to disable the MMU
MACRUM 6:40e873bbc5f7 1301 __set_SCTLR( __get_SCTLR() & ~1);
MACRUM 6:40e873bbc5f7 1302 __ISB();
MACRUM 6:40e873bbc5f7 1303 }
MACRUM 6:40e873bbc5f7 1304
MACRUM 6:40e873bbc5f7 1305 /******************************** TLB maintenance operations ************************************************/
MACRUM 6:40e873bbc5f7 1306 /** \brief Invalidate the whole tlb
MACRUM 6:40e873bbc5f7 1307
MACRUM 6:40e873bbc5f7 1308 TLBIALL. Invalidate the whole tlb
MACRUM 6:40e873bbc5f7 1309 */
MACRUM 6:40e873bbc5f7 1310
MACRUM 6:40e873bbc5f7 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
MACRUM 6:40e873bbc5f7 1312 #if 1
MACRUM 6:40e873bbc5f7 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
MACRUM 6:40e873bbc5f7 1314 #else
MACRUM 6:40e873bbc5f7 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
MACRUM 6:40e873bbc5f7 1316 __TLBIALL = 0;
MACRUM 6:40e873bbc5f7 1317 #endif
MACRUM 6:40e873bbc5f7 1318 __DSB();
MACRUM 6:40e873bbc5f7 1319 __ISB();
MACRUM 6:40e873bbc5f7 1320 }
MACRUM 6:40e873bbc5f7 1321
MACRUM 6:40e873bbc5f7 1322 /******************************** BTB maintenance operations ************************************************/
MACRUM 6:40e873bbc5f7 1323 /** \brief Invalidate entire branch predictor array
MACRUM 6:40e873bbc5f7 1324
MACRUM 6:40e873bbc5f7 1325 BPIALL. Branch Predictor Invalidate All.
MACRUM 6:40e873bbc5f7 1326 */
MACRUM 6:40e873bbc5f7 1327
MACRUM 6:40e873bbc5f7 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
MACRUM 6:40e873bbc5f7 1329 #if 1
MACRUM 6:40e873bbc5f7 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
MACRUM 6:40e873bbc5f7 1331 #else
MACRUM 6:40e873bbc5f7 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
MACRUM 6:40e873bbc5f7 1333 __BPIALL = 0;
MACRUM 6:40e873bbc5f7 1334 #endif
MACRUM 6:40e873bbc5f7 1335 __DSB(); //ensure completion of the invalidation
MACRUM 6:40e873bbc5f7 1336 __ISB(); //ensure instruction fetch path sees new state
MACRUM 6:40e873bbc5f7 1337 }
MACRUM 6:40e873bbc5f7 1338
MACRUM 6:40e873bbc5f7 1339
MACRUM 6:40e873bbc5f7 1340 /******************************** L1 cache operations ******************************************************/
MACRUM 6:40e873bbc5f7 1341
MACRUM 6:40e873bbc5f7 1342 /** \brief Invalidate the whole I$
MACRUM 6:40e873bbc5f7 1343
MACRUM 6:40e873bbc5f7 1344 ICIALLU. Instruction Cache Invalidate All to PoU
MACRUM 6:40e873bbc5f7 1345 */
MACRUM 6:40e873bbc5f7 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
MACRUM 6:40e873bbc5f7 1347 #if 1
MACRUM 6:40e873bbc5f7 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
MACRUM 6:40e873bbc5f7 1349 #else
MACRUM 6:40e873bbc5f7 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
MACRUM 6:40e873bbc5f7 1351 __ICIALLU = 0;
MACRUM 6:40e873bbc5f7 1352 #endif
MACRUM 6:40e873bbc5f7 1353 __DSB(); //ensure completion of the invalidation
MACRUM 6:40e873bbc5f7 1354 __ISB(); //ensure instruction fetch path sees new I cache state
MACRUM 6:40e873bbc5f7 1355 }
MACRUM 6:40e873bbc5f7 1356
MACRUM 6:40e873bbc5f7 1357 /** \brief Clean D$ by MVA
MACRUM 6:40e873bbc5f7 1358
MACRUM 6:40e873bbc5f7 1359 DCCMVAC. Data cache clean by MVA to PoC
MACRUM 6:40e873bbc5f7 1360 */
MACRUM 6:40e873bbc5f7 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
MACRUM 6:40e873bbc5f7 1362 #if 1
MACRUM 6:40e873bbc5f7 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
MACRUM 6:40e873bbc5f7 1364 #else
MACRUM 6:40e873bbc5f7 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
MACRUM 6:40e873bbc5f7 1366 __DCCMVAC = (uint32_t)va;
MACRUM 6:40e873bbc5f7 1367 #endif
MACRUM 6:40e873bbc5f7 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MACRUM 6:40e873bbc5f7 1369 }
MACRUM 6:40e873bbc5f7 1370
MACRUM 6:40e873bbc5f7 1371 /** \brief Invalidate D$ by MVA
MACRUM 6:40e873bbc5f7 1372
MACRUM 6:40e873bbc5f7 1373 DCIMVAC. Data cache invalidate by MVA to PoC
MACRUM 6:40e873bbc5f7 1374 */
MACRUM 6:40e873bbc5f7 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
MACRUM 6:40e873bbc5f7 1376 #if 1
MACRUM 6:40e873bbc5f7 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
MACRUM 6:40e873bbc5f7 1378 #else
MACRUM 6:40e873bbc5f7 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
MACRUM 6:40e873bbc5f7 1380 __DCIMVAC = (uint32_t)va;
MACRUM 6:40e873bbc5f7 1381 #endif
MACRUM 6:40e873bbc5f7 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MACRUM 6:40e873bbc5f7 1383 }
MACRUM 6:40e873bbc5f7 1384
MACRUM 6:40e873bbc5f7 1385 /** \brief Clean and Invalidate D$ by MVA
MACRUM 6:40e873bbc5f7 1386
MACRUM 6:40e873bbc5f7 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
MACRUM 6:40e873bbc5f7 1388 */
MACRUM 6:40e873bbc5f7 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
MACRUM 6:40e873bbc5f7 1390 #if 1
MACRUM 6:40e873bbc5f7 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
MACRUM 6:40e873bbc5f7 1392 #else
MACRUM 6:40e873bbc5f7 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
MACRUM 6:40e873bbc5f7 1394 __DCCIMVAC = (uint32_t)va;
MACRUM 6:40e873bbc5f7 1395 #endif
MACRUM 6:40e873bbc5f7 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MACRUM 6:40e873bbc5f7 1397 }
MACRUM 6:40e873bbc5f7 1398
MACRUM 6:40e873bbc5f7 1399 /** \brief Clean and Invalidate the entire data or unified cache
MACRUM 6:40e873bbc5f7 1400
MACRUM 6:40e873bbc5f7 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
MACRUM 6:40e873bbc5f7 1402 */
MACRUM 6:40e873bbc5f7 1403 extern void __v7_all_cache(uint32_t op);
MACRUM 6:40e873bbc5f7 1404
MACRUM 6:40e873bbc5f7 1405
MACRUM 6:40e873bbc5f7 1406 /** \brief Invalidate the whole D$
MACRUM 6:40e873bbc5f7 1407
MACRUM 6:40e873bbc5f7 1408 DCISW. Invalidate by Set/Way
MACRUM 6:40e873bbc5f7 1409 */
MACRUM 6:40e873bbc5f7 1410
MACRUM 6:40e873bbc5f7 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
MACRUM 6:40e873bbc5f7 1412 __v7_all_cache(0);
MACRUM 6:40e873bbc5f7 1413 }
MACRUM 6:40e873bbc5f7 1414
MACRUM 6:40e873bbc5f7 1415 /** \brief Clean the whole D$
MACRUM 6:40e873bbc5f7 1416
MACRUM 6:40e873bbc5f7 1417 DCCSW. Clean by Set/Way
MACRUM 6:40e873bbc5f7 1418 */
MACRUM 6:40e873bbc5f7 1419
MACRUM 6:40e873bbc5f7 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
MACRUM 6:40e873bbc5f7 1421 __v7_all_cache(1);
MACRUM 6:40e873bbc5f7 1422 }
MACRUM 6:40e873bbc5f7 1423
MACRUM 6:40e873bbc5f7 1424 /** \brief Clean and invalidate the whole D$
MACRUM 6:40e873bbc5f7 1425
MACRUM 6:40e873bbc5f7 1426 DCCISW. Clean and Invalidate by Set/Way
MACRUM 6:40e873bbc5f7 1427 */
MACRUM 6:40e873bbc5f7 1428
MACRUM 6:40e873bbc5f7 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
MACRUM 6:40e873bbc5f7 1430 __v7_all_cache(2);
MACRUM 6:40e873bbc5f7 1431 }
MACRUM 6:40e873bbc5f7 1432
MACRUM 6:40e873bbc5f7 1433 #include "core_ca_mmu.h"
MACRUM 6:40e873bbc5f7 1434
MACRUM 6:40e873bbc5f7 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
MACRUM 6:40e873bbc5f7 1436
MACRUM 6:40e873bbc5f7 1437 #error TASKING Compiler support not implemented for Cortex-A
MACRUM 6:40e873bbc5f7 1438
MACRUM 6:40e873bbc5f7 1439 #endif
MACRUM 6:40e873bbc5f7 1440
MACRUM 6:40e873bbc5f7 1441 /*@} end of CMSIS_Core_RegAccFunctions */
MACRUM 6:40e873bbc5f7 1442
MACRUM 6:40e873bbc5f7 1443
MACRUM 6:40e873bbc5f7 1444 #endif /* __CORE_CAFUNC_H__ */