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Describes predefine macros for mbed online compiler (armcc)

mbed/TARGET_LPC1114/TARGET_NXP/TARGET_LPC11XX_11CXX/device/bitfields.h@6:40e873bbc5f7, 2017-03-16 (annotated)

Committer:: MACRUM
Date:: Thu Mar 16 21:58:09 2017 +0900
Revision:: 6:40e873bbc5f7

Add licence header info

Who changed what in which revision?

User	Revision	Line number	New contents of line
MACRUM	6:40e873bbc5f7	1	#ifndef MBED_BITFIELDS_H
MACRUM	6:40e873bbc5f7	2	#define MBED_BITFIELDS_H
MACRUM	6:40e873bbc5f7	3
MACRUM	6:40e873bbc5f7	4	//! Massage x for use in bitfield name.
MACRUM	6:40e873bbc5f7	5	#define BFN_PREP(x, name) ( ((x)<<name##_SHIFT) & name##_MASK )
MACRUM	6:40e873bbc5f7	6
MACRUM	6:40e873bbc5f7	7	//! Get the value of bitfield name from y. Equivalent to (var=) y.name
MACRUM	6:40e873bbc5f7	8	#define BFN_GET(y, name) ( ((y) & name##_MASK)>>name##_SHIFT )
MACRUM	6:40e873bbc5f7	9
MACRUM	6:40e873bbc5f7	10	//! Set bitfield name from y to x: y.name= x.
MACRUM	6:40e873bbc5f7	11	#define BFN_SET(y, x, name) (y = ((y)&~name##_MASK) \| BFN_PREP(x,name) )
MACRUM	6:40e873bbc5f7	12
MACRUM	6:40e873bbc5f7	13
MACRUM	6:40e873bbc5f7	14	/* SYSMEMREMAP, address 0x4004 8000 */
MACRUM	6:40e873bbc5f7	15	#define SYSMEMREMAP_MAP_MASK 0x0003 // System memory remap
MACRUM	6:40e873bbc5f7	16	#define SYSMEMREMAP_MAP_SHIFT 0
MACRUM	6:40e873bbc5f7	17
MACRUM	6:40e873bbc5f7	18	/* PRESETCTRL, address 0x4004 8004 */
MACRUM	6:40e873bbc5f7	19	#define PRESETCTRL_SSP0_RST_N (1 << 0) // SPI0 reset control
MACRUM	6:40e873bbc5f7	20	#define PRESETCTRL_I2C_RST_N (1 << 1) // I2C reset control
MACRUM	6:40e873bbc5f7	21	#define PRESETCTRL_SSP1_RST_N (1 << 2) // SPI1 reset control
MACRUM	6:40e873bbc5f7	22	#define PRESETCTRL_CAN_RST_N (1 << 3) // C_CAN reset control. See Section 3.1 for part specific details.
MACRUM	6:40e873bbc5f7	23
MACRUM	6:40e873bbc5f7	24	/* SYSPLLCTRL, address 0x4004 8008 */
MACRUM	6:40e873bbc5f7	25	#define SYSPLLCTRL_MSEL_MASK 0x001F // Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32.
MACRUM	6:40e873bbc5f7	26	#define SYSPLLCTRL_MSEL_SHIFT 0
MACRUM	6:40e873bbc5f7	27	#define SYSPLLCTRL_PSEL_MASK 0x0060 // Post divider ratio P. The division ratio is 2 P.
MACRUM	6:40e873bbc5f7	28	#define SYSPLLCTRL_PSEL_SHIFT 5
MACRUM	6:40e873bbc5f7	29
MACRUM	6:40e873bbc5f7	30	/* SYSPLLSTAT, address 0x4004 800C */
MACRUM	6:40e873bbc5f7	31	#define SYSPLLSTAT_LOCK (1 << 0) // PLL lock status
MACRUM	6:40e873bbc5f7	32
MACRUM	6:40e873bbc5f7	33	/* SYSOSCCTRL, address 0x4004 8020 */
MACRUM	6:40e873bbc5f7	34	#define SYSOSCCTRL_BYPASS (1 << 0) // Bypass system oscillator
MACRUM	6:40e873bbc5f7	35	#define SYSOSCCTRL_FREQRANGE (1 << 1) // Determines frequency range for Low-power oscillator.
MACRUM	6:40e873bbc5f7	36
MACRUM	6:40e873bbc5f7	37	/* WDTOSCCTRL, address 0x4004 8024 */
MACRUM	6:40e873bbc5f7	38	#define WDTOSCCTRL_DIVSEL_MASK 0x001F // Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 (1 + DIVSEL)) 00000: 2 (1 + DIVSEL) = 2 00001: 2 (1 + DIVSEL) = 4 to 11111: 2 (1 + DIVSEL) = 64
MACRUM	6:40e873bbc5f7	39	#define WDTOSCCTRL_DIVSEL_SHIFT 0
MACRUM	6:40e873bbc5f7	40	#define WDTOSCCTRL_FREQSEL_MASK 0x01E0 // Select watchdog oscillator analog output frequency (Fclkana).
MACRUM	6:40e873bbc5f7	41	#define WDTOSCCTRL_FREQSEL_SHIFT 5
MACRUM	6:40e873bbc5f7	42
MACRUM	6:40e873bbc5f7	43	/* IRCCTRL, address 0x4004 8028 */
MACRUM	6:40e873bbc5f7	44	#define IRCCTRL_TRIM_MASK 0x00FF // Trim value
MACRUM	6:40e873bbc5f7	45	#define IRCCTRL_TRIM_SHIFT 0
MACRUM	6:40e873bbc5f7	46
MACRUM	6:40e873bbc5f7	47	/* SYSRSTSTAT, address 0x4004 8030 */
MACRUM	6:40e873bbc5f7	48	#define SYSRSTSTAT_POR (1 << 0) // POR reset status
MACRUM	6:40e873bbc5f7	49	#define SYSRSTSTAT_EXTRST (1 << 1) // Status of the external RESET pin.
MACRUM	6:40e873bbc5f7	50	#define SYSRSTSTAT_WDT (1 << 2) // Status of the Watchdog reset
MACRUM	6:40e873bbc5f7	51	#define SYSRSTSTAT_BOD (1 << 3) // Status of the Brown-out detect reset
MACRUM	6:40e873bbc5f7	52	#define SYSRSTSTAT_SYSRST (1 << 4) // Status of the software system reset
MACRUM	6:40e873bbc5f7	53
MACRUM	6:40e873bbc5f7	54	/* SYSPLLCLKSEL, address 0x4004 8040 */
MACRUM	6:40e873bbc5f7	55	#define SYSPLLCLKSEL_SEL_MASK 0x0003 // System PLL clock source
MACRUM	6:40e873bbc5f7	56	#define SYSPLLCLKSEL_SEL_SHIFT 0
MACRUM	6:40e873bbc5f7	57
MACRUM	6:40e873bbc5f7	58	/* SYSPLLCLKUEN, address 0x4004 8044 */
MACRUM	6:40e873bbc5f7	59	#define SYSPLLCLKUEN_ENA (1 << 0) // Enable system PLL clock source update
MACRUM	6:40e873bbc5f7	60
MACRUM	6:40e873bbc5f7	61	/* MAINCLKSEL, address 0x4004 8070 */
MACRUM	6:40e873bbc5f7	62	#define MAINCLKSEL_SEL_MASK 0x0003 // Clock source for main clock
MACRUM	6:40e873bbc5f7	63	#define MAINCLKSEL_SEL_SHIFT 0
MACRUM	6:40e873bbc5f7	64
MACRUM	6:40e873bbc5f7	65	/* MAINCLKUEN, address 0x4004 8074 */
MACRUM	6:40e873bbc5f7	66	#define MAINCLKUEN_ENA (1 << 0) // Enable main clock source update 0
MACRUM	6:40e873bbc5f7	67
MACRUM	6:40e873bbc5f7	68	/* SYSAHBCLKDIV, address 0x4004 8078 */
MACRUM	6:40e873bbc5f7	69	#define SYSAHBCLKDIV_DIV_MASK 0x00FF // System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
MACRUM	6:40e873bbc5f7	70	#define SYSAHBCLKDIV_DIV_SHIFT 0
MACRUM	6:40e873bbc5f7	71
MACRUM	6:40e873bbc5f7	72	/* SYSAHBCLKCTRL, address 0x4004 8080 */
MACRUM	6:40e873bbc5f7	73	#define SYSAHBCLKCTRL_SYS (1 << 0) // Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only.
MACRUM	6:40e873bbc5f7	74	#define SYSAHBCLKCTRL_ROM (1 << 1) // Enables clock for ROM.
MACRUM	6:40e873bbc5f7	75	#define SYSAHBCLKCTRL_RAM (1 << 2) // Enables clock for RAM.
MACRUM	6:40e873bbc5f7	76	#define SYSAHBCLKCTRL_FLASHREG (1 << 3) // Enables clock for flash register interface.
MACRUM	6:40e873bbc5f7	77	#define SYSAHBCLKCTRL_FLASHARRAY (1 << 4) // Enables clock for flash array access.
MACRUM	6:40e873bbc5f7	78	#define SYSAHBCLKCTRL_I2C (1 << 5) // Enables clock for I2C.
MACRUM	6:40e873bbc5f7	79	#define SYSAHBCLKCTRL_GPIO (1 << 6) // Enables clock for GPIO.
MACRUM	6:40e873bbc5f7	80	#define SYSAHBCLKCTRL_CT16B0 (1 << 7) // Enables clock for 16-bit counter/timer 0.
MACRUM	6:40e873bbc5f7	81	#define SYSAHBCLKCTRL_CT16B1 (1 << 8) // Enables clock for 16-bit counter/timer 1.
MACRUM	6:40e873bbc5f7	82	#define SYSAHBCLKCTRL_CT32B0 (1 << 9) // Enables clock for 32-bit counter/timer 0.
MACRUM	6:40e873bbc5f7	83	#define SYSAHBCLKCTRL_CT32B1 (1 << 10) // Enables clock for 32-bit counter/timer 1.
MACRUM	6:40e873bbc5f7	84	#define SYSAHBCLKCTRL_SSP0 (1 << 11) // Enables clock for SPI0.
MACRUM	6:40e873bbc5f7	85	#define SYSAHBCLKCTRL_UART (1 << 12) // Enables clock for UART. See Section 3.1 for part specific details.
MACRUM	6:40e873bbc5f7	86	#define SYSAHBCLKCTRL_ADC (1 << 13) // Enables clock for ADC.
MACRUM	6:40e873bbc5f7	87	#define SYSAHBCLKCTRL_WDT (1 << 15) // Enables clock for WDT.
MACRUM	6:40e873bbc5f7	88	#define SYSAHBCLKCTRL_IOCON (1 << 16) // Enables clock for I/O configuration block.
MACRUM	6:40e873bbc5f7	89	#define SYSAHBCLKCTRL_CAN (1 << 17) // Enables clock for C_CAN. See Section 3.1 for part specific details.
MACRUM	6:40e873bbc5f7	90	#define SYSAHBCLKCTRL_SSP1 (1 << 18) // Enables clock for SPI1.
MACRUM	6:40e873bbc5f7	91
MACRUM	6:40e873bbc5f7	92	/* SSP0CLKDIV, address 0x4004 8094 */
MACRUM	6:40e873bbc5f7	93	#define SSP0CLKDIV_DIV_MASK 0x00FF // SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255.
MACRUM	6:40e873bbc5f7	94	#define SSP0CLKDIV_DIV_SHIFT 0
MACRUM	6:40e873bbc5f7	95
MACRUM	6:40e873bbc5f7	96	/* UARTCLKDIV, address 0x4004 8098 */
MACRUM	6:40e873bbc5f7	97	#define UARTCLKDIV_DIV_MASK 0x00FF // UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255.
MACRUM	6:40e873bbc5f7	98	#define UARTCLKDIV_DIV_SHIFT 0
MACRUM	6:40e873bbc5f7	99
MACRUM	6:40e873bbc5f7	100	/* SSP1CLKDIV, address 0x4004 809C */
MACRUM	6:40e873bbc5f7	101	#define SSP1CLKDIV_DIV_MASK 0x00FF // SPI1_PCLK clock divider values 0: Disable SPI1_PCLK. 1: Divide by 1. to 255: Divide by 255.
MACRUM	6:40e873bbc5f7	102	#define SSP1CLKDIV_DIV_SHIFT 0
MACRUM	6:40e873bbc5f7	103
MACRUM	6:40e873bbc5f7	104	/* WDTCLKSEL, address 0x4004 80D0 */
MACRUM	6:40e873bbc5f7	105	#define WDTCLKSEL_SEL_MASK 0x0003 // WDT clock source
MACRUM	6:40e873bbc5f7	106	#define WDTCLKSEL_SEL_SHIFT 0
MACRUM	6:40e873bbc5f7	107
MACRUM	6:40e873bbc5f7	108	/* WDTCLKUEN, address 0x4004 80D4 */
MACRUM	6:40e873bbc5f7	109	#define WDTCLKUEN_ENA (1 << 0) // Enable WDT clock source update
MACRUM	6:40e873bbc5f7	110
MACRUM	6:40e873bbc5f7	111	/* WDTCLKDIV, address 0x4004 80D8 */
MACRUM	6:40e873bbc5f7	112	#define WDTCLKDIV_DIV_MASK 0x00FF // WDT clock divider values 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255.
MACRUM	6:40e873bbc5f7	113	#define WDTCLKDIV_DIV_SHIFT 0
MACRUM	6:40e873bbc5f7	114
MACRUM	6:40e873bbc5f7	115	/* CLKOUTCLKSEL, address 0x4004 80E0 */
MACRUM	6:40e873bbc5f7	116	#define CLKOUTCLKSEL_SEL_MASK 0x0003 // CLKOUT clock source
MACRUM	6:40e873bbc5f7	117	#define CLKOUTCLKSEL_SEL_SHIFT 0
MACRUM	6:40e873bbc5f7	118
MACRUM	6:40e873bbc5f7	119	/* CLKOUTUEN, address 0x4004 80E4 */
MACRUM	6:40e873bbc5f7	120	#define CLKOUTUEN_ENA (1 << 0) // Enable CLKOUT clock source update 0
MACRUM	6:40e873bbc5f7	121
MACRUM	6:40e873bbc5f7	122	/* CLKOUTCLKDIV, address 0x4004 80E8 */
MACRUM	6:40e873bbc5f7	123	#define CLKOUTCLKDIV_DIV_MASK 0x00FF // Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255.
MACRUM	6:40e873bbc5f7	124	#define CLKOUTCLKDIV_DIV_SHIFT 0
MACRUM	6:40e873bbc5f7	125
MACRUM	6:40e873bbc5f7	126	/* PIOPORCAP0, address 0x4004 8100 */
MACRUM	6:40e873bbc5f7	127	#define PIOPORCAP0_CAPPIO0_N_MASK 0x0FFF // Raw reset status input PIO0_n: PIO0_11 to PIO0_0
MACRUM	6:40e873bbc5f7	128	#define PIOPORCAP0_CAPPIO0_N_SHIFT 0
MACRUM	6:40e873bbc5f7	129	#define PIOPORCAP0_CAPPIO1_N_MASK 0xFFF000 // Raw reset status input PIO1_n: PIO1_11 to PIO1_0
MACRUM	6:40e873bbc5f7	130	#define PIOPORCAP0_CAPPIO1_N_SHIFT 12
MACRUM	6:40e873bbc5f7	131	#define PIOPORCAP0_CAPPIO2_N_MASK 0xFF000000 // Raw reset status input PIO2_n: PIO2_7 to PIO2_0
MACRUM	6:40e873bbc5f7	132	#define PIOPORCAP0_CAPPIO2_N_SHIFT 24
MACRUM	6:40e873bbc5f7	133
MACRUM	6:40e873bbc5f7	134	/* PIOPORCAP1, address 0x4004 8104 */
MACRUM	6:40e873bbc5f7	135	#define PIOPORCAP1_CAPPIO2_8 (1 << 0) // Raw reset status input PIO2_8
MACRUM	6:40e873bbc5f7	136	#define PIOPORCAP1_CAPPIO2_9 (1 << 1) // Raw reset status input PIO2_9
MACRUM	6:40e873bbc5f7	137	#define PIOPORCAP1_CAPPIO2_10 (1 << 2) // Raw reset status input PIO2_10
MACRUM	6:40e873bbc5f7	138	#define PIOPORCAP1_CAPPIO2_11 (1 << 3) // Raw reset status input PIO2_11
MACRUM	6:40e873bbc5f7	139	#define PIOPORCAP1_CAPPIO3_0 (1 << 4) // Raw reset status input PIO3_0
MACRUM	6:40e873bbc5f7	140	#define PIOPORCAP1_CAPPIO3_1 (1 << 5) // Raw reset status input PIO3_1
MACRUM	6:40e873bbc5f7	141	#define PIOPORCAP1_CAPPIO3_2 (1 << 6) // Raw reset status input PIO3_2
MACRUM	6:40e873bbc5f7	142	#define PIOPORCAP1_CAPPIO3_3 (1 << 7) // Raw reset status input PIO3_3
MACRUM	6:40e873bbc5f7	143	#define PIOPORCAP1_CAPPIO3_4 (1 << 8) // Raw reset status input PIO3_4
MACRUM	6:40e873bbc5f7	144	#define PIOPORCAP1_CAPPIO3_5 (1 << 9) // Raw reset status input PIO3_5
MACRUM	6:40e873bbc5f7	145
MACRUM	6:40e873bbc5f7	146	/* BODCTRL, address 0x4004 8150 */
MACRUM	6:40e873bbc5f7	147	#define BODCTRL_BODRSTLEV_MASK 0x0003 // BOD reset level
MACRUM	6:40e873bbc5f7	148	#define BODCTRL_BODRSTLEV_SHIFT 0
MACRUM	6:40e873bbc5f7	149	#define BODCTRL_BODINTVAL_MASK 0x000C // BOD interrupt level
MACRUM	6:40e873bbc5f7	150	#define BODCTRL_BODINTVAL_SHIFT 2
MACRUM	6:40e873bbc5f7	151	#define BODCTRL_BODRSTENA (1 << 4) // BOD reset enable
MACRUM	6:40e873bbc5f7	152
MACRUM	6:40e873bbc5f7	153	/* SYSTCKCAL, address 0x4004 8154 */
MACRUM	6:40e873bbc5f7	154	#define SYSTCKCAL_CAL_MASK 0x3FFFFFF // System tick timer calibration value
MACRUM	6:40e873bbc5f7	155	#define SYSTCKCAL_CAL_SHIFT 0
MACRUM	6:40e873bbc5f7	156
MACRUM	6:40e873bbc5f7	157	/* NMISRC, address 0x4004 8174 */
MACRUM	6:40e873bbc5f7	158	#define NMISRC_IRQNO_MASK 0x001F // The IRQ number of the interrupt that acts as the Non-Maskable Interrupt 0 (NMI) if bit 31 in this register is 1. See Table 54 for the list of interrupt sources and their IRQ numbers.
MACRUM	6:40e873bbc5f7	159	#define NMISRC_IRQNO_SHIFT 0
MACRUM	6:40e873bbc5f7	160	#define NMISRC_NMIEN (1 << 31) // Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.
MACRUM	6:40e873bbc5f7	161
MACRUM	6:40e873bbc5f7	162	/* STARTAPRP0, address 0x4004 8200 */
MACRUM	6:40e873bbc5f7	163	#define STARTAPRP0_APRPIO0_N_MASK 0x0FFF // Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge
MACRUM	6:40e873bbc5f7	164	#define STARTAPRP0_APRPIO0_N_SHIFT 0
MACRUM	6:40e873bbc5f7	165	#define STARTAPRP0_APRPIO1_0 (1 << 12) // Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge Reserved. Do not write a 1 to reserved bits in this register.
MACRUM	6:40e873bbc5f7	166
MACRUM	6:40e873bbc5f7	167	/* STARTERP0, address 0x4004 8204 */
MACRUM	6:40e873bbc5f7	168	#define STARTERP0_ERPIO0_N_MASK 0x0FFF // Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled
MACRUM	6:40e873bbc5f7	169	#define STARTERP0_ERPIO0_N_SHIFT 0
MACRUM	6:40e873bbc5f7	170	#define STARTERP0_ERPIO1_0 (1 << 12) // Enable start signal for start logic input PIO1_0 0 = Disabled 1 = Enabled Reserved. Do not write a 1 to reserved bits in this register.
MACRUM	6:40e873bbc5f7	171
MACRUM	6:40e873bbc5f7	172	/* STARTRSRP0CLR, address 0x4004 8208 */
MACRUM	6:40e873bbc5f7	173	#define STARTRSRP0CLR_RSRPIO0_N_MASK 0x0FFF // Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.
MACRUM	6:40e873bbc5f7	174	#define STARTRSRP0CLR_RSRPIO0_N_SHIFT 0
MACRUM	6:40e873bbc5f7	175	#define STARTRSRP0CLR_RSRPIO1_0 (1 << 12) // Start signal reset for start logic input PIO1_0 0 = Do nothing. 1 = Writing 1 resets the start signal.
MACRUM	6:40e873bbc5f7	176
MACRUM	6:40e873bbc5f7	177	/* STARTSRP0, address 0x4004 820C */
MACRUM	6:40e873bbc5f7	178	#define STARTSRP0_SRPIO0_N_MASK 0x0FFF // Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.
MACRUM	6:40e873bbc5f7	179	#define STARTSRP0_SRPIO0_N_SHIFT 0
MACRUM	6:40e873bbc5f7	180	#define STARTSRP0_SRPIO1_0 (1 << 12) // Start signal status for start logic input PIO1_0 0 = No start signal received. 1 = Start signal pending.
MACRUM	6:40e873bbc5f7	181
MACRUM	6:40e873bbc5f7	182	/* PDSLEEPCFG, address 0x4004 8230 */
MACRUM	6:40e873bbc5f7	183	#define PDSLEEPCFG_BOD_PD (1 << 3) // BOD power-down control in Deep-sleep mode, see Table 40.
MACRUM	6:40e873bbc5f7	184	#define PDSLEEPCFG_WDTOSC_PD (1 << 6) // Watchdog oscillator power control in Deep-sleep mode, see Table 40.
MACRUM	6:40e873bbc5f7	185
MACRUM	6:40e873bbc5f7	186	/* PDAWAKECFG, address 0x4004 8234 */
MACRUM	6:40e873bbc5f7	187	#define PDAWAKECFG_IRCOUT_PD (1 << 0) // IRC oscillator output wake-up configuration
MACRUM	6:40e873bbc5f7	188	#define PDAWAKECFG_IRC_PD (1 << 1) // IRC oscillator power-down wake-up configuration
MACRUM	6:40e873bbc5f7	189	#define PDAWAKECFG_FLASH_PD (1 << 2) // Flash wake-up configuration
MACRUM	6:40e873bbc5f7	190	#define PDAWAKECFG_BOD_PD (1 << 3) // BOD wake-up configuration
MACRUM	6:40e873bbc5f7	191	#define PDAWAKECFG_ADC_PD (1 << 4) // ADC wake-up configuration
MACRUM	6:40e873bbc5f7	192	#define PDAWAKECFG_SYSOSC_PD (1 << 5) // System oscillator wake-up configuration
MACRUM	6:40e873bbc5f7	193	#define PDAWAKECFG_WDTOSC_PD (1 << 6) // Watchdog oscillator wake-up configuration
MACRUM	6:40e873bbc5f7	194	#define PDAWAKECFG_SYSPLL_PD (1 << 7) // System PLL wake-up configuration
MACRUM	6:40e873bbc5f7	195
MACRUM	6:40e873bbc5f7	196	/* PDRUNCFG, address 0x4004 8238 */
MACRUM	6:40e873bbc5f7	197	#define PDRUNCFG_IRCOUT_PD (1 << 0) // IRC oscillator output power-down
MACRUM	6:40e873bbc5f7	198	#define PDRUNCFG_IRC_PD (1 << 1) // IRC oscillator power-down
MACRUM	6:40e873bbc5f7	199	#define PDRUNCFG_FLASH_PD (1 << 2) // Flash power-down
MACRUM	6:40e873bbc5f7	200	#define PDRUNCFG_BOD_PD (1 << 3) // BOD power-down
MACRUM	6:40e873bbc5f7	201	#define PDRUNCFG_ADC_PD (1 << 4) // ADC power-down
MACRUM	6:40e873bbc5f7	202	#define PDRUNCFG_SYSOSC_PD (1 << 5) // System oscillator power-down
MACRUM	6:40e873bbc5f7	203	#define PDRUNCFG_WDTOSC_PD (1 << 6) // Watchdog oscillator power-down
MACRUM	6:40e873bbc5f7	204	#define PDRUNCFG_SYSPLL_PD (1 << 7) // System PLL power-down
MACRUM	6:40e873bbc5f7	205
MACRUM	6:40e873bbc5f7	206	/* DEVICE_ID, address 0x4004 83F4 */
MACRUM	6:40e873bbc5f7	207	#define DEVICE_ID_DEVICEID_MASK 0xFFFFFFFF // Part ID numbers for LPC111x/LPC11Cxx parts
MACRUM	6:40e873bbc5f7	208	#define DEVICE_ID_DEVICEID_SHIFT 0
MACRUM	6:40e873bbc5f7	209
MACRUM	6:40e873bbc5f7	210	/* FLASHCFG, address 0x4003 C010 */
MACRUM	6:40e873bbc5f7	211	#define FLASHCFG_FLASHTIM_MASK 0x0003 // Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
MACRUM	6:40e873bbc5f7	212	#define FLASHCFG_FLASHTIM_SHIFT 0
MACRUM	6:40e873bbc5f7	213
MACRUM	6:40e873bbc5f7	214	/* PCON, address 0x4003 8000 */
MACRUM	6:40e873bbc5f7	215	#define PCON_DPDEN (1 << 1) // Deep power-down mode enable
MACRUM	6:40e873bbc5f7	216	#define PCON_SLEEPFLAG (1 << 8) // Sleep mode flag
MACRUM	6:40e873bbc5f7	217	#define PCON_DPDFLAG (1 << 11) // Deep power-down flag
MACRUM	6:40e873bbc5f7	218
MACRUM	6:40e873bbc5f7	219	/* GPREG0 - GPREG3, address 0x4003 8004 to 0x4003 8010 */
MACRUM	6:40e873bbc5f7	220	#define GPREGn_GPDATA_MASK 0xFFFFFFFF // Data retained during Deep power-down mode.
MACRUM	6:40e873bbc5f7	221	#define GPREGn_GPDATA_SHIFT 0
MACRUM	6:40e873bbc5f7	222
MACRUM	6:40e873bbc5f7	223	/* GPREG4, address 0x4003 8014 */
MACRUM	6:40e873bbc5f7	224	#define GPREG4_WAKEUPHYS (1 << 10) // WAKEUP pin hysteresis enable
MACRUM	6:40e873bbc5f7	225	#define GPREG4_GPDATA_MASK 0xFFFFF800 // Data retained during Deep power-down mode.
MACRUM	6:40e873bbc5f7	226	#define GPREG4_GPDATA_SHIFT 11
MACRUM	6:40e873bbc5f7	227
MACRUM	6:40e873bbc5f7	228	/* IOCON_PIO2_6, address 0x4004 4000 */
MACRUM	6:40e873bbc5f7	229	#define IOCON_PIO2_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	230	#define IOCON_PIO2_6_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	231	#define IOCON_PIO2_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	232	#define IOCON_PIO2_6_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	233	#define IOCON_PIO2_6_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	234	#define IOCON_PIO2_6_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	235
MACRUM	6:40e873bbc5f7	236	/* IOCON_PIO2_0, address 0x4004 4008 */
MACRUM	6:40e873bbc5f7	237	#define IOCON_PIO2_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	238	#define IOCON_PIO2_0_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	239	#define IOCON_PIO2_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	240	#define IOCON_PIO2_0_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	241	#define IOCON_PIO2_0_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	242	#define IOCON_PIO2_0_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	243
MACRUM	6:40e873bbc5f7	244	/* IOCON_RESET_PIO0_0, address 0x4004 400C */
MACRUM	6:40e873bbc5f7	245	#define IOCON_RESET_PIO0_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	246	#define IOCON_RESET_PIO0_0_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	247	#define IOCON_RESET_PIO0_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	248	#define IOCON_RESET_PIO0_0_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	249	#define IOCON_RESET_PIO0_0_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	250	#define IOCON_RESET_PIO0_0_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	251
MACRUM	6:40e873bbc5f7	252	/* IOCON_PIO0_1, address 0x4004 4010 */
MACRUM	6:40e873bbc5f7	253	#define IOCON_PIO0_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	254	#define IOCON_PIO0_1_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	255	#define IOCON_PIO0_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	256	#define IOCON_PIO0_1_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	257	#define IOCON_PIO0_1_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	258	#define IOCON_PIO0_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	259
MACRUM	6:40e873bbc5f7	260	/* IOCON_PIO1_8, address 0x4004 4014 */
MACRUM	6:40e873bbc5f7	261	#define IOCON_PIO1_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	262	#define IOCON_PIO1_8_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	263	#define IOCON_PIO1_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	264	#define IOCON_PIO1_8_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	265	#define IOCON_PIO1_8_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	266	#define IOCON_PIO1_8_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	267
MACRUM	6:40e873bbc5f7	268	/* IOCON_PIO0_2, address 0x4004 401C */
MACRUM	6:40e873bbc5f7	269	#define IOCON_PIO0_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	270	#define IOCON_PIO0_2_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	271	#define IOCON_PIO0_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	272	#define IOCON_PIO0_2_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	273	#define IOCON_PIO0_2_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	274	#define IOCON_PIO0_2_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	275
MACRUM	6:40e873bbc5f7	276	/* IOCON_PIO2_7, address 0x4004 4020 */
MACRUM	6:40e873bbc5f7	277	#define IOCON_PIO2_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	278	#define IOCON_PIO2_7_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	279	#define IOCON_PIO2_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	280	#define IOCON_PIO2_7_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	281	#define IOCON_PIO2_7_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	282	#define IOCON_PIO2_7_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	283
MACRUM	6:40e873bbc5f7	284	/* IOCON_PIO2_8, address 0x4004 4024 */
MACRUM	6:40e873bbc5f7	285	#define IOCON_PIO2_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	286	#define IOCON_PIO2_8_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	287	#define IOCON_PIO2_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	288	#define IOCON_PIO2_8_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	289	#define IOCON_PIO2_8_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	290	#define IOCON_PIO2_8_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	291
MACRUM	6:40e873bbc5f7	292	/* IOCON_PIO2_1, address 0x4004 4028 */
MACRUM	6:40e873bbc5f7	293	#define IOCON_PIO2_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	294	#define IOCON_PIO2_1_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	295	#define IOCON_PIO2_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	296	#define IOCON_PIO2_1_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	297	#define IOCON_PIO2_1_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	298	#define IOCON_PIO2_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	299
MACRUM	6:40e873bbc5f7	300	/* IOCON_PIO0_3, address 0x4004 402C */
MACRUM	6:40e873bbc5f7	301	#define IOCON_PIO0_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	302	#define IOCON_PIO0_3_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	303	#define IOCON_PIO0_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	304	#define IOCON_PIO0_3_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	305	#define IOCON_PIO0_3_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	306	#define IOCON_PIO0_3_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	307
MACRUM	6:40e873bbc5f7	308	/* IOCON_PIO0_4, address 0x4004 4030 */
MACRUM	6:40e873bbc5f7	309	#define IOCON_PIO0_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	310	#define IOCON_PIO0_4_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	311	#define IOCON_PIO0_4_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, 00 default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
MACRUM	6:40e873bbc5f7	312	#define IOCON_PIO0_4_I2CMODE_SHIFT 8
MACRUM	6:40e873bbc5f7	313
MACRUM	6:40e873bbc5f7	314	/* IOCON_PIO0_5, address 0x4004 4034 */
MACRUM	6:40e873bbc5f7	315	#define IOCON_PIO0_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	316	#define IOCON_PIO0_5_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	317	#define IOCON_PIO0_5_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
MACRUM	6:40e873bbc5f7	318	#define IOCON_PIO0_5_I2CMODE_SHIFT 8
MACRUM	6:40e873bbc5f7	319
MACRUM	6:40e873bbc5f7	320	/* IOCON_PIO1_9, address 0x4004 4038 */
MACRUM	6:40e873bbc5f7	321	#define IOCON_PIO1_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	322	#define IOCON_PIO1_9_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	323	#define IOCON_PIO1_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	324	#define IOCON_PIO1_9_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	325	#define IOCON_PIO1_9_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	326	#define IOCON_PIO1_9_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	327
MACRUM	6:40e873bbc5f7	328	/* IOCON_PIO3_4, address 0x4004 403C */
MACRUM	6:40e873bbc5f7	329	#define IOCON_PIO3_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	330	#define IOCON_PIO3_4_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	331	#define IOCON_PIO3_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	332	#define IOCON_PIO3_4_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	333	#define IOCON_PIO3_4_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	334	#define IOCON_PIO3_4_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	335
MACRUM	6:40e873bbc5f7	336	/* IOCON_PIO2_4, address 0x4004 4040 */
MACRUM	6:40e873bbc5f7	337	#define IOCON_PIO2_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	338	#define IOCON_PIO2_4_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	339	#define IOCON_PIO2_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	340	#define IOCON_PIO2_4_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	341	#define IOCON_PIO2_4_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	342	#define IOCON_PIO2_4_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	343
MACRUM	6:40e873bbc5f7	344	/* IOCON_PIO2_5, address 0x4004 4044 */
MACRUM	6:40e873bbc5f7	345	#define IOCON_PIO2_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	346	#define IOCON_PIO2_5_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	347	#define IOCON_PIO2_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	348	#define IOCON_PIO2_5_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	349	#define IOCON_PIO2_5_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	350	#define IOCON_PIO2_5_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	351
MACRUM	6:40e873bbc5f7	352	/* IOCON_PIO3_5, address 0x4004 4048 */
MACRUM	6:40e873bbc5f7	353	#define IOCON_PIO3_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	354	#define IOCON_PIO3_5_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	355	#define IOCON_PIO3_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	356	#define IOCON_PIO3_5_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	357	#define IOCON_PIO3_5_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	358	#define IOCON_PIO3_5_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	359
MACRUM	6:40e873bbc5f7	360	/* IOCON_PIO0_6, address 0x4004 404C */
MACRUM	6:40e873bbc5f7	361	#define IOCON_PIO0_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	362	#define IOCON_PIO0_6_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	363	#define IOCON_PIO0_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	364	#define IOCON_PIO0_6_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	365	#define IOCON_PIO0_6_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	366	#define IOCON_PIO0_6_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	367
MACRUM	6:40e873bbc5f7	368	/* IOCON_PIO0_7, address 0x4004 4050 */
MACRUM	6:40e873bbc5f7	369	#define IOCON_PIO0_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	370	#define IOCON_PIO0_7_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	371	#define IOCON_PIO0_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	372	#define IOCON_PIO0_7_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	373	#define IOCON_PIO0_7_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	374	#define IOCON_PIO0_7_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	375
MACRUM	6:40e873bbc5f7	376	/* IOCON_PIO2_9, address 0x4004 4054 */
MACRUM	6:40e873bbc5f7	377	#define IOCON_PIO2_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	378	#define IOCON_PIO2_9_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	379	#define IOCON_PIO2_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	380	#define IOCON_PIO2_9_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	381	#define IOCON_PIO2_9_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	382	#define IOCON_PIO2_9_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	383
MACRUM	6:40e873bbc5f7	384	/* IOCON_PIO2_10, address 0x4004 4058 */
MACRUM	6:40e873bbc5f7	385	#define IOCON_PIO2_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	386	#define IOCON_PIO2_10_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	387	#define IOCON_PIO2_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	388	#define IOCON_PIO2_10_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	389	#define IOCON_PIO2_10_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	390	#define IOCON_PIO2_10_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	391
MACRUM	6:40e873bbc5f7	392	/* IOCON_PIO2_2, address 0x4004 405C */
MACRUM	6:40e873bbc5f7	393	#define IOCON_PIO2_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	394	#define IOCON_PIO2_2_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	395	#define IOCON_PIO2_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	396	#define IOCON_PIO2_2_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	397	#define IOCON_PIO2_2_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	398	#define IOCON_PIO2_2_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	399
MACRUM	6:40e873bbc5f7	400	/* IOCON_PIO0_8, address 0x4004 4060 */
MACRUM	6:40e873bbc5f7	401	#define IOCON_PIO0_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	402	#define IOCON_PIO0_8_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	403	#define IOCON_PIO0_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	404	#define IOCON_PIO0_8_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	405	#define IOCON_PIO0_8_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	406	#define IOCON_PIO0_8_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	407
MACRUM	6:40e873bbc5f7	408	/* IOCON_PIO0_9, address 0x4004 4064 */
MACRUM	6:40e873bbc5f7	409	#define IOCON_PIO0_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	410	#define IOCON_PIO0_9_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	411	#define IOCON_PIO0_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	412	#define IOCON_PIO0_9_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	413	#define IOCON_PIO0_9_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	414	#define IOCON_PIO0_9_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	415
MACRUM	6:40e873bbc5f7	416	/* IOCON_SWCLK_PIO0_10, address 0x4004 4068 */
MACRUM	6:40e873bbc5f7	417	#define IOCON_SWCLK_PIO0_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	418	#define IOCON_SWCLK_PIO0_10_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	419	#define IOCON_SWCLK_PIO0_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	420	#define IOCON_SWCLK_PIO0_10_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	421	#define IOCON_SWCLK_PIO0_10_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	422	#define IOCON_SWCLK_PIO0_10_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	423
MACRUM	6:40e873bbc5f7	424	/* IOCON_PIO1_10, address 0x4004 406C */
MACRUM	6:40e873bbc5f7	425	#define IOCON_PIO1_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	426	#define IOCON_PIO1_10_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	427	#define IOCON_PIO1_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	428	#define IOCON_PIO1_10_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	429	#define IOCON_PIO1_10_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	430	#define IOCON_PIO1_10_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	431	#define IOCON_PIO1_10_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	432
MACRUM	6:40e873bbc5f7	433	/* IOCON_PIO2_11, address 0x4004 4070 */
MACRUM	6:40e873bbc5f7	434	#define IOCON_PIO2_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	435	#define IOCON_PIO2_11_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	436	#define IOCON_PIO2_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	437	#define IOCON_PIO2_11_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	438	#define IOCON_PIO2_11_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	439	#define IOCON_PIO2_11_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	440
MACRUM	6:40e873bbc5f7	441	/* IOCON_R_PIO0_11, address 0x4004 4074 */
MACRUM	6:40e873bbc5f7	442	#define IOCON_R_PIO0_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	443	#define IOCON_R_PIO0_11_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	444	#define IOCON_R_PIO0_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	445	#define IOCON_R_PIO0_11_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	446	#define IOCON_R_PIO0_11_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	447	#define IOCON_R_PIO0_11_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	448	#define IOCON_R_PIO0_11_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	449
MACRUM	6:40e873bbc5f7	450	/* IOCON_R_PIO1_0, address 0x4004 4078 */
MACRUM	6:40e873bbc5f7	451	#define IOCON_R_PIO1_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	452	#define IOCON_R_PIO1_0_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	453	#define IOCON_R_PIO1_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	454	#define IOCON_R_PIO1_0_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	455	#define IOCON_R_PIO1_0_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	456	#define IOCON_R_PIO1_0_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	457	#define IOCON_R_PIO1_0_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	458
MACRUM	6:40e873bbc5f7	459	/* IOCON_R_PIO1_1, address 0x4004 407C */
MACRUM	6:40e873bbc5f7	460	#define IOCON_R_PIO1_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	461	#define IOCON_R_PIO1_1_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	462	#define IOCON_R_PIO1_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	463	#define IOCON_R_PIO1_1_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	464	#define IOCON_R_PIO1_1_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	465	#define IOCON_R_PIO1_1_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	466	#define IOCON_R_PIO1_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	467
MACRUM	6:40e873bbc5f7	468	/* IOCON_R_PIO1_2, address 0x4004 4080 */
MACRUM	6:40e873bbc5f7	469	#define IOCON_R_PIO1_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	470	#define IOCON_R_PIO1_2_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	471	#define IOCON_R_PIO1_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	472	#define IOCON_R_PIO1_2_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	473	#define IOCON_R_PIO1_2_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	474	#define IOCON_R_PIO1_2_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	475	#define IOCON_R_PIO1_2_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	476
MACRUM	6:40e873bbc5f7	477	/* IOCON_PIO3_0, address 0x4004 4084 */
MACRUM	6:40e873bbc5f7	478	#define IOCON_PIO3_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	479	#define IOCON_PIO3_0_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	480	#define IOCON_PIO3_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	481	#define IOCON_PIO3_0_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	482	#define IOCON_PIO3_0_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	483	#define IOCON_PIO3_0_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	484
MACRUM	6:40e873bbc5f7	485	/* IOCON_PIO3_1, address 0x4004 4088 */
MACRUM	6:40e873bbc5f7	486	#define IOCON_PIO3_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	487	#define IOCON_PIO3_1_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	488	#define IOCON_PIO3_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	489	#define IOCON_PIO3_1_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	490	#define IOCON_PIO3_1_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	491	#define IOCON_PIO3_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	492
MACRUM	6:40e873bbc5f7	493	/* IOCON_PIO2_3, address 0x4004 408C */
MACRUM	6:40e873bbc5f7	494	#define IOCON_PIO2_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	495	#define IOCON_PIO2_3_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	496	#define IOCON_PIO2_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	497	#define IOCON_PIO2_3_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	498	#define IOCON_PIO2_3_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	499	#define IOCON_PIO2_3_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	500
MACRUM	6:40e873bbc5f7	501	/* IOCON_SWDIO_PIO1_3, address 0x4004 4090 */
MACRUM	6:40e873bbc5f7	502	#define IOCON_SWDIO_PIO1_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	503	#define IOCON_SWDIO_PIO1_3_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	504	#define IOCON_SWDIO_PIO1_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	505	#define IOCON_SWDIO_PIO1_3_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	506	#define IOCON_SWDIO_PIO1_3_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	507	#define IOCON_SWDIO_PIO1_3_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	508	#define IOCON_SWDIO_PIO1_3_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	509
MACRUM	6:40e873bbc5f7	510	/* IOCON_PIO1_4, address 0x4004 4094 */
MACRUM	6:40e873bbc5f7	511	#define IOCON_PIO1_4_FUNC_MASK 0x0007 // Selects pin function. This pin functions as WAKEUP pin if the 000 LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.
MACRUM	6:40e873bbc5f7	512	#define IOCON_PIO1_4_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	513	#define IOCON_PIO1_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	514	#define IOCON_PIO1_4_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	515	#define IOCON_PIO1_4_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	516	#define IOCON_PIO1_4_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	517	#define IOCON_PIO1_4_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	518
MACRUM	6:40e873bbc5f7	519	/* IOCON_PIO1_11, address 0x4004 4098 */
MACRUM	6:40e873bbc5f7	520	#define IOCON_PIO1_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	521	#define IOCON_PIO1_11_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	522	#define IOCON_PIO1_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	523	#define IOCON_PIO1_11_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	524	#define IOCON_PIO1_11_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	525	#define IOCON_PIO1_11_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	526	#define IOCON_PIO1_11_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	527
MACRUM	6:40e873bbc5f7	528	/* IOCON_PIO3_2, address 0x4004 409C */
MACRUM	6:40e873bbc5f7	529	#define IOCON_PIO3_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	530	#define IOCON_PIO3_2_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	531	#define IOCON_PIO3_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	532	#define IOCON_PIO3_2_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	533	#define IOCON_PIO3_2_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	534	#define IOCON_PIO3_2_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	535
MACRUM	6:40e873bbc5f7	536	/* IOCON_PIO1_5, address 0x4004 40A0 */
MACRUM	6:40e873bbc5f7	537	#define IOCON_PIO1_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	538	#define IOCON_PIO1_5_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	539	#define IOCON_PIO1_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	540	#define IOCON_PIO1_5_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	541	#define IOCON_PIO1_5_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	542	#define IOCON_PIO1_5_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	543
MACRUM	6:40e873bbc5f7	544	/* IOCON_PIO1_6, address 0x4004 40A4 */
MACRUM	6:40e873bbc5f7	545	#define IOCON_PIO1_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	546	#define IOCON_PIO1_6_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	547	#define IOCON_PIO1_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	548	#define IOCON_PIO1_6_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	549	#define IOCON_PIO1_6_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	550	#define IOCON_PIO1_6_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	551
MACRUM	6:40e873bbc5f7	552	/* IOCON_PIO1_7, address 0x4004 40A8 */
MACRUM	6:40e873bbc5f7	553	#define IOCON_PIO1_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	554	#define IOCON_PIO1_7_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	555	#define IOCON_PIO1_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	556	#define IOCON_PIO1_7_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	557	#define IOCON_PIO1_7_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	558	#define IOCON_PIO1_7_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	559
MACRUM	6:40e873bbc5f7	560	/* IOCON_PIO3_3, address 0x4004 40AC */
MACRUM	6:40e873bbc5f7	561	#define IOCON_PIO3_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	562	#define IOCON_PIO3_3_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	563	#define IOCON_PIO3_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	564	#define IOCON_PIO3_3_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	565	#define IOCON_PIO3_3_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	566	#define IOCON_PIO3_3_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
MACRUM	6:40e873bbc5f7	567
MACRUM	6:40e873bbc5f7	568	/* IOCON_SCK_LOC, address 0x4004 40B0 */
MACRUM	6:40e873bbc5f7	569	#define IOCON_SCK_LOC_SCKLOC_MASK 0x0003 // Selects pin location for SCK0 function.
MACRUM	6:40e873bbc5f7	570	#define IOCON_SCK_LOC_SCKLOC_SHIFT 0
MACRUM	6:40e873bbc5f7	571
MACRUM	6:40e873bbc5f7	572	/* IOCON_DSR_LOC, address 0x4004 40B4 */
MACRUM	6:40e873bbc5f7	573	#define IOCON_DSR_LOC_DSRLOC_MASK 0x0003 // elects pin location for DSR function.
MACRUM	6:40e873bbc5f7	574	#define IOCON_DSR_LOC_DSRLOC_SHIFT 0
MACRUM	6:40e873bbc5f7	575
MACRUM	6:40e873bbc5f7	576	/* IOCON_DCD_LOC, address 0x4004 40B8 */
MACRUM	6:40e873bbc5f7	577	#define IOCON_DCD_LOC_DCDLOC_MASK 0x0003 // Selects pin location for DCD function.
MACRUM	6:40e873bbc5f7	578	#define IOCON_DCD_LOC_DCDLOC_SHIFT 0
MACRUM	6:40e873bbc5f7	579
MACRUM	6:40e873bbc5f7	580	/* IOCON_RI_LOC, address 0x4004 40BC */
MACRUM	6:40e873bbc5f7	581	#define IOCON_RI_LOC_RILOC_MASK 0x0003 // Selects pin location for RI function.
MACRUM	6:40e873bbc5f7	582	#define IOCON_RI_LOC_RILOC_SHIFT 0
MACRUM	6:40e873bbc5f7	583
MACRUM	6:40e873bbc5f7	584	/* IOCON_PIO2_6, address 0x4004 4000 */
MACRUM	6:40e873bbc5f7	585	#define IOCON_PIO2_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	586	#define IOCON_PIO2_6_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	587	#define IOCON_PIO2_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	588	#define IOCON_PIO2_6_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	589	#define IOCON_PIO2_6_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	590	#define IOCON_PIO2_6_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	591
MACRUM	6:40e873bbc5f7	592	/* IOCON_PIO2_0, address 0x4004 4008 */
MACRUM	6:40e873bbc5f7	593	#define IOCON_PIO2_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	594	#define IOCON_PIO2_0_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	595	#define IOCON_PIO2_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	596	#define IOCON_PIO2_0_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	597	#define IOCON_PIO2_0_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	598	#define IOCON_PIO2_0_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	599
MACRUM	6:40e873bbc5f7	600	/* IOCON_RESET_PIO0_0, address 0x4004 400C */
MACRUM	6:40e873bbc5f7	601	#define IOCON_RESET_PIO0_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	602	#define IOCON_RESET_PIO0_0_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	603	#define IOCON_RESET_PIO0_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	604	#define IOCON_RESET_PIO0_0_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	605	#define IOCON_RESET_PIO0_0_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	606	#define IOCON_RESET_PIO0_0_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	607
MACRUM	6:40e873bbc5f7	608	/* IOCON_PIO0_1, address 0x4004 4010 */
MACRUM	6:40e873bbc5f7	609	#define IOCON_PIO0_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	610	#define IOCON_PIO0_1_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	611	#define IOCON_PIO0_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	612	#define IOCON_PIO0_1_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	613	#define IOCON_PIO0_1_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	614	#define IOCON_PIO0_1_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	615
MACRUM	6:40e873bbc5f7	616	/* IOCON_PIO1_8, address 0x4004 4014 */
MACRUM	6:40e873bbc5f7	617	#define IOCON_PIO1_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	618	#define IOCON_PIO1_8_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	619	#define IOCON_PIO1_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	620	#define IOCON_PIO1_8_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	621	#define IOCON_PIO1_8_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	622	#define IOCON_PIO1_8_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	623
MACRUM	6:40e873bbc5f7	624	/* IOCON_PIO0_2, address 0x4004 401C */
MACRUM	6:40e873bbc5f7	625	#define IOCON_PIO0_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	626	#define IOCON_PIO0_2_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	627	#define IOCON_PIO0_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	628	#define IOCON_PIO0_2_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	629	#define IOCON_PIO0_2_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	630	#define IOCON_PIO0_2_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	631
MACRUM	6:40e873bbc5f7	632	/* IOCON_PIO2_7, address 0x4004 4020 */
MACRUM	6:40e873bbc5f7	633	#define IOCON_PIO2_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	634	#define IOCON_PIO2_7_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	635	#define IOCON_PIO2_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	636	#define IOCON_PIO2_7_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	637	#define IOCON_PIO2_7_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	638	#define IOCON_PIO2_7_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	639
MACRUM	6:40e873bbc5f7	640	/* IOCON_PIO2_8, address 0x4004 4024 */
MACRUM	6:40e873bbc5f7	641	#define IOCON_PIO2_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	642	#define IOCON_PIO2_8_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	643	#define IOCON_PIO2_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	644	#define IOCON_PIO2_8_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	645	#define IOCON_PIO2_8_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	646	#define IOCON_PIO2_8_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	647
MACRUM	6:40e873bbc5f7	648	/* IOCON_PIO2_1, address 0x4004 4028 */
MACRUM	6:40e873bbc5f7	649	#define IOCON_PIO2_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	650	#define IOCON_PIO2_1_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	651	#define IOCON_PIO2_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	652	#define IOCON_PIO2_1_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	653	#define IOCON_PIO2_1_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	654	#define IOCON_PIO2_1_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	655
MACRUM	6:40e873bbc5f7	656	/* IOCON_PIO0_3, address 0x4004 402C */
MACRUM	6:40e873bbc5f7	657	#define IOCON_PIO0_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	658	#define IOCON_PIO0_3_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	659	#define IOCON_PIO0_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	660	#define IOCON_PIO0_3_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	661	#define IOCON_PIO0_3_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	662	#define IOCON_PIO0_3_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	663
MACRUM	6:40e873bbc5f7	664	/* IOCON_PIO0_4, address 0x4004 4030 */
MACRUM	6:40e873bbc5f7	665	#define IOCON_PIO0_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	666	#define IOCON_PIO0_4_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	667	#define IOCON_PIO0_4_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, 00 default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
MACRUM	6:40e873bbc5f7	668	#define IOCON_PIO0_4_I2CMODE_SHIFT 8
MACRUM	6:40e873bbc5f7	669
MACRUM	6:40e873bbc5f7	670	/* IOCON_PIO0_5, address 0x4004 4034 */
MACRUM	6:40e873bbc5f7	671	#define IOCON_PIO0_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	672	#define IOCON_PIO0_5_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	673	#define IOCON_PIO0_5_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
MACRUM	6:40e873bbc5f7	674	#define IOCON_PIO0_5_I2CMODE_SHIFT 8
MACRUM	6:40e873bbc5f7	675
MACRUM	6:40e873bbc5f7	676	/* IOCON_PIO1_9, address 0x4004 4038 */
MACRUM	6:40e873bbc5f7	677	#define IOCON_PIO1_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	678	#define IOCON_PIO1_9_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	679	#define IOCON_PIO1_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	680	#define IOCON_PIO1_9_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	681	#define IOCON_PIO1_9_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	682	#define IOCON_PIO1_9_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	683
MACRUM	6:40e873bbc5f7	684	/* IOCON_PIO3_4, address 0x4004 403C */
MACRUM	6:40e873bbc5f7	685	#define IOCON_PIO3_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	686	#define IOCON_PIO3_4_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	687	#define IOCON_PIO3_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	688	#define IOCON_PIO3_4_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	689	#define IOCON_PIO3_4_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	690	#define IOCON_PIO3_4_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	691
MACRUM	6:40e873bbc5f7	692	/* IOCON_PIO2_4, address 0x4004 4040 */
MACRUM	6:40e873bbc5f7	693	#define IOCON_PIO2_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	694	#define IOCON_PIO2_4_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	695	#define IOCON_PIO2_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	696	#define IOCON_PIO2_4_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	697	#define IOCON_PIO2_4_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	698	#define IOCON_PIO2_4_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	699
MACRUM	6:40e873bbc5f7	700	/* IOCON_PIO2_5, address 0x4004 4044 */
MACRUM	6:40e873bbc5f7	701	#define IOCON_PIO2_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	702	#define IOCON_PIO2_5_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	703	#define IOCON_PIO2_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	704	#define IOCON_PIO2_5_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	705	#define IOCON_PIO2_5_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	706	#define IOCON_PIO2_5_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	707
MACRUM	6:40e873bbc5f7	708	/* IOCON_PIO3_5, address 0x4004 4048 */
MACRUM	6:40e873bbc5f7	709	#define IOCON_PIO3_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	710	#define IOCON_PIO3_5_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	711	#define IOCON_PIO3_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	712	#define IOCON_PIO3_5_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	713	#define IOCON_PIO3_5_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	714	#define IOCON_PIO3_5_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	715
MACRUM	6:40e873bbc5f7	716	/* IOCON_PIO0_6, address 0x4004 404C */
MACRUM	6:40e873bbc5f7	717	#define IOCON_PIO0_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	718	#define IOCON_PIO0_6_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	719	#define IOCON_PIO0_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	720	#define IOCON_PIO0_6_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	721	#define IOCON_PIO0_6_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	722	#define IOCON_PIO0_6_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	723
MACRUM	6:40e873bbc5f7	724	/* IOCON_PIO0_7, address 0x4004 4050 */
MACRUM	6:40e873bbc5f7	725	#define IOCON_PIO0_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	726	#define IOCON_PIO0_7_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	727	#define IOCON_PIO0_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	728	#define IOCON_PIO0_7_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	729	#define IOCON_PIO0_7_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	730	#define IOCON_PIO0_7_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	731
MACRUM	6:40e873bbc5f7	732	/* IOCON_PIO2_9, address 0x4004 4054 */
MACRUM	6:40e873bbc5f7	733	#define IOCON_PIO2_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	734	#define IOCON_PIO2_9_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	735	#define IOCON_PIO2_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	736	#define IOCON_PIO2_9_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	737	#define IOCON_PIO2_9_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	738	#define IOCON_PIO2_9_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	739
MACRUM	6:40e873bbc5f7	740	/* IOCON_PIO2_10, address 0x4004 4058 */
MACRUM	6:40e873bbc5f7	741	#define IOCON_PIO2_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	742	#define IOCON_PIO2_10_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	743	#define IOCON_PIO2_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	744	#define IOCON_PIO2_10_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	745	#define IOCON_PIO2_10_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	746	#define IOCON_PIO2_10_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	747
MACRUM	6:40e873bbc5f7	748	/* IOCON_PIO2_2, address 0x4004 405C */
MACRUM	6:40e873bbc5f7	749	#define IOCON_PIO2_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	750	#define IOCON_PIO2_2_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	751	#define IOCON_PIO2_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	752	#define IOCON_PIO2_2_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	753	#define IOCON_PIO2_2_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	754	#define IOCON_PIO2_2_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	755
MACRUM	6:40e873bbc5f7	756	/* IOCON_PIO0_8, address 0x4004 4060 */
MACRUM	6:40e873bbc5f7	757	#define IOCON_PIO0_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	758	#define IOCON_PIO0_8_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	759	#define IOCON_PIO0_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	760	#define IOCON_PIO0_8_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	761	#define IOCON_PIO0_8_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	762	#define IOCON_PIO0_8_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	763
MACRUM	6:40e873bbc5f7	764	/* IOCON_PIO0_9, address 0x4004 4064 */
MACRUM	6:40e873bbc5f7	765	#define IOCON_PIO0_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	766	#define IOCON_PIO0_9_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	767	#define IOCON_PIO0_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	768	#define IOCON_PIO0_9_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	769	#define IOCON_PIO0_9_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	770	#define IOCON_PIO0_9_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	771
MACRUM	6:40e873bbc5f7	772	/* IOCON_SWCLK_PIO0_10, address 0x4004 4068 */
MACRUM	6:40e873bbc5f7	773	#define IOCON_SWCLK_PIO0_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	774	#define IOCON_SWCLK_PIO0_10_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	775	#define IOCON_SWCLK_PIO0_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	776	#define IOCON_SWCLK_PIO0_10_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	777	#define IOCON_SWCLK_PIO0_10_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	778	#define IOCON_SWCLK_PIO0_10_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	779
MACRUM	6:40e873bbc5f7	780	/* IOCON_PIO1_10, address 0x4004 406C */
MACRUM	6:40e873bbc5f7	781	#define IOCON_PIO1_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	782	#define IOCON_PIO1_10_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	783	#define IOCON_PIO1_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	784	#define IOCON_PIO1_10_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	785	#define IOCON_PIO1_10_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	786	#define IOCON_PIO1_10_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	787	#define IOCON_PIO1_10_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	788
MACRUM	6:40e873bbc5f7	789	/* IOCON_PIO2_11, address 0x4004 4070 */
MACRUM	6:40e873bbc5f7	790	#define IOCON_PIO2_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	791	#define IOCON_PIO2_11_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	792	#define IOCON_PIO2_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	793	#define IOCON_PIO2_11_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	794	#define IOCON_PIO2_11_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	795	#define IOCON_PIO2_11_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	796
MACRUM	6:40e873bbc5f7	797	/* IOCON_R_PIO0_11, address 0x4004 4074 */
MACRUM	6:40e873bbc5f7	798	#define IOCON_R_PIO0_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	799	#define IOCON_R_PIO0_11_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	800	#define IOCON_R_PIO0_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	801	#define IOCON_R_PIO0_11_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	802	#define IOCON_R_PIO0_11_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	803	#define IOCON_R_PIO0_11_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	804	#define IOCON_R_PIO0_11_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	805
MACRUM	6:40e873bbc5f7	806	/* IOCON_R_PIO1_0, address 0x4004 4078 */
MACRUM	6:40e873bbc5f7	807	#define IOCON_R_PIO1_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	808	#define IOCON_R_PIO1_0_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	809	#define IOCON_R_PIO1_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	810	#define IOCON_R_PIO1_0_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	811	#define IOCON_R_PIO1_0_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	812	#define IOCON_R_PIO1_0_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	813	#define IOCON_R_PIO1_0_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	814
MACRUM	6:40e873bbc5f7	815	/* IOCON_R_PIO1_1, address 0x4004 407C */
MACRUM	6:40e873bbc5f7	816	#define IOCON_R_PIO1_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	817	#define IOCON_R_PIO1_1_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	818	#define IOCON_R_PIO1_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	819	#define IOCON_R_PIO1_1_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	820	#define IOCON_R_PIO1_1_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	821	#define IOCON_R_PIO1_1_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	822	#define IOCON_R_PIO1_1_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	823
MACRUM	6:40e873bbc5f7	824	/* IOCON_R_PIO1_2, address 0x4004 4080 */
MACRUM	6:40e873bbc5f7	825	#define IOCON_R_PIO1_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	826	#define IOCON_R_PIO1_2_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	827	#define IOCON_R_PIO1_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	828	#define IOCON_R_PIO1_2_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	829	#define IOCON_R_PIO1_2_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	830	#define IOCON_R_PIO1_2_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	831	#define IOCON_R_PIO1_2_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	832
MACRUM	6:40e873bbc5f7	833	/* IOCON_PIO3_0, address 0x4004 4084 */
MACRUM	6:40e873bbc5f7	834	#define IOCON_PIO3_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	835	#define IOCON_PIO3_0_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	836	#define IOCON_PIO3_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	837	#define IOCON_PIO3_0_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	838	#define IOCON_PIO3_0_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	839	#define IOCON_PIO3_0_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	840
MACRUM	6:40e873bbc5f7	841	/* IOCON_PIO3_1, address 0x4004 4088 */
MACRUM	6:40e873bbc5f7	842	#define IOCON_PIO3_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	843	#define IOCON_PIO3_1_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	844	#define IOCON_PIO3_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	845	#define IOCON_PIO3_1_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	846	#define IOCON_PIO3_1_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	847	#define IOCON_PIO3_1_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	848
MACRUM	6:40e873bbc5f7	849	/* IOCON_PIO2_3, address 0x4004 408C */
MACRUM	6:40e873bbc5f7	850	#define IOCON_PIO2_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	851	#define IOCON_PIO2_3_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	852	#define IOCON_PIO2_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	853	#define IOCON_PIO2_3_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	854	#define IOCON_PIO2_3_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	855	#define IOCON_PIO2_3_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	856
MACRUM	6:40e873bbc5f7	857	/* IOCON_SWDIO_PIO1_3, address 0x4004 4090 */
MACRUM	6:40e873bbc5f7	858	#define IOCON_SWDIO_PIO1_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	859	#define IOCON_SWDIO_PIO1_3_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	860	#define IOCON_SWDIO_PIO1_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	861	#define IOCON_SWDIO_PIO1_3_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	862	#define IOCON_SWDIO_PIO1_3_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	863	#define IOCON_SWDIO_PIO1_3_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	864	#define IOCON_SWDIO_PIO1_3_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	865
MACRUM	6:40e873bbc5f7	866	/* IOCON_PIO1_4, address 0x4004 4094 */
MACRUM	6:40e873bbc5f7	867	#define IOCON_PIO1_4_FUNC_MASK 0x0007 // Selects pin function. This pin functions as WAKEUP pin if the 000 LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.
MACRUM	6:40e873bbc5f7	868	#define IOCON_PIO1_4_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	869	#define IOCON_PIO1_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	870	#define IOCON_PIO1_4_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	871	#define IOCON_PIO1_4_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	872	#define IOCON_PIO1_4_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	873	#define IOCON_PIO1_4_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	874
MACRUM	6:40e873bbc5f7	875	/* IOCON_PIO1_11, address 0x4004 4098 */
MACRUM	6:40e873bbc5f7	876	#define IOCON_PIO1_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	877	#define IOCON_PIO1_11_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	878	#define IOCON_PIO1_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	879	#define IOCON_PIO1_11_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	880	#define IOCON_PIO1_11_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	881	#define IOCON_PIO1_11_ADMODE (1 << 7) // Selects Analog/Digital mode
MACRUM	6:40e873bbc5f7	882	#define IOCON_PIO1_11_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	883
MACRUM	6:40e873bbc5f7	884	/* IOCON_PIO3_2, address 0x4004 409C */
MACRUM	6:40e873bbc5f7	885	#define IOCON_PIO3_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	886	#define IOCON_PIO3_2_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	887	#define IOCON_PIO3_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	888	#define IOCON_PIO3_2_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	889	#define IOCON_PIO3_2_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	890	#define IOCON_PIO3_2_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	891
MACRUM	6:40e873bbc5f7	892	/* IOCON_PIO1_5, address 0x4004 40A0 */
MACRUM	6:40e873bbc5f7	893	#define IOCON_PIO1_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	894	#define IOCON_PIO1_5_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	895	#define IOCON_PIO1_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	896	#define IOCON_PIO1_5_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	897	#define IOCON_PIO1_5_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	898	#define IOCON_PIO1_5_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	899
MACRUM	6:40e873bbc5f7	900	/* IOCON_PIO1_6, address 0x4004 40A4 */
MACRUM	6:40e873bbc5f7	901	#define IOCON_PIO1_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	902	#define IOCON_PIO1_6_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	903	#define IOCON_PIO1_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	904	#define IOCON_PIO1_6_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	905	#define IOCON_PIO1_6_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	906	#define IOCON_PIO1_6_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	907
MACRUM	6:40e873bbc5f7	908	/* IOCON_PIO1_7, address 0x4004 40A8 */
MACRUM	6:40e873bbc5f7	909	#define IOCON_PIO1_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	910	#define IOCON_PIO1_7_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	911	#define IOCON_PIO1_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	912	#define IOCON_PIO1_7_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	913	#define IOCON_PIO1_7_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	914	#define IOCON_PIO1_7_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	915
MACRUM	6:40e873bbc5f7	916	/* IOCON_PIO3_3, address 0x4004 40AC */
MACRUM	6:40e873bbc5f7	917	#define IOCON_PIO3_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
MACRUM	6:40e873bbc5f7	918	#define IOCON_PIO3_3_FUNC_SHIFT 0
MACRUM	6:40e873bbc5f7	919	#define IOCON_PIO3_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
MACRUM	6:40e873bbc5f7	920	#define IOCON_PIO3_3_MODE_SHIFT 3
MACRUM	6:40e873bbc5f7	921	#define IOCON_PIO3_3_HYS (1 << 5) // Hysteresis.
MACRUM	6:40e873bbc5f7	922	#define IOCON_PIO3_3_OD (1 << 10) // Selects pseudo open-drain mode.
MACRUM	6:40e873bbc5f7	923
MACRUM	6:40e873bbc5f7	924	/* IOCON_SCK0_LOC, address 0x4004 40B0 */
MACRUM	6:40e873bbc5f7	925	#define IOCON_SCK0_LOC_SCKLOC_MASK 0x0003 // Selects pin location for SCK0 function.
MACRUM	6:40e873bbc5f7	926	#define IOCON_SCK0_LOC_SCKLOC_SHIFT 0
MACRUM	6:40e873bbc5f7	927
MACRUM	6:40e873bbc5f7	928	/* IOCON_DSR_LOC, address 0x4004 40B4 */
MACRUM	6:40e873bbc5f7	929	#define IOCON_DSR_LOC_DSRLOC_MASK 0x0003 // elects pin location for DSR function.
MACRUM	6:40e873bbc5f7	930	#define IOCON_DSR_LOC_DSRLOC_SHIFT 0
MACRUM	6:40e873bbc5f7	931
MACRUM	6:40e873bbc5f7	932	/* IOCON_DCD_LOC, address 0x4004 40B8 */
MACRUM	6:40e873bbc5f7	933	#define IOCON_DCD_LOC_DCDLOC_MASK 0x0003 // Selects pin location for DCD function.
MACRUM	6:40e873bbc5f7	934	#define IOCON_DCD_LOC_DCDLOC_SHIFT 0
MACRUM	6:40e873bbc5f7	935
MACRUM	6:40e873bbc5f7	936	/* IOCON_RI_LOC, address 0x4004 40BC */
MACRUM	6:40e873bbc5f7	937	#define IOCON_RI_LOC_RILOC_MASK 0x0003 // Selects pin location for RI function.
MACRUM	6:40e873bbc5f7	938	#define IOCON_RI_LOC_RILOC_SHIFT 0
MACRUM	6:40e873bbc5f7	939
MACRUM	6:40e873bbc5f7	940	/* IOCON_SSEL1_LOC, address 0x4004 4018 */
MACRUM	6:40e873bbc5f7	941	#define IOCON_SSEL1_LOC_SSEL1LOC_MASK 0x0003 // Selects pin location for SSEL1 function.
MACRUM	6:40e873bbc5f7	942	#define IOCON_SSEL1_LOC_SSEL1LOC_SHIFT 0
MACRUM	6:40e873bbc5f7	943
MACRUM	6:40e873bbc5f7	944	/* IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0 */
MACRUM	6:40e873bbc5f7	945	#define IOCON_CT16B0_CAP0_LOC_CT16B0_CAP0LOC_MASK 0x0003 // Selects pin location for CT16B0_CAP0 function.
MACRUM	6:40e873bbc5f7	946	#define IOCON_CT16B0_CAP0_LOC_CT16B0_CAP0LOC_SHIFT 0
MACRUM	6:40e873bbc5f7	947
MACRUM	6:40e873bbc5f7	948	/* IOCON_SCK1_LOC, address 0x4004 40C4 */
MACRUM	6:40e873bbc5f7	949	#define IOCON_SCK1_LOC_SCK1LOC_MASK 0x0003 // Selects pin location for SCK1 function.
MACRUM	6:40e873bbc5f7	950	#define IOCON_SCK1_LOC_SCK1LOC_SHIFT 0
MACRUM	6:40e873bbc5f7	951
MACRUM	6:40e873bbc5f7	952	/* IOCON_MISO1_LOC, address 0x4004 40C8 */
MACRUM	6:40e873bbc5f7	953	#define IOCON_MISO1_LOC_MISO1LOC_MASK 0x0003 // Selects pin location for the MISO1 function.
MACRUM	6:40e873bbc5f7	954	#define IOCON_MISO1_LOC_MISO1LOC_SHIFT 0
MACRUM	6:40e873bbc5f7	955
MACRUM	6:40e873bbc5f7	956	/* IOCON_MOSI1_LOC, address 0x4004 40CC */
MACRUM	6:40e873bbc5f7	957	#define IOCON_MOSI1_LOC_MOSI1LOC_MASK 0x0003 // Selects pin location for the MOSI1 function.
MACRUM	6:40e873bbc5f7	958	#define IOCON_MOSI1_LOC_MOSI1LOC_SHIFT 0
MACRUM	6:40e873bbc5f7	959
MACRUM	6:40e873bbc5f7	960	/* IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0 */
MACRUM	6:40e873bbc5f7	961	#define IOCON_CT32B0_CAP0_LOC_CT32B0_CAP0LOC_MASK 0x0003 // Selects pin location for the CT32B0_CAP0 function.
MACRUM	6:40e873bbc5f7	962	#define IOCON_CT32B0_CAP0_LOC_CT32B0_CAP0LOC_SHIFT 0
MACRUM	6:40e873bbc5f7	963
MACRUM	6:40e873bbc5f7	964	/* IOCON_RXD_LOC, address 0x4004 40D4 */
MACRUM	6:40e873bbc5f7	965	#define IOCON_RXD_LOC_RXDLOC_MASK 0x0003 // Selects pin location for the RXD function.
MACRUM	6:40e873bbc5f7	966	#define IOCON_RXD_LOC_RXDLOC_SHIFT 0
MACRUM	6:40e873bbc5f7	967
MACRUM	6:40e873bbc5f7	968	/* GPIO0DIR, address 0x5000 8000 to GPIO3DIR, address 0x5003 8000 */
MACRUM	6:40e873bbc5f7	969	#define GPIO0DIR_IO_MASK 0x0FFF // Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
MACRUM	6:40e873bbc5f7	970	#define GPIO0DIR_IO_SHIFT 0
MACRUM	6:40e873bbc5f7	971
MACRUM	6:40e873bbc5f7	972	/* GPIO0IS, address 0x5000 8004 to GPIO3IS, address 0x5003 8004 */
MACRUM	6:40e873bbc5f7	973	#define GPIO0IS_ISENSE_MASK 0x0FFF // Selects interrupt on pin x as level or edge sensitive (x = 0 to 0x00 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
MACRUM	6:40e873bbc5f7	974	#define GPIO0IS_ISENSE_SHIFT 0
MACRUM	6:40e873bbc5f7	975
MACRUM	6:40e873bbc5f7	976	/* GPIO0IBE, address 0x5000 8008 to GPIO3IBE, address 0x5003 8008 */
MACRUM	6:40e873bbc5f7	977	#define GPIO0IBE_IBE_MASK 0x0FFF // Selects interrupt on pin x to be triggered on both edges (x = 0 0x00 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
MACRUM	6:40e873bbc5f7	978	#define GPIO0IBE_IBE_SHIFT 0
MACRUM	6:40e873bbc5f7	979
MACRUM	6:40e873bbc5f7	980	/* GPIO0IEV, address 0x5000 800C to GPIO3IEV, address 0x5003 800C */
MACRUM	6:40e873bbc5f7	981	#define GPIO0IEV_IEV_MASK 0x0FFF // Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 175), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 175), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
MACRUM	6:40e873bbc5f7	982	#define GPIO0IEV_IEV_SHIFT 0
MACRUM	6:40e873bbc5f7	983
MACRUM	6:40e873bbc5f7	984	/* GPIO0IE, address 0x5000 8010 to GPIO3IE, address 0x5003 8010 */
MACRUM	6:40e873bbc5f7	985	#define GPIO0IE_MASK_MASK 0x0FFF // Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
MACRUM	6:40e873bbc5f7	986	#define GPIO0IE_MASK_SHIFT 0
MACRUM	6:40e873bbc5f7	987
MACRUM	6:40e873bbc5f7	988	/* GPIO0RIS, address 0x5000 8014 to GPIO3RIS, address 0x5003 8014 */
MACRUM	6:40e873bbc5f7	989	#define GPIO0RIS_RAWST_MASK 0x0FFF // Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
MACRUM	6:40e873bbc5f7	990	#define GPIO0RIS_RAWST_SHIFT 0
MACRUM	6:40e873bbc5f7	991
MACRUM	6:40e873bbc5f7	992	/* GPIO0MIS, address 0x5000 8018 to GPIO3MIS, address 0x5003 8018 */
MACRUM	6:40e873bbc5f7	993	#define GPIO0MIS_MASK_MASK 0x0FFF // Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
MACRUM	6:40e873bbc5f7	994	#define GPIO0MIS_MASK_SHIFT 0
MACRUM	6:40e873bbc5f7	995
MACRUM	6:40e873bbc5f7	996	/* GPIO0IC, address 0x5000 801C to GPIO3IC, address 0x5003 801C */
MACRUM	6:40e873bbc5f7	997	#define GPIO0IC_CLR_MASK 0x0FFF // Selects interrupt on pin x to be cleared (x = 0 to 11). Clears 0x00 the interrupt edge detection logic. This register is write-only. Remark: The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
MACRUM	6:40e873bbc5f7	998	#define GPIO0IC_CLR_SHIFT 0
MACRUM	6:40e873bbc5f7	999
MACRUM	6:40e873bbc5f7	1000	/* U0IIR - address 0x4004 8008, Read Only */
MACRUM	6:40e873bbc5f7	1001	#define U0IIR_INTSTATUS (1 << 0) // Interrupt status. Note that U0IIR[0] is active low. The pending interrupt can be determined by evaluating U0IIR[3:1].
MACRUM	6:40e873bbc5f7	1002	#define U0IIR_INTID_MASK 0x000E // Interrupt identification. U0IER[3:1] identifies an interrupt 0 corresponding to the UART Rx FIFO. All other combinations of U0IER[3:1] not listed below are reserved (100,101,111).
MACRUM	6:40e873bbc5f7	1003	#define U0IIR_INTID_SHIFT 1
MACRUM	6:40e873bbc5f7	1004	#define U0IIR_FIFOENABLE_MASK 0x00C0 // These bits are equivalent to U0FCR[0].
MACRUM	6:40e873bbc5f7	1005	#define U0IIR_FIFOENABLE_SHIFT 6
MACRUM	6:40e873bbc5f7	1006	#define U0IIR_ABEOINT (1 << 8) // End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
MACRUM	6:40e873bbc5f7	1007	#define U0IIR_ABTOINT (1 << 9) // Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
MACRUM	6:40e873bbc5f7	1008
MACRUM	6:40e873bbc5f7	1009	/* U0FCR - address 0x4000 8008, Write Only */
MACRUM	6:40e873bbc5f7	1010	#define U0FCR_FIFOEN (1 << 0) // FIFO Enable
MACRUM	6:40e873bbc5f7	1011	#define U0FCR_RXFIFORES (1 << 1) // RX FIFO Reset
MACRUM	6:40e873bbc5f7	1012	#define U0FCR_TXFIFORES (1 << 2) // TX FIFO Reset
MACRUM	6:40e873bbc5f7	1013	#define U0FCR_RXTL_MASK 0x00C0 // RX Trigger Level. These two bits determine how many 0 receiver UART FIFO characters must be written before an interrupt is activated.
MACRUM	6:40e873bbc5f7	1014	#define U0FCR_RXTL_SHIFT 6
MACRUM	6:40e873bbc5f7	1015
MACRUM	6:40e873bbc5f7	1016	/* U0LCR - address 0x4000 800C */
MACRUM	6:40e873bbc5f7	1017	#define U0LCR_WLS_MASK 0x0003 // Word Length Select
MACRUM	6:40e873bbc5f7	1018	#define U0LCR_WLS_SHIFT 0
MACRUM	6:40e873bbc5f7	1019	#define U0LCR_SBS (1 << 2) // Stop Bit Select
MACRUM	6:40e873bbc5f7	1020	#define U0LCR_PE (1 << 3) // Parity Enable
MACRUM	6:40e873bbc5f7	1021	#define U0LCR_PS_MASK 0x0030 // Parity Select 0x0 Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x1 Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x2 Forced 1 stick parity. 0x3 Forced 0 stick parity.
MACRUM	6:40e873bbc5f7	1022	#define U0LCR_PS_SHIFT 4
MACRUM	6:40e873bbc5f7	1023	#define U0LCR_BC (1 << 6) // Break Control
MACRUM	6:40e873bbc5f7	1024	#define U0LCR_DLAB (1 << 7) // Divisor Latch Access Bit
MACRUM	6:40e873bbc5f7	1025
MACRUM	6:40e873bbc5f7	1026	/* U0MCR - address 0x4000 8010 */
MACRUM	6:40e873bbc5f7	1027	#define U0MCR_DTRC (1 << 0) // DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.
MACRUM	6:40e873bbc5f7	1028	#define U0MCR_RTSC (1 << 1) // RTS Control. Source for modem output pin RTS. This bit reads as 0 0 when modem loopback mode is active.
MACRUM	6:40e873bbc5f7	1029	#define U0MCR_LMS (1 << 4) // Loopback Mode Select. The modem loopback mode provides a 0 mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the U0MSR will be driven by the lower four bits of the U0MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of U0MCR.
MACRUM	6:40e873bbc5f7	1030	#define U0MCR_RTSEN (1 << 6) // RTS flow control
MACRUM	6:40e873bbc5f7	1031	#define U0MCR_CTSEN (1 << 7) // CTS flow control
MACRUM	6:40e873bbc5f7	1032
MACRUM	6:40e873bbc5f7	1033	/* U0LSR - address 0x4000 8014, Read Only */
MACRUM	6:40e873bbc5f7	1034	#define U0LSR_RDR (1 << 0) // Receiver Data Ready. U0LSR[0] is set when the U0RBR holds 0 an unread character and is cleared when the UART RBR FIFO is empty.
MACRUM	6:40e873bbc5f7	1035	#define U0LSR_OE (1 << 1) // Overrun Error. The overrun error condition is set as soon as it 0 occurs. A U0LSR read clears U0LSR[1]. U0LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost.
MACRUM	6:40e873bbc5f7	1036	#define U0LSR_PE (1 << 2) // Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A U0LSR read clears U0LSR[2]. Time of parity error detection is dependent on U0FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO.
MACRUM	6:40e873bbc5f7	1037	#define U0LSR_FE (1 << 3) // Framing Error. When the stop bit of a received character is a 0 logic 0, a framing error occurs. A U0LSR read clears U0LSR[3]. The time of the framing error detection is dependent on U0FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO.
MACRUM	6:40e873bbc5f7	1038	#define U0LSR_BI (1 << 4) // Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A U0LSR read clears this status bit. The time of break detection is dependent on U0FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO.
MACRUM	6:40e873bbc5f7	1039	#define U0LSR_THRE (1 << 5) // Transmitter Holding Register Empty. THRE is set immediately 1 upon detection of an empty UART THR and is cleared on a U0THR write.
MACRUM	6:40e873bbc5f7	1040	#define U0LSR_TEMT (1 << 6) // Transmitter Empty. TEMT is set when both U0THR and 1 U0TSR are empty; TEMT is cleared when either the U0TSR or the U0THR contain valid data. This bit is updated as soon as 50 % of the first stop bit has been transmitted or a byte has been written into the THR.
MACRUM	6:40e873bbc5f7	1041	#define U0LSR_RXFE (1 << 7) // Error in RX FIFO. U0LSR[7] is set when a character with a RX 0 error such as framing error, parity error or break interrupt, is loaded into the U0RBR. This bit is cleared when the U0LSR register is read and there are no subsequent errors in the UART FIFO.
MACRUM	6:40e873bbc5f7	1042
MACRUM	6:40e873bbc5f7	1043	/* U0MSR - address 0x4000 8018 */
MACRUM	6:40e873bbc5f7	1044	#define U0MSR_DCTS (1 << 0) // Delta CTS. Set upon state change of input CTS. Cleared on a U0MSR read. 0 No change detected on modem input CTS. 1 State change detected on modem input CTS.
MACRUM	6:40e873bbc5f7	1045	#define U0MSR_DDSR (1 << 1) // Delta DSR. Set upon state change of input DSR. Cleared on a U0MSR read. 0 No change detected on modem input DSR. 1 State change detected on modem input DSR.
MACRUM	6:40e873bbc5f7	1046	#define U0MSR_TERI (1 << 2) // Trailing Edge RI. Set upon low to high transition of input RI. Cleared 0 on a U0MSR read. 0 No change detected on modem input, RI. 1 Low-to-high transition detected on RI.
MACRUM	6:40e873bbc5f7	1047	#define U0MSR_DDCD (1 << 3) // Delta DCD. Set upon state change of input DCD. Cleared on a U0MSR read. 0 No change detected on modem input DCD. 1 State change detected on modem input DCD.
MACRUM	6:40e873bbc5f7	1048	#define U0MSR_CTS (1 << 4) // Clear To Send State. Complement of input signal CTS. This bit is connected to U0MCR[1] in modem loopback mode.
MACRUM	6:40e873bbc5f7	1049	#define U0MSR_DSR (1 << 5) // Data Set Ready State. Complement of input signal DSR. This bit is connected to U0MCR[0] in modem loopback mode.
MACRUM	6:40e873bbc5f7	1050	#define U0MSR_RI (1 << 6) // Ring Indicator State. Complement of input RI. This bit is connected to U0MCR[2] in modem loopback mode.
MACRUM	6:40e873bbc5f7	1051	#define U0MSR_DCD (1 << 7) // Data Carrier Detect State. Complement of input DCD. This bit is connected to U0MCR[3] in modem loopback mode.
MACRUM	6:40e873bbc5f7	1052
MACRUM	6:40e873bbc5f7	1053	/* U0SCR - address 0x4000 801C */
MACRUM	6:40e873bbc5f7	1054	#define U0SCR_PAD_MASK 0x00FF // A readable, writable byte.
MACRUM	6:40e873bbc5f7	1055	#define U0SCR_PAD_SHIFT 0
MACRUM	6:40e873bbc5f7	1056
MACRUM	6:40e873bbc5f7	1057	/* U0ACR - address 0x4000 8020 */
MACRUM	6:40e873bbc5f7	1058	#define U0ACR_START (1 << 0) // Start bit. This bit is automatically cleared after auto-baud completion.
MACRUM	6:40e873bbc5f7	1059	#define U0ACR_MODE (1 << 1) // Auto-baud mode select
MACRUM	6:40e873bbc5f7	1060	#define U0ACR_AUTORESTART (1 << 2) // Restart enable
MACRUM	6:40e873bbc5f7	1061	#define U0ACR_ABEOINTCLR (1 << 8) // End of auto-baud interrupt clear (write only accessible)
MACRUM	6:40e873bbc5f7	1062	#define U0ACR_ABTOINTCLR (1 << 9) // Auto-baud time-out interrupt clear (write only accessible)
MACRUM	6:40e873bbc5f7	1063
MACRUM	6:40e873bbc5f7	1064	/* U0TER - address 0x4000 8030 */
MACRUM	6:40e873bbc5f7	1065	#define U0TER_TXEN (1 << 7) // When this bit is 1, as it is after a Reset, data written to the THR 1 is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. Reserved
MACRUM	6:40e873bbc5f7	1066
MACRUM	6:40e873bbc5f7	1067	/* U0RS485CTRL - address 0x4000 804C */
MACRUM	6:40e873bbc5f7	1068	#define U0RS485CTRL_NMMEN (1 << 0) // NMM enable.
MACRUM	6:40e873bbc5f7	1069	#define U0RS485CTRL_RXDIS (1 << 1) // Receiver enable.
MACRUM	6:40e873bbc5f7	1070	#define U0RS485CTRL_AADEN (1 << 2) // AAD enable.
MACRUM	6:40e873bbc5f7	1071	#define U0RS485CTRL_SEL (1 << 3) // Select direction control pin
MACRUM	6:40e873bbc5f7	1072	#define U0RS485CTRL_DCTRL (1 << 4) // Auto direction control enable.
MACRUM	6:40e873bbc5f7	1073	#define U0RS485CTRL_OINV (1 << 5) // Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
MACRUM	6:40e873bbc5f7	1074
MACRUM	6:40e873bbc5f7	1075	/* U0RS485ADRMATCH - address 0x4000 8050 */
MACRUM	6:40e873bbc5f7	1076	#define U0RS485ADRMATCH_ADRMATCH_MASK 0x00FF // Contains the address match value. 0
MACRUM	6:40e873bbc5f7	1077	#define U0RS485ADRMATCH_ADRMATCH_SHIFT 0
MACRUM	6:40e873bbc5f7	1078
MACRUM	6:40e873bbc5f7	1079	/* U0RS485DLY - address 0x4000 8054 */
MACRUM	6:40e873bbc5f7	1080	#define U0RS485DLY_DLY_MASK 0x00FF // Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.
MACRUM	6:40e873bbc5f7	1081	#define U0RS485DLY_DLY_SHIFT 0
MACRUM	6:40e873bbc5f7	1082
MACRUM	6:40e873bbc5f7	1083	/* SSP0CR0 - address 0x4004 0000, SSP1CR0 - address 0x4005 8000 */
MACRUM	6:40e873bbc5f7	1084	#define SSP0CR0_DSS_MASK 0x000F // Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
MACRUM	6:40e873bbc5f7	1085	#define SSP0CR0_DSS_SHIFT 0
MACRUM	6:40e873bbc5f7	1086	#define SSP0CR0_FRF_MASK 0x0030 // Frame Format.
MACRUM	6:40e873bbc5f7	1087	#define SSP0CR0_FRF_SHIFT 4
MACRUM	6:40e873bbc5f7	1088	#define SSP0CR0_CPOL (1 << 6) // Clock Out Polarity. This bit is only used in SPI mode.
MACRUM	6:40e873bbc5f7	1089	#define SSP0CR0_CPHA (1 << 7) // Clock Out Phase. This bit is only used in SPI mode.
MACRUM	6:40e873bbc5f7	1090	#define SSP0CR0_SCR_MASK 0xFF00 // Serial Clock Rate. The number of prescaler output clocks per 0x00 bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR [SCR+1]). Reserved
MACRUM	6:40e873bbc5f7	1091	#define SSP0CR0_SCR_SHIFT 8
MACRUM	6:40e873bbc5f7	1092
MACRUM	6:40e873bbc5f7	1093	/* SSP0CR1 - address 0x4004 0004, SSP1CR1 - address 0x4005 8004 */
MACRUM	6:40e873bbc5f7	1094	#define SSP0CR1_LBM (1 << 0) // Loop Back Mode.
MACRUM	6:40e873bbc5f7	1095	#define SSP0CR1_SSE (1 << 1) // SPI Enable.
MACRUM	6:40e873bbc5f7	1096	#define SSP0CR1_MS (1 << 2) // Master/Slave Mode.This bit can only be written when the SSE bit is 0.
MACRUM	6:40e873bbc5f7	1097	#define SSP0CR1_SOD (1 << 3) // Slave Output Disable. This bit is relevant only in slave 0 mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO).
MACRUM	6:40e873bbc5f7	1098
MACRUM	6:40e873bbc5f7	1099	/* SSP0DR - address 0x4004 0008, SSP1DR - address 0x4005 8008 */
MACRUM	6:40e873bbc5f7	1100	#define SSP0DR_DATA_MASK 0xFFFF // Write: software can write data to be sent in a future frame to this 0x0000 register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. Reserved.
MACRUM	6:40e873bbc5f7	1101	#define SSP0DR_DATA_SHIFT 0
MACRUM	6:40e873bbc5f7	1102
MACRUM	6:40e873bbc5f7	1103	/* SSP0SR - address 0x4004 000C, SSP1SR - address 0x4005 800C */
MACRUM	6:40e873bbc5f7	1104	#define SSP0SR_TFE (1 << 0) // Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
MACRUM	6:40e873bbc5f7	1105	#define SSP0SR_TNF (1 << 1) // Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
MACRUM	6:40e873bbc5f7	1106	#define SSP0SR_RNE (1 << 2) // Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
MACRUM	6:40e873bbc5f7	1107	#define SSP0SR_RFF (1 << 3) // Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
MACRUM	6:40e873bbc5f7	1108	#define SSP0SR_BSY (1 << 4) // Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
MACRUM	6:40e873bbc5f7	1109
MACRUM	6:40e873bbc5f7	1110	/* SSP0CPSR - address 0x4004 0010, SSP1CPSR - address 0x4005 8010 */
MACRUM	6:40e873bbc5f7	1111	#define SSP0CPSR_CPSDVSR_MASK 0x00FF // This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.
MACRUM	6:40e873bbc5f7	1112	#define SSP0CPSR_CPSDVSR_SHIFT 0
MACRUM	6:40e873bbc5f7	1113
MACRUM	6:40e873bbc5f7	1114	/* SSP0IMSC - address 0x4004 0014, SSP1IMSC - address 0x4005 8014 */
MACRUM	6:40e873bbc5f7	1115	#define SSP0IMSC_RORIM (1 << 0) // Software should set this bit to enable interrupt when a Receive 0 Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
MACRUM	6:40e873bbc5f7	1116	#define SSP0IMSC_RTIM (1 << 1) // Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
MACRUM	6:40e873bbc5f7	1117	#define SSP0IMSC_RXIM (1 << 2) // Software should set this bit to enable interrupt when the Rx FIFO is at 0 least half full.
MACRUM	6:40e873bbc5f7	1118	#define SSP0IMSC_TXIM (1 << 3) // Software should set this bit to enable interrupt when the Tx FIFO is at 0 least half empty.
MACRUM	6:40e873bbc5f7	1119
MACRUM	6:40e873bbc5f7	1120	/* SSP0RIS - address 0x4004 0018, SSP1RIS - address 0x4005 8018 */
MACRUM	6:40e873bbc5f7	1121	#define SSP0RIS_RORRIS (1 << 0) // This bit is 1 if another frame was completely received while the 0 RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
MACRUM	6:40e873bbc5f7	1122	#define SSP0RIS_RTRIS (1 << 1) // This bit is 1 if the Rx FIFO is not empty, and has not been read 0 for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
MACRUM	6:40e873bbc5f7	1123	#define SSP0RIS_RXRIS (1 << 2) // This bit is 1 if the Rx FIFO is at least half full.
MACRUM	6:40e873bbc5f7	1124	#define SSP0RIS_TXRIS (1 << 3) // This bit is 1 if the Tx FIFO is at least half empty.
MACRUM	6:40e873bbc5f7	1125
MACRUM	6:40e873bbc5f7	1126	/* SSP0MIS - address 0x4004 001C, SSP1MIS - address 0x4005 801C */
MACRUM	6:40e873bbc5f7	1127	#define SSP0MIS_RORMIS (1 << 0) // This bit is 1 if another frame was completely received while the 0 RxFIFO was full, and this interrupt is enabled.
MACRUM	6:40e873bbc5f7	1128	#define SSP0MIS_RTMIS (1 << 1) // This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
MACRUM	6:40e873bbc5f7	1129	#define SSP0MIS_RXMIS (1 << 2) // This bit is 1 if the Rx FIFO is at least half full, and this interrupt 0 is enabled.
MACRUM	6:40e873bbc5f7	1130	#define SSP0MIS_TXMIS (1 << 3) // This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.
MACRUM	6:40e873bbc5f7	1131
MACRUM	6:40e873bbc5f7	1132	/* SSP0ICR - address 0x4004 0020, SSP1ICR - address 0x4005 8020 */
MACRUM	6:40e873bbc5f7	1133	#define SSP0ICR_RORIC (1 << 0) // Writing a 1 to this bit clears the "frame was received when RxFIFO was full" interrupt.
MACRUM	6:40e873bbc5f7	1134	#define SSP0ICR_RTIC (1 << 1) // Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
MACRUM	6:40e873bbc5f7	1135
MACRUM	6:40e873bbc5f7	1136	/* I2C0CONSET - address 0x4000 0000 */
MACRUM	6:40e873bbc5f7	1137	#define I2C0CONSET_AA (1 << 2) // Assert acknowledge flag.
MACRUM	6:40e873bbc5f7	1138	#define I2C0CONSET_SI (1 << 3) // I2C interrupt flag.
MACRUM	6:40e873bbc5f7	1139	#define I2C0CONSET_STO (1 << 4) // STOP flag.
MACRUM	6:40e873bbc5f7	1140	#define I2C0CONSET_STA (1 << 5) // START flag.
MACRUM	6:40e873bbc5f7	1141	#define I2C0CONSET_I2EN (1 << 6) // I2C interface enable. Reserved. The value read from a reserved bit is not defined.
MACRUM	6:40e873bbc5f7	1142
MACRUM	6:40e873bbc5f7	1143	/* I2C0STAT - 0x4000 0004 */
MACRUM	6:40e873bbc5f7	1144	#define I2C0STAT_STATUS_MASK 0x00F8 // These bits give the actual status information about the I2 C interface. Reserved. The value read from a reserved bit is not defined.
MACRUM	6:40e873bbc5f7	1145	#define I2C0STAT_STATUS_SHIFT 3
MACRUM	6:40e873bbc5f7	1146
MACRUM	6:40e873bbc5f7	1147	/* I2C0DAT - 0x4000 0008 */
MACRUM	6:40e873bbc5f7	1148	#define I2C0DAT_DATA_MASK 0x00FF // This register holds data values that have been received or are to 0 be transmitted. Reserved. The value read from a reserved bit is not defined.
MACRUM	6:40e873bbc5f7	1149	#define I2C0DAT_DATA_SHIFT 0
MACRUM	6:40e873bbc5f7	1150
MACRUM	6:40e873bbc5f7	1151	/* I2C0ADR0 - 0x4000 000C */
MACRUM	6:40e873bbc5f7	1152	#define I2C0ADR0_GC (1 << 0) // General Call enable bit.
MACRUM	6:40e873bbc5f7	1153	#define I2C0ADR0_ADDRESS_MASK 0x00FE // The I2C device address for slave mode. Reserved. The value read from a reserved bit is not defined.
MACRUM	6:40e873bbc5f7	1154	#define I2C0ADR0_ADDRESS_SHIFT 1
MACRUM	6:40e873bbc5f7	1155
MACRUM	6:40e873bbc5f7	1156	/* I2C0SCLH - address 0x4000 0010 */
MACRUM	6:40e873bbc5f7	1157	#define I2C0SCLH_SCLH_MASK 0xFFFF // Count for SCL HIGH time period selection.
MACRUM	6:40e873bbc5f7	1158	#define I2C0SCLH_SCLH_SHIFT 0
MACRUM	6:40e873bbc5f7	1159
MACRUM	6:40e873bbc5f7	1160	/* I2C0SCLL - 0x4000 0014 */
MACRUM	6:40e873bbc5f7	1161	#define I2C0SCLL_SCLL_MASK 0xFFFF // Count for SCL low time period selection.
MACRUM	6:40e873bbc5f7	1162	#define I2C0SCLL_SCLL_SHIFT 0
MACRUM	6:40e873bbc5f7	1163
MACRUM	6:40e873bbc5f7	1164	/* I2C0CONCLR - 0x4000 0018 */
MACRUM	6:40e873bbc5f7	1165	#define I2C0CONCLR_AAC (1 << 2) // Assert acknowledge Clear bit.
MACRUM	6:40e873bbc5f7	1166	#define I2C0CONCLR_SIC (1 << 3) // I2C interrupt Clear bit.
MACRUM	6:40e873bbc5f7	1167	#define I2C0CONCLR_STAC (1 << 5) // START flag Clear bit.
MACRUM	6:40e873bbc5f7	1168	#define I2C0CONCLR_I2ENC (1 << 6) // I2C interface Disable bit. Reserved. The value read from a reserved bit is not defined.
MACRUM	6:40e873bbc5f7	1169
MACRUM	6:40e873bbc5f7	1170	/* I2C0MMCTRL - 0x4000 001C */
MACRUM	6:40e873bbc5f7	1171	#define I2C0MMCTRL_MM_ENA (1 << 0) // Monitor mode enable.
MACRUM	6:40e873bbc5f7	1172	#define I2C0MMCTRL_ENA_SCL (1 << 1) // SCL output enable.
MACRUM	6:40e873bbc5f7	1173
MACRUM	6:40e873bbc5f7	1174	/* I2C0DATA_BUFFER - 0x4000 002C */
MACRUM	6:40e873bbc5f7	1175	#define I2C0DATA_BUFFER_DATA_MASK 0x00FF // This register holds contents of the 8 MSBs of the DAT shift register. Reserved. The value read from a reserved bit is not defined.
MACRUM	6:40e873bbc5f7	1176	#define I2C0DATA_BUFFER_DATA_SHIFT 0
MACRUM	6:40e873bbc5f7	1177
MACRUM	6:40e873bbc5f7	1178	/* CANCNTL, address 0x4005 0000 */
MACRUM	6:40e873bbc5f7	1179	#define CANCNTL_INIT (1 << 0) // Initialization
MACRUM	6:40e873bbc5f7	1180	#define CANCNTL_IE (1 << 1) // Module interrupt enable
MACRUM	6:40e873bbc5f7	1181	#define CANCNTL_SIE (1 << 2) // Status change interrupt enable
MACRUM	6:40e873bbc5f7	1182	#define CANCNTL_EIE (1 << 3) // Error interrupt enable
MACRUM	6:40e873bbc5f7	1183	#define CANCNTL_DAR (1 << 5) // Disable automatic retransmission
MACRUM	6:40e873bbc5f7	1184	#define CANCNTL_CCE (1 << 6) // Configuration change enable
MACRUM	6:40e873bbc5f7	1185	#define CANCNTL_TEST (1 << 7) // Test mode enable
MACRUM	6:40e873bbc5f7	1186
MACRUM	6:40e873bbc5f7	1187	/* CANSTAT, address 0x4005 0004 */
MACRUM	6:40e873bbc5f7	1188	#define CANSTAT_LEC_MASK 0x0007 // Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to `0' when a message has been transferred (reception or transmission) without error. The unused code `111' may be written by the CPU to check for updates.
MACRUM	6:40e873bbc5f7	1189	#define CANSTAT_LEC_SHIFT 0
MACRUM	6:40e873bbc5f7	1190	#define CANSTAT_TXOK (1 << 3) // Transmitted a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
MACRUM	6:40e873bbc5f7	1191	#define CANSTAT_RXOK (1 << 4) // Received a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
MACRUM	6:40e873bbc5f7	1192	#define CANSTAT_EPASS (1 << 5) // Error passive
MACRUM	6:40e873bbc5f7	1193	#define CANSTAT_EWARN (1 << 6) // Warning status
MACRUM	6:40e873bbc5f7	1194	#define CANSTAT_BOFF (1 << 7) // Busoff status
MACRUM	6:40e873bbc5f7	1195
MACRUM	6:40e873bbc5f7	1196	/* CANEC, address 0x4005 0008 */
MACRUM	6:40e873bbc5f7	1197	#define CANEC_TEC_MASK 0x00FF // Transmit error counter Current value of the transmit error counter (maximum value 255)
MACRUM	6:40e873bbc5f7	1198	#define CANEC_TEC_SHIFT 0
MACRUM	6:40e873bbc5f7	1199	#define CANEC_REC_MASK 0x7F00 // Receive error counter Current value of the receive error counter (maximum value 127).
MACRUM	6:40e873bbc5f7	1200	#define CANEC_REC_SHIFT 8
MACRUM	6:40e873bbc5f7	1201	#define CANEC_RP (1 << 15) // Receive error passive
MACRUM	6:40e873bbc5f7	1202
MACRUM	6:40e873bbc5f7	1203	/* CANBT, address 0x4005 000C */
MACRUM	6:40e873bbc5f7	1204	#define CANBT_BRP_MASK 0x003F // Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63.[1]
MACRUM	6:40e873bbc5f7	1205	#define CANBT_BRP_SHIFT 0
MACRUM	6:40e873bbc5f7	1206	#define CANBT_SJW_MASK 0x00C0 // (Re)synchronization jump width Valid programmed values are 0 to 3.[1]
MACRUM	6:40e873bbc5f7	1207	#define CANBT_SJW_SHIFT 6
MACRUM	6:40e873bbc5f7	1208	#define CANBT_TSEG1_MASK 0x0F00 // Time segment before the sample point Valid values are 1 to 15.[1]
MACRUM	6:40e873bbc5f7	1209	#define CANBT_TSEG1_SHIFT 8
MACRUM	6:40e873bbc5f7	1210	#define CANBT_TSEG2_MASK 0x7000 // Time segment after the sample point Valid values are 0 to 7.[1]
MACRUM	6:40e873bbc5f7	1211	#define CANBT_TSEG2_SHIFT 12
MACRUM	6:40e873bbc5f7	1212
MACRUM	6:40e873bbc5f7	1213	/* CANINT, address 0x4005 0010 */
MACRUM	6:40e873bbc5f7	1214	#define CANINT_INTID_MASK 0xFFFF // 0x0000 = No interrupt is pending. 0 0x0001 - 0x0020 = Number of message object which caused the interrupt. 0x0021 - 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 - 0xFFFF = Unused
MACRUM	6:40e873bbc5f7	1215	#define CANINT_INTID_SHIFT 0
MACRUM	6:40e873bbc5f7	1216
MACRUM	6:40e873bbc5f7	1217	/* CANTEST, address 0x4005 0014 */
MACRUM	6:40e873bbc5f7	1218	#define CANTEST_BASIC (1 << 2) // Basic mode
MACRUM	6:40e873bbc5f7	1219	#define CANTEST_SILENT (1 << 3) // Silent mode
MACRUM	6:40e873bbc5f7	1220	#define CANTEST_LBACK (1 << 4) // Loop back mode
MACRUM	6:40e873bbc5f7	1221	#define CANTEST_TX_MASK 0x0060 // Control of CAN_TXD pins
MACRUM	6:40e873bbc5f7	1222	#define CANTEST_TX_SHIFT 5
MACRUM	6:40e873bbc5f7	1223	#define CANTEST_RX (1 << 7) // Monitors the actual value of the CAN_RXD pin.
MACRUM	6:40e873bbc5f7	1224
MACRUM	6:40e873bbc5f7	1225	/* CANBRPE, address 0x4005 0018 */
MACRUM	6:40e873bbc5f7	1226	#define CANBRPE_BRPE_MASK 0x000F // Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0 to 15.
MACRUM	6:40e873bbc5f7	1227	#define CANBRPE_BRPE_SHIFT 0
MACRUM	6:40e873bbc5f7	1228
MACRUM	6:40e873bbc5f7	1229	/* CANIF1_CMDREQ, address 0x4005 0020 and CANIF2_CMDREQ, address 0x4005 0080 */
MACRUM	6:40e873bbc5f7	1230	#define CANIFn_CMDREQ_MN_MASK 0x003F // Message number 0x01 - 0x20 = Valid message numbers. The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 - 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]
MACRUM	6:40e873bbc5f7	1231	#define CANIFn_CMDREQ_MN_SHIFT 0
MACRUM	6:40e873bbc5f7	1232	#define CANIFn_CMDREQ_BUSY (1 << 15) // BUSY flag
MACRUM	6:40e873bbc5f7	1233
MACRUM	6:40e873bbc5f7	1234	/* CANIF1_CMDMSK, address 0x4005 0024 and CANIF2_CMDMSK, address 0x4005 0084 */
MACRUM	6:40e873bbc5f7	1235	#define CANIFn_CMDMSK_DATA_B (1 << 0) // Access data bytes 4-7
MACRUM	6:40e873bbc5f7	1236	#define CANIFn_CMDMSK_DATA_A (1 << 1) // Access data bytes 0-3
MACRUM	6:40e873bbc5f7	1237	#define CANIFn_CMDMSK_TXRQST (1 << 2) // Access transmission request bit (Write direction)
MACRUM	6:40e873bbc5f7	1238	#define CANIFn_CMDMSK_NEWDAT (1 << 2) // Access new data bit (Read direction)
MACRUM	6:40e873bbc5f7	1239	#define CANIFn_CMDMSK_CLRINTPND (1 << 3) // This bit is ignored in the write direction.
MACRUM	6:40e873bbc5f7	1240	#define CANIFn_CMDMSK_CTRL (1 << 4) // Access control bits
MACRUM	6:40e873bbc5f7	1241	#define CANIFn_CMDMSK_ARB (1 << 5) // Access arbitration bits
MACRUM	6:40e873bbc5f7	1242	#define CANIFn_CMDMSK_MASK (1 << 6) // Access mask bits
MACRUM	6:40e873bbc5f7	1243	#define CANIFn_CMDMSK_WR (1 << 7) // Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.
MACRUM	6:40e873bbc5f7	1244	#define CANIFn_CMDMSK_RD (0 << 7) // Read transfer Read data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.
MACRUM	6:40e873bbc5f7	1245
MACRUM	6:40e873bbc5f7	1246	/* CANIF1_MSK1, address 0x4005 0028 and CANIF2_MASK1, address 0x4005 0088 */
MACRUM	6:40e873bbc5f7	1247	#define CANIFn_MSK1_MSK_MASK 0xFFFF // Identifier mask
MACRUM	6:40e873bbc5f7	1248	#define CANIFn_MSK1_MSK_SHIFT 0
MACRUM	6:40e873bbc5f7	1249
MACRUM	6:40e873bbc5f7	1250	/* CANIF1_MSK2, address 0x4005 002C and CANIF2_MASK2, address 0x4005 008C */
MACRUM	6:40e873bbc5f7	1251	#define CANIFn_MSK2_MSK_MASK 0x1FFF // Identifier mask
MACRUM	6:40e873bbc5f7	1252	#define CANIFn_MSK2_MSK_SHIFT 0
MACRUM	6:40e873bbc5f7	1253	#define CANIFn_MSK2_MDIR (1 << 14) // Mask message direction
MACRUM	6:40e873bbc5f7	1254	#define CANIFn_MSK2_MXTD (1 << 15) // Mask extend identifier
MACRUM	6:40e873bbc5f7	1255
MACRUM	6:40e873bbc5f7	1256	/* CANIF1_ARB1, address 0x4005 0030 and CANIF2_ARB1, address 0x4005 0090 */
MACRUM	6:40e873bbc5f7	1257	#define CANIFn_ARB1_ID_MASK 0xFFFF // Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)
MACRUM	6:40e873bbc5f7	1258	#define CANIFn_ARB1_ID_SHIFT 0
MACRUM	6:40e873bbc5f7	1259
MACRUM	6:40e873bbc5f7	1260	/* CANIF1_ARB2, address 0x4005 0034 and CANIF2_ARB2, address 0x4005 0094 */
MACRUM	6:40e873bbc5f7	1261	#define CANIFn_ARB2_ID_MASK 0x1FFF // Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)
MACRUM	6:40e873bbc5f7	1262	#define CANIFn_ARB2_ID_SHIFT 0
MACRUM	6:40e873bbc5f7	1263	#define CANIFn_ARB2_DIR (1 << 13) // Message direction
MACRUM	6:40e873bbc5f7	1264	#define CANIFn_ARB2_XTD (1 << 14) // Extend identifier
MACRUM	6:40e873bbc5f7	1265	#define CANIFn_ARB2_MSGVAL (1 << 15) // Message valid Remark: The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.
MACRUM	6:40e873bbc5f7	1266
MACRUM	6:40e873bbc5f7	1267	/* CANIF1_MCTRL, address 0x4005 0038 and CANIF2_MCTRL, address 0x4005 0098 */
MACRUM	6:40e873bbc5f7	1268	#define CANIFn_MCTRL_DLC_MASK 0x000F // Data length code Remark: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 - 1000 = Data frame has 0 - 8 data bytes. 1001 - 1111 = Data frame has 8 data bytes.
MACRUM	6:40e873bbc5f7	1269	#define CANIFn_MCTRL_DLC_SHIFT 0
MACRUM	6:40e873bbc5f7	1270	#define CANIFn_MCTRL_EOB (1 << 7) // End of buffer
MACRUM	6:40e873bbc5f7	1271	#define CANIFn_MCTRL_TXRQST (1 << 8) // Transmit request
MACRUM	6:40e873bbc5f7	1272	#define CANIFn_MCTRL_RMTEN (1 << 9) // Remote enable
MACRUM	6:40e873bbc5f7	1273	#define CANIFn_MCTRL_RXIE (1 << 10) // Receive interrupt enable
MACRUM	6:40e873bbc5f7	1274	#define CANIFn_MCTRL_TXIE (1 << 11) // Transmit interrupt enable
MACRUM	6:40e873bbc5f7	1275	#define CANIFn_MCTRL_UMASK (1 << 12) // Use acceptance mask Remark: If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.
MACRUM	6:40e873bbc5f7	1276	#define CANIFn_MCTRL_INTPND (1 << 13) // Interrupt pending
MACRUM	6:40e873bbc5f7	1277	#define CANIFn_MCTRL_MSGLST (1 << 14) // Message lost (only valid for message objects in the direction receive).
MACRUM	6:40e873bbc5f7	1278	#define CANIFn_MCTRL_NEWDAT (1 << 15) // New data
MACRUM	6:40e873bbc5f7	1279
MACRUM	6:40e873bbc5f7	1280	/* CANIF1_DA1, address 0x4005 003C and CANIF2_DA1, address 0x4005 009C */
MACRUM	6:40e873bbc5f7	1281	#define CANIFn_DA1_DATA0_MASK 0x00FF // Data byte 0
MACRUM	6:40e873bbc5f7	1282	#define CANIFn_DA1_DATA0_SHIFT 0
MACRUM	6:40e873bbc5f7	1283	#define CANIFn_DA1_DATA1_MASK 0xFF00 // Data byte 1
MACRUM	6:40e873bbc5f7	1284	#define CANIFn_DA1_DATA1_SHIFT 8
MACRUM	6:40e873bbc5f7	1285
MACRUM	6:40e873bbc5f7	1286	/* CANIF1_DA2, address 0x4005 0040 and CANIF2_DA2, address 0x4005 00A0 */
MACRUM	6:40e873bbc5f7	1287	#define CANIFn_DA2_DATA2_MASK 0x00FF // Data byte 2
MACRUM	6:40e873bbc5f7	1288	#define CANIFn_DA2_DATA2_SHIFT 0
MACRUM	6:40e873bbc5f7	1289	#define CANIFn_DA2_DATA3_MASK 0xFF00 // Data byte 3
MACRUM	6:40e873bbc5f7	1290	#define CANIFn_DA2_DATA3_SHIFT 8
MACRUM	6:40e873bbc5f7	1291
MACRUM	6:40e873bbc5f7	1292	/* CANIF1_DB1, address 0x4005 0044 and CANIF2_DB1, address 0x4005 00A4 */
MACRUM	6:40e873bbc5f7	1293	#define CANIFn_DB1_DATA4_MASK 0x00FF // Data byte 4
MACRUM	6:40e873bbc5f7	1294	#define CANIFn_DB1_DATA4_SHIFT 0
MACRUM	6:40e873bbc5f7	1295	#define CANIFn_DB1_DATA5_MASK 0xFF00 // Data byte 5
MACRUM	6:40e873bbc5f7	1296	#define CANIFn_DB1_DATA5_SHIFT 8
MACRUM	6:40e873bbc5f7	1297
MACRUM	6:40e873bbc5f7	1298	/* CANIF1_DB2, address 0x4005 0048 and CANIF2_DB2, address 0x4005 00A8 */
MACRUM	6:40e873bbc5f7	1299	#define CANIFn_DB2_DATA6_MASK 0x00FF // Data byte 6
MACRUM	6:40e873bbc5f7	1300	#define CANIFn_DB2_DATA6_SHIFT 0
MACRUM	6:40e873bbc5f7	1301	#define CANIFn_DB2_DATA7_MASK 0xFF00 // Data byte 7
MACRUM	6:40e873bbc5f7	1302	#define CANIFn_DB2_DATA7_SHIFT 8
MACRUM	6:40e873bbc5f7	1303
MACRUM	6:40e873bbc5f7	1304	/* CANTXREQ1, address 0x4005 0100 */
MACRUM	6:40e873bbc5f7	1305	#define CANTXREQ1_TXRQST_MASK 0xFFFF // Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. Reserved
MACRUM	6:40e873bbc5f7	1306	#define CANTXREQ1_TXRQST_SHIFT 0
MACRUM	6:40e873bbc5f7	1307
MACRUM	6:40e873bbc5f7	1308	/* CANTXREQ2, address 0x4005 0104 */
MACRUM	6:40e873bbc5f7	1309	#define CANTXREQ2_TXRQST_MASK 0xFFFF // Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. Reserved
MACRUM	6:40e873bbc5f7	1310	#define CANTXREQ2_TXRQST_SHIFT 0
MACRUM	6:40e873bbc5f7	1311
MACRUM	6:40e873bbc5f7	1312	/* CANND1, address 0x4005 0120 */
MACRUM	6:40e873bbc5f7	1313	#define CANND1_NEWDAT_MASK 0xFFFF // New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.
MACRUM	6:40e873bbc5f7	1314	#define CANND1_NEWDAT_SHIFT 0
MACRUM	6:40e873bbc5f7	1315
MACRUM	6:40e873bbc5f7	1316	/* CANND2, address 0x4005 0124 */
MACRUM	6:40e873bbc5f7	1317	#define CANND2_NEWDAT_MASK 0xFFFF // New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.
MACRUM	6:40e873bbc5f7	1318	#define CANND2_NEWDAT_SHIFT 0
MACRUM	6:40e873bbc5f7	1319
MACRUM	6:40e873bbc5f7	1320	/* CANIR1, address 0x4005 0140 */
MACRUM	6:40e873bbc5f7	1321	#define CANIR1_INTPND_INTERRUPT_MASK 0xFFFF // pending bits of message objects 16 to 1. essage object is ignored by the message essage object is the source of an interrupt. Reserved
MACRUM	6:40e873bbc5f7	1322	#define CANIR1_INTPND_INTERRUPT_SHIFT 0
MACRUM	6:40e873bbc5f7	1323
MACRUM	6:40e873bbc5f7	1324	/* CANIR2, addresses 0x4005 0144 */
MACRUM	6:40e873bbc5f7	1325	#define CANIR2_INTPND_MASK 0xFFFF // Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt. Reserved
MACRUM	6:40e873bbc5f7	1326	#define CANIR2_INTPND_SHIFT 0
MACRUM	6:40e873bbc5f7	1327
MACRUM	6:40e873bbc5f7	1328	/* CANMSGV1, addresses 0x4005 0160 */
MACRUM	6:40e873bbc5f7	1329	#define CANMSGV1_MSGVAL_MASK 0xFFFF // Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. Reserved
MACRUM	6:40e873bbc5f7	1330	#define CANMSGV1_MSGVAL_SHIFT 0
MACRUM	6:40e873bbc5f7	1331
MACRUM	6:40e873bbc5f7	1332	/* CANMSGV2, address 0x4005 0164 */
MACRUM	6:40e873bbc5f7	1333	#define CANMSGV2_MSGVAL_MASK 0xFFFF // Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. Reserved
MACRUM	6:40e873bbc5f7	1334	#define CANMSGV2_MSGVAL_SHIFT 0
MACRUM	6:40e873bbc5f7	1335
MACRUM	6:40e873bbc5f7	1336	/* CANCLKDIV, address 0x4005 0180 */
MACRUM	6:40e873bbc5f7	1337	#define CANCLKDIV_CLKDIVVAL_MASK 0x000F // Clock divider value. CAN_CLK = PCLK/(CLKDIVVAL +1) 0000: CAN_CLK = PCLK divided by 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = PCLK divided by 3 0011: CAN_CLK = PCLK divided by 4. ... 1111: CAN_CLK = PCLK divided by 16.
MACRUM	6:40e873bbc5f7	1338	#define CANCLKDIV_CLKDIVVAL_SHIFT 0
MACRUM	6:40e873bbc5f7	1339
MACRUM	6:40e873bbc5f7	1340	/* TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000 */
MACRUM	6:40e873bbc5f7	1341	#define TMR16B0IR_MR0 (1 << 0) // Interrupt flag for match channel 0.
MACRUM	6:40e873bbc5f7	1342	#define TMR16B0IR_MR1 (1 << 1) // Interrupt flag for match channel 1.
MACRUM	6:40e873bbc5f7	1343	#define TMR16B0IR_MR2 (1 << 2) // Interrupt flag for match channel 2.
MACRUM	6:40e873bbc5f7	1344	#define TMR16B0IR_MR3 (1 << 3) // Interrupt flag for match channel 3.
MACRUM	6:40e873bbc5f7	1345	#define TMR16B0IR_CR0 (1 << 4) // Interrupt flag for capture channel 0 event.
MACRUM	6:40e873bbc5f7	1346
MACRUM	6:40e873bbc5f7	1347	/* TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR - address 0x4001 0004 */
MACRUM	6:40e873bbc5f7	1348	#define TMR16B0TCR_CEN (1 << 0) // Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
MACRUM	6:40e873bbc5f7	1349	#define TMR16B0TCR_CRST (1 << 1) // Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
MACRUM	6:40e873bbc5f7	1350
MACRUM	6:40e873bbc5f7	1351	/* TMR16B0TC, address 0x4000 C008 and TMR16B1TC 0x4001 0008 */
MACRUM	6:40e873bbc5f7	1352	#define TMR16B0TC_TC_MASK 0xFFFF // Timer counter value.
MACRUM	6:40e873bbc5f7	1353	#define TMR16B0TC_TC_SHIFT 0
MACRUM	6:40e873bbc5f7	1354
MACRUM	6:40e873bbc5f7	1355	/* TMR16B0PR, address 0x4000 C00C and TMR16B1PR 0x4001 000C */
MACRUM	6:40e873bbc5f7	1356	#define TMR16B0PR_PR_MASK 0xFFFF // Prescale max value.
MACRUM	6:40e873bbc5f7	1357	#define TMR16B0PR_PR_SHIFT 0
MACRUM	6:40e873bbc5f7	1358
MACRUM	6:40e873bbc5f7	1359	/* TMR16B0PC, address 0x4001 C010 and TMR16B1PC 0x4000 0010 */
MACRUM	6:40e873bbc5f7	1360	#define TMR16B0PC_PC_MASK 0xFFFF // Prescale counter value.
MACRUM	6:40e873bbc5f7	1361	#define TMR16B0PC_PC_SHIFT 0
MACRUM	6:40e873bbc5f7	1362
MACRUM	6:40e873bbc5f7	1363	/* TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014 */
MACRUM	6:40e873bbc5f7	1364	#define TMR16B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1365	#define TMR16B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
MACRUM	6:40e873bbc5f7	1366	#define TMR16B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1367	#define TMR16B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1368	#define TMR16B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
MACRUM	6:40e873bbc5f7	1369	#define TMR16B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1370	#define TMR16B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1371	#define TMR16B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
MACRUM	6:40e873bbc5f7	1372	#define TMR16B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1373	#define TMR16B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1374	#define TMR16B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
MACRUM	6:40e873bbc5f7	1375	#define TMR16B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1376
MACRUM	6:40e873bbc5f7	1377	/* TMR16B0MR0 to 3, addresses 0x4000 C018 to 24 and TMR16B1MR0 to 3, addresses 0x4001 0018 to 24 */
MACRUM	6:40e873bbc5f7	1378	#define TMR16B0MR0_to_3_MATCH_MASK 0xFFFF // Timer counter match value.
MACRUM	6:40e873bbc5f7	1379	#define TMR16B0MR0_to_3_MATCH_SHIFT 0
MACRUM	6:40e873bbc5f7	1380
MACRUM	6:40e873bbc5f7	1381	/* TMR16B0CCR - address 0x4000 C028 and TMR16B1CCR - address 0x4001 0028 */
MACRUM	6:40e873bbc5f7	1382	#define TMR16B0CCR_CAP0RE (1 << 0) // Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
MACRUM	6:40e873bbc5f7	1383	#define TMR16B0CCR_CAP0FE (1 << 1) // Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
MACRUM	6:40e873bbc5f7	1384	#define TMR16B0CCR_CAP0I (1 << 2) // Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.
MACRUM	6:40e873bbc5f7	1385
MACRUM	6:40e873bbc5f7	1386	/* TMR16B0CR0, address 0x4000 C02C and TMR16B1CR0, address 0x4001 002C */
MACRUM	6:40e873bbc5f7	1387	#define TMR16B0CR0_CAP_MASK 0xFFFF // Timer counter capture value.
MACRUM	6:40e873bbc5f7	1388	#define TMR16B0CR0_CAP_SHIFT 0
MACRUM	6:40e873bbc5f7	1389
MACRUM	6:40e873bbc5f7	1390	/* TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address 0x4001 003C */
MACRUM	6:40e873bbc5f7	1391	#define TMR16B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1392	#define TMR16B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1393	#define TMR16B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output match channel 2, whether or not 0 this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1394	#define TMR16B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output of match channel 3. When a match 0 occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.
MACRUM	6:40e873bbc5f7	1395	#define TMR16B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
MACRUM	6:40e873bbc5f7	1396	#define TMR16B0EMR_EMC0_SHIFT 4
MACRUM	6:40e873bbc5f7	1397	#define TMR16B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
MACRUM	6:40e873bbc5f7	1398	#define TMR16B0EMR_EMC1_SHIFT 6
MACRUM	6:40e873bbc5f7	1399	#define TMR16B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
MACRUM	6:40e873bbc5f7	1400	#define TMR16B0EMR_EMC2_SHIFT 8
MACRUM	6:40e873bbc5f7	1401	#define TMR16B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
MACRUM	6:40e873bbc5f7	1402	#define TMR16B0EMR_EMC3_SHIFT 10
MACRUM	6:40e873bbc5f7	1403
MACRUM	6:40e873bbc5f7	1404	/* TMR16B0CTCR - address 0x4000 C070 and TMR16B1CTCR - address 0x4001 0070 */
MACRUM	6:40e873bbc5f7	1405	#define TMR16B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK 00 edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
MACRUM	6:40e873bbc5f7	1406	#define TMR16B0CTCR_CTM_SHIFT 0
MACRUM	6:40e873bbc5f7	1407
MACRUM	6:40e873bbc5f7	1408	/* TMR16B0PWMC - address 0x4000 C074 and TMR16B1PWMC- address 0x4001 0074 */
MACRUM	6:40e873bbc5f7	1409	#define TMR16B0PWMC_PWMEN0 (1 << 0) // PWM channel0 enable
MACRUM	6:40e873bbc5f7	1410	#define TMR16B0PWMC_PWMEN1 (1 << 1) // PWM channel1 enable
MACRUM	6:40e873bbc5f7	1411	#define TMR16B0PWMC_PWMEN2 (1 << 2) // PWM channel2 enable
MACRUM	6:40e873bbc5f7	1412	#define TMR16B0PWMC_PWMEN3 (1 << 3) // PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.
MACRUM	6:40e873bbc5f7	1413
MACRUM	6:40e873bbc5f7	1414	/* TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000 */
MACRUM	6:40e873bbc5f7	1415	#define TMR16B0IR_MR0INT (1 << 0) // Interrupt flag for match channel 0.
MACRUM	6:40e873bbc5f7	1416	#define TMR16B0IR_MR1INT (1 << 1) // Interrupt flag for match channel 1.
MACRUM	6:40e873bbc5f7	1417	#define TMR16B0IR_MR2INT (1 << 2) // Interrupt flag for match channel 2.
MACRUM	6:40e873bbc5f7	1418	#define TMR16B0IR_MR3INT (1 << 3) // Interrupt flag for match channel 3.
MACRUM	6:40e873bbc5f7	1419	#define TMR16B0IR_CR0INT (1 << 4) // Interrupt flag for capture channel 0 event.
MACRUM	6:40e873bbc5f7	1420	#define TMR16B0IR_CR1INT (1 << 5) // Interrupt flag for capture channel 1 event.
MACRUM	6:40e873bbc5f7	1421
MACRUM	6:40e873bbc5f7	1422	/* TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR - address 0x4001 0004 */
MACRUM	6:40e873bbc5f7	1423	#define TMR16B0TCR_CEN (1 << 0) // Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
MACRUM	6:40e873bbc5f7	1424	#define TMR16B0TCR_CRST (1 << 1) // Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
MACRUM	6:40e873bbc5f7	1425
MACRUM	6:40e873bbc5f7	1426	/* TMR16B0TC, address 0x4000 C008 and TMR16B1TC 0x4001 0008 */
MACRUM	6:40e873bbc5f7	1427	#define TMR16B0TC_TC_MASK 0xFFFF // Timer counter value.
MACRUM	6:40e873bbc5f7	1428	#define TMR16B0TC_TC_SHIFT 0
MACRUM	6:40e873bbc5f7	1429
MACRUM	6:40e873bbc5f7	1430	/* TMR16B0PR, address 0x4000 C00C and TMR16B1PR 0x4001 000C */
MACRUM	6:40e873bbc5f7	1431	#define TMR16B0PR_PR_MASK 0xFFFF // Prescale max value.
MACRUM	6:40e873bbc5f7	1432	#define TMR16B0PR_PR_SHIFT 0
MACRUM	6:40e873bbc5f7	1433
MACRUM	6:40e873bbc5f7	1434	/* TMR16B0PC, address 0x4001 C010 and TMR16B1PC 0x4000 0010 */
MACRUM	6:40e873bbc5f7	1435	#define TMR16B0PC_PC_MASK 0xFFFF // Prescale counter value.
MACRUM	6:40e873bbc5f7	1436	#define TMR16B0PC_PC_SHIFT 0
MACRUM	6:40e873bbc5f7	1437
MACRUM	6:40e873bbc5f7	1438	/* TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014 */
MACRUM	6:40e873bbc5f7	1439	#define TMR16B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1440	#define TMR16B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
MACRUM	6:40e873bbc5f7	1441	#define TMR16B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1442	#define TMR16B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1443	#define TMR16B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
MACRUM	6:40e873bbc5f7	1444	#define TMR16B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1445	#define TMR16B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1446	#define TMR16B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
MACRUM	6:40e873bbc5f7	1447	#define TMR16B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1448	#define TMR16B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1449	#define TMR16B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
MACRUM	6:40e873bbc5f7	1450	#define TMR16B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1451
MACRUM	6:40e873bbc5f7	1452	/* TMR16B0MR0 to 3, addresses 0x4000 C018 to 24 and TMR16B1MR0 to 3, addresses 0x4001 0018 to 24 */
MACRUM	6:40e873bbc5f7	1453	#define TMR16B0MR0_to_3_MATCH_MASK 0xFFFF // Timer counter match value.
MACRUM	6:40e873bbc5f7	1454	#define TMR16B0MR0_to_3_MATCH_SHIFT 0
MACRUM	6:40e873bbc5f7	1455
MACRUM	6:40e873bbc5f7	1456	/* TMR16B0CCR - address 0x4000 C028 and TMR16B1CCR - address 0x4001 0028 */
MACRUM	6:40e873bbc5f7	1457	#define TMR16B0CCR_CAP0RE (1 << 0) // Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
MACRUM	6:40e873bbc5f7	1458	#define TMR16B0CCR_CAP0FE (1 << 1) // Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
MACRUM	6:40e873bbc5f7	1459	#define TMR16B0CCR_CAP0I (1 << 2) // Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.
MACRUM	6:40e873bbc5f7	1460	#define TMR16B0CCR_CAP1RE (1 << 3) // Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.
MACRUM	6:40e873bbc5f7	1461	#define TMR16B0CCR_CAP1FE (1 << 4) // Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will 0 cause CR1 to be loaded with the contents of TC.
MACRUM	6:40e873bbc5f7	1462	#define TMR16B0CCR_CAP1I (1 << 5) // Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt.
MACRUM	6:40e873bbc5f7	1463
MACRUM	6:40e873bbc5f7	1464	/* TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address 0x4001 003C */
MACRUM	6:40e873bbc5f7	1465	#define TMR16B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1466	#define TMR16B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1467	#define TMR16B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output match channel 2, whether or not 0 this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1468	#define TMR16B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output of match channel 3. When a match 0 occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.
MACRUM	6:40e873bbc5f7	1469	#define TMR16B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
MACRUM	6:40e873bbc5f7	1470	#define TMR16B0EMR_EMC0_SHIFT 4
MACRUM	6:40e873bbc5f7	1471	#define TMR16B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
MACRUM	6:40e873bbc5f7	1472	#define TMR16B0EMR_EMC1_SHIFT 6
MACRUM	6:40e873bbc5f7	1473	#define TMR16B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
MACRUM	6:40e873bbc5f7	1474	#define TMR16B0EMR_EMC2_SHIFT 8
MACRUM	6:40e873bbc5f7	1475	#define TMR16B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
MACRUM	6:40e873bbc5f7	1476	#define TMR16B0EMR_EMC3_SHIFT 10
MACRUM	6:40e873bbc5f7	1477
MACRUM	6:40e873bbc5f7	1478	/* TMR16B0CTCR - address 0x4000 C070 and TMR16B1CTCR - address 0x4001 0070 */
MACRUM	6:40e873bbc5f7	1479	#define TMR16B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK 00 edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
MACRUM	6:40e873bbc5f7	1480	#define TMR16B0CTCR_CTM_SHIFT 0
MACRUM	6:40e873bbc5f7	1481	#define TMR16B0CTCR_SELCC_MASK 0x00E0 // When bit 4 is one, these bits select which capture input edge 0 will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.
MACRUM	6:40e873bbc5f7	1482	#define TMR16B0CTCR_SELCC_SHIFT 5
MACRUM	6:40e873bbc5f7	1483
MACRUM	6:40e873bbc5f7	1484	/* TMR16B0PWMC - address 0x4000 C074 and TMR16B1PWMC- address 0x4001 0074 */
MACRUM	6:40e873bbc5f7	1485	#define TMR16B0PWMC_PWMEN0 (1 << 0) // PWM channel0 enable
MACRUM	6:40e873bbc5f7	1486	#define TMR16B0PWMC_PWMEN1 (1 << 1) // PWM channel1 enable
MACRUM	6:40e873bbc5f7	1487	#define TMR16B0PWMC_PWMEN2 (1 << 2) // PWM channel2 enable
MACRUM	6:40e873bbc5f7	1488	#define TMR16B0PWMC_PWMEN3 (1 << 3) // PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.
MACRUM	6:40e873bbc5f7	1489
MACRUM	6:40e873bbc5f7	1490	/* TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000 */
MACRUM	6:40e873bbc5f7	1491	#define TMR32B0IR_MR0_INTERRUPT (1 << 0) // Interrupt flag for match channel 0.
MACRUM	6:40e873bbc5f7	1492	#define TMR32B0IR_MR1_INTERRUPT (1 << 1) // Interrupt flag for match channel 1.
MACRUM	6:40e873bbc5f7	1493	#define TMR32B0IR_MR2_INTERRUPT (1 << 2) // Interrupt flag for match channel 2.
MACRUM	6:40e873bbc5f7	1494	#define TMR32B0IR_MR3_INTERRUPT (1 << 3) // Interrupt flag for match channel 3.
MACRUM	6:40e873bbc5f7	1495	#define TMR32B0IR_CR0_INTERRUPT (1 << 4) // Interrupt flag for capture channel 0 event.
MACRUM	6:40e873bbc5f7	1496
MACRUM	6:40e873bbc5f7	1497	/* TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR - address 0x4001 8004 */
MACRUM	6:40e873bbc5f7	1498	#define TMR32B0TCR_CEN (1 << 0) // When one, the Timer Counter and Prescale Counter are 0 enabled for counting. When zero, the counters are disabled.
MACRUM	6:40e873bbc5f7	1499	#define TMR32B0TCR_CRST (1 << 1) // When one, the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
MACRUM	6:40e873bbc5f7	1500
MACRUM	6:40e873bbc5f7	1501	/* TMR32B0TC, address 0x4001 4008 and TMR32B1TC 0x4001 8008 */
MACRUM	6:40e873bbc5f7	1502	#define TMR32B0TC_TC_MASK 0xFFFFFFFF // Timer counter value.
MACRUM	6:40e873bbc5f7	1503	#define TMR32B0TC_TC_SHIFT 0
MACRUM	6:40e873bbc5f7	1504
MACRUM	6:40e873bbc5f7	1505	/* TMR32B0PR, address 0x4001 400C and TMR32B1PR 0x4001 800C */
MACRUM	6:40e873bbc5f7	1506	#define TMR32B0PR_PR_MASK 0xFFFFFFFF // Prescale value.
MACRUM	6:40e873bbc5f7	1507	#define TMR32B0PR_PR_SHIFT 0
MACRUM	6:40e873bbc5f7	1508
MACRUM	6:40e873bbc5f7	1509	/* TMR32B0PC, address 0x4001 4010 and TMR32B1PC 0x4001 8010 */
MACRUM	6:40e873bbc5f7	1510	#define TMR32B0PC_PC_MASK 0xFFFFFFFF // Prescale counter value.
MACRUM	6:40e873bbc5f7	1511	#define TMR32B0PC_PC_SHIFT 0
MACRUM	6:40e873bbc5f7	1512
MACRUM	6:40e873bbc5f7	1513	/* TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014 */
MACRUM	6:40e873bbc5f7	1514	#define TMR32B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1515	#define TMR32B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
MACRUM	6:40e873bbc5f7	1516	#define TMR32B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1517	#define TMR32B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1518	#define TMR32B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
MACRUM	6:40e873bbc5f7	1519	#define TMR32B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1520	#define TMR32B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1521	#define TMR32B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
MACRUM	6:40e873bbc5f7	1522	#define TMR32B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1523	#define TMR32B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1524	#define TMR32B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
MACRUM	6:40e873bbc5f7	1525	#define TMR32B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1526
MACRUM	6:40e873bbc5f7	1527	/* TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and TMR32B1MR0 to 3, addresses 0x4001 8018 to 24 */
MACRUM	6:40e873bbc5f7	1528	#define TMR32B0MRn_MATCH_MASK 0xFFFFFFFF // Timer counter match value.
MACRUM	6:40e873bbc5f7	1529	#define TMR32B0MRn_MATCH_SHIFT 0
MACRUM	6:40e873bbc5f7	1530
MACRUM	6:40e873bbc5f7	1531	/* TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address 0x4001 8028 */
MACRUM	6:40e873bbc5f7	1532	#define TMR32B0CCR_CAP0RE (1 << 0) // Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
MACRUM	6:40e873bbc5f7	1533	#define TMR32B0CCR_CAP0FE (1 << 1) // Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
MACRUM	6:40e873bbc5f7	1534	#define TMR32B0CCR_CAP0I (1 << 2) // Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
MACRUM	6:40e873bbc5f7	1535
MACRUM	6:40e873bbc5f7	1536	/* TMR32B0CR0, addresses 0x4001 402C and TMR32B1CR0, addresses 0x4001 802C */
MACRUM	6:40e873bbc5f7	1537	#define TMR32B0CR0_CAP_MASK 0xFFFFFFFF // Timer counter capture value.
MACRUM	6:40e873bbc5f7	1538	#define TMR32B0CR0_CAP_SHIFT 0
MACRUM	6:40e873bbc5f7	1539
MACRUM	6:40e873bbc5f7	1540	/* TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C */
MACRUM	6:40e873bbc5f7	1541	#define TMR32B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1542	#define TMR32B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1543	#define TMR32B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1544	#define TMR32B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1545	#define TMR32B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
MACRUM	6:40e873bbc5f7	1546	#define TMR32B0EMR_EMC0_SHIFT 4
MACRUM	6:40e873bbc5f7	1547	#define TMR32B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
MACRUM	6:40e873bbc5f7	1548	#define TMR32B0EMR_EMC1_SHIFT 6
MACRUM	6:40e873bbc5f7	1549	#define TMR32B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
MACRUM	6:40e873bbc5f7	1550	#define TMR32B0EMR_EMC2_SHIFT 8
MACRUM	6:40e873bbc5f7	1551	#define TMR32B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
MACRUM	6:40e873bbc5f7	1552	#define TMR32B0EMR_EMC3_SHIFT 10
MACRUM	6:40e873bbc5f7	1553
MACRUM	6:40e873bbc5f7	1554	/* TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR - address 0x4001 8070 */
MACRUM	6:40e873bbc5f7	1555	#define TMR32B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
MACRUM	6:40e873bbc5f7	1556	#define TMR32B0CTCR_CTM_SHIFT 0
MACRUM	6:40e873bbc5f7	1557	#define TMR32B0CTCR_CIS_MASK 0x000C // Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
MACRUM	6:40e873bbc5f7	1558	#define TMR32B0CTCR_CIS_SHIFT 2
MACRUM	6:40e873bbc5f7	1559
MACRUM	6:40e873bbc5f7	1560	/* TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC - 0x4001 8074 */
MACRUM	6:40e873bbc5f7	1561	#define TMR32B0PWMC_PWMEN0 (1 << 0) // PWM channel 0 enable
MACRUM	6:40e873bbc5f7	1562	#define TMR32B0PWMC_PWMEN1 (1 << 1) // PWM channel 1 enable
MACRUM	6:40e873bbc5f7	1563	#define TMR32B0PWMC_PWMEN2 (1 << 2) // PWM channel 2 enable
MACRUM	6:40e873bbc5f7	1564	#define TMR32B0PWMC_PWMEN3 (1 << 3) // PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.
MACRUM	6:40e873bbc5f7	1565
MACRUM	6:40e873bbc5f7	1566	/* TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000 */
MACRUM	6:40e873bbc5f7	1567	#define TMR32B0IR_MR0INT (1 << 0) // Interrupt flag for match channel 0.
MACRUM	6:40e873bbc5f7	1568	#define TMR32B0IR_MR1INT (1 << 1) // Interrupt flag for match channel 1.
MACRUM	6:40e873bbc5f7	1569	#define TMR32B0IR_MR2INT (1 << 2) // Interrupt flag for match channel 2.
MACRUM	6:40e873bbc5f7	1570	#define TMR32B0IR_MR3INT (1 << 3) // Interrupt flag for match channel 3.
MACRUM	6:40e873bbc5f7	1571	#define TMR32B0IR_CR0INT (1 << 4) // Interrupt flag for capture channel 0 event.
MACRUM	6:40e873bbc5f7	1572	#define TMR32B0IR_CR1INT (1 << 5) // Interrupt flag for capture channel 1 event.
MACRUM	6:40e873bbc5f7	1573
MACRUM	6:40e873bbc5f7	1574	/* TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR - address 0x4001 8004 */
MACRUM	6:40e873bbc5f7	1575	#define TMR32B0TCR_CEN (1 << 0) // When one, the Timer Counter and Prescale Counter are 0 enabled for counting. When zero, the counters are disabled.
MACRUM	6:40e873bbc5f7	1576	#define TMR32B0TCR_CRST (1 << 1) // When one, the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
MACRUM	6:40e873bbc5f7	1577
MACRUM	6:40e873bbc5f7	1578	/* TMR32B0TC, address 0x4001 4008 and TMR32B1TC 0x4001 8008 */
MACRUM	6:40e873bbc5f7	1579	#define TMR32B0TC_TC_MASK 0xFFFFFFFF // Timer counter value.
MACRUM	6:40e873bbc5f7	1580	#define TMR32B0TC_TC_SHIFT 0
MACRUM	6:40e873bbc5f7	1581
MACRUM	6:40e873bbc5f7	1582	/* TMR32B0PR, address 0x4001 400C and TMR32B1PR 0x4001 800C */
MACRUM	6:40e873bbc5f7	1583	#define TMR32B0PR_PR_MASK 0xFFFFFFFF // Prescale value.
MACRUM	6:40e873bbc5f7	1584	#define TMR32B0PR_PR_SHIFT 0
MACRUM	6:40e873bbc5f7	1585
MACRUM	6:40e873bbc5f7	1586	/* TMR32B0PC, address 0x4001 4010 and TMR32B1PC 0x4001 8010 */
MACRUM	6:40e873bbc5f7	1587	#define TMR32B0PC_PC_MASK 0xFFFFFFFF // Prescale counter value.
MACRUM	6:40e873bbc5f7	1588	#define TMR32B0PC_PC_SHIFT 0
MACRUM	6:40e873bbc5f7	1589
MACRUM	6:40e873bbc5f7	1590	/* TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014 */
MACRUM	6:40e873bbc5f7	1591	#define TMR32B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1592	#define TMR32B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
MACRUM	6:40e873bbc5f7	1593	#define TMR32B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1594	#define TMR32B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1595	#define TMR32B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
MACRUM	6:40e873bbc5f7	1596	#define TMR32B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1597	#define TMR32B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1598	#define TMR32B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
MACRUM	6:40e873bbc5f7	1599	#define TMR32B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1600	#define TMR32B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
MACRUM	6:40e873bbc5f7	1601	#define TMR32B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
MACRUM	6:40e873bbc5f7	1602	#define TMR32B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
MACRUM	6:40e873bbc5f7	1603
MACRUM	6:40e873bbc5f7	1604	/* TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and TMR32B1MR0 to 3, addresses 0x4001 8018 to 24 */
MACRUM	6:40e873bbc5f7	1605	#define TMR32B0MRn_MATCH_MASK 0xFFFFFFFF // Timer counter match value.
MACRUM	6:40e873bbc5f7	1606	#define TMR32B0MRn_MATCH_SHIFT 0
MACRUM	6:40e873bbc5f7	1607
MACRUM	6:40e873bbc5f7	1608	/* TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address 0x4001 8028 */
MACRUM	6:40e873bbc5f7	1609	#define TMR32B0CCR_CAP0RE (1 << 0) // Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
MACRUM	6:40e873bbc5f7	1610	#define TMR32B0CCR_CAP0FE (1 << 1) // Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
MACRUM	6:40e873bbc5f7	1611	#define TMR32B0CCR_CAP0I (1 << 2) // Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
MACRUM	6:40e873bbc5f7	1612	#define TMR32B0CCR_CAP1RE (1 << 3) // Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.
MACRUM	6:40e873bbc5f7	1613	#define TMR32B0CCR_CAP1FE (1 << 4) // Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will 0 cause CR1 to be loaded with the contents of TC.
MACRUM	6:40e873bbc5f7	1614	#define TMR32B0CCR_CAP1I (1 << 5) // Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt.
MACRUM	6:40e873bbc5f7	1615
MACRUM	6:40e873bbc5f7	1616	/* TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C */
MACRUM	6:40e873bbc5f7	1617	#define TMR32B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1618	#define TMR32B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1619	#define TMR32B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1620	#define TMR32B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
MACRUM	6:40e873bbc5f7	1621	#define TMR32B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
MACRUM	6:40e873bbc5f7	1622	#define TMR32B0EMR_EMC0_SHIFT 4
MACRUM	6:40e873bbc5f7	1623	#define TMR32B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
MACRUM	6:40e873bbc5f7	1624	#define TMR32B0EMR_EMC1_SHIFT 6
MACRUM	6:40e873bbc5f7	1625	#define TMR32B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
MACRUM	6:40e873bbc5f7	1626	#define TMR32B0EMR_EMC2_SHIFT 8
MACRUM	6:40e873bbc5f7	1627	#define TMR32B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
MACRUM	6:40e873bbc5f7	1628	#define TMR32B0EMR_EMC3_SHIFT 10
MACRUM	6:40e873bbc5f7	1629
MACRUM	6:40e873bbc5f7	1630	/* TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR - address 0x4001 8070 */
MACRUM	6:40e873bbc5f7	1631	#define TMR32B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
MACRUM	6:40e873bbc5f7	1632	#define TMR32B0CTCR_CTM_SHIFT 0
MACRUM	6:40e873bbc5f7	1633	#define TMR32B0CTCR_CIS_MASK 0x000C // Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
MACRUM	6:40e873bbc5f7	1634	#define TMR32B0CTCR_CIS_SHIFT 2
MACRUM	6:40e873bbc5f7	1635	#define TMR32B0CTCR_ENCC (1 << 4) // Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
MACRUM	6:40e873bbc5f7	1636	#define TMR32B0CTCR_SELCC_MASK 0x00E0 // When bit 4 is one, these bits select which capture input edge 0 will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.
MACRUM	6:40e873bbc5f7	1637	#define TMR32B0CTCR_SELCC_SHIFT 5
MACRUM	6:40e873bbc5f7	1638
MACRUM	6:40e873bbc5f7	1639	/* TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC - 0x4001 8074 */
MACRUM	6:40e873bbc5f7	1640	#define TMR32B0PWMC_PWMEN0 (1 << 0) // PWM channel 0 enable
MACRUM	6:40e873bbc5f7	1641	#define TMR32B0PWMC_PWMEN1 (1 << 1) // PWM channel 1 enable
MACRUM	6:40e873bbc5f7	1642	#define TMR32B0PWMC_PWMEN2 (1 << 2) // PWM channel 2 enable
MACRUM	6:40e873bbc5f7	1643	#define TMR32B0PWMC_PWMEN3 (1 << 3) // PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.
MACRUM	6:40e873bbc5f7	1644
MACRUM	6:40e873bbc5f7	1645	/* WDMOD - 0x4000 4000 */
MACRUM	6:40e873bbc5f7	1646	#define WDMOD_WDEN (1 << 0) // Watchdog enable bit. This bit is Set Only. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one.
MACRUM	6:40e873bbc5f7	1647	#define WDMOD_WDRESET (1 << 1) // Watchdog reset enable bit. This bit is Set Only.
MACRUM	6:40e873bbc5f7	1648	#define WDMOD_WDTOF (1 << 2) // Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1.
MACRUM	6:40e873bbc5f7	1649	#define WDMOD_WDINT (1 << 3) // Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.
MACRUM	6:40e873bbc5f7	1650	#define WDMOD_WDPROTECT (1 << 4) // Watchdog update mode. This bit is Set Only.
MACRUM	6:40e873bbc5f7	1651
MACRUM	6:40e873bbc5f7	1652	/* WDTC - 0x4000 4004 */
MACRUM	6:40e873bbc5f7	1653	#define WDTC_COUNT_MASK 0xFFFFFF // Watchdog time-out interval.
MACRUM	6:40e873bbc5f7	1654	#define WDTC_COUNT_SHIFT 0
MACRUM	6:40e873bbc5f7	1655
MACRUM	6:40e873bbc5f7	1656	/* WDFEED - 0x4000 4008 */
MACRUM	6:40e873bbc5f7	1657	#define WDFEED_FEED_MASK 0x00FF // Feed value should be 0xAA followed by 0x55.
MACRUM	6:40e873bbc5f7	1658	#define WDFEED_FEED_SHIFT 0
MACRUM	6:40e873bbc5f7	1659
MACRUM	6:40e873bbc5f7	1660	/* WDTV - 0x4000 400C */
MACRUM	6:40e873bbc5f7	1661	#define WDTV_COUNT_MASK 0xFFFFFF // Counter timer value.
MACRUM	6:40e873bbc5f7	1662	#define WDTV_COUNT_SHIFT 0
MACRUM	6:40e873bbc5f7	1663
MACRUM	6:40e873bbc5f7	1664	/* WDWARNINT - 0x4000 4014 */
MACRUM	6:40e873bbc5f7	1665	#define WDWARNINT_WARNINT_MASK 0x03FF // Watchdog warning interrupt compare value.
MACRUM	6:40e873bbc5f7	1666	#define WDWARNINT_WARNINT_SHIFT 0
MACRUM	6:40e873bbc5f7	1667
MACRUM	6:40e873bbc5f7	1668	/* WDWINDOW - 0x4000 4018 */
MACRUM	6:40e873bbc5f7	1669	#define WDWINDOW_WINDOW_MASK 0xFFFFFF // Watchdog window value.
MACRUM	6:40e873bbc5f7	1670	#define WDWINDOW_WINDOW_SHIFT 0
MACRUM	6:40e873bbc5f7	1671
MACRUM	6:40e873bbc5f7	1672	/* WDMOD - address 0x4000 4000 */
MACRUM	6:40e873bbc5f7	1673	#define WDMOD_WDEN (1 << 0) // WDEN Watchdog enable bit (Set Only). When 1, the watchdog timer is running. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one. The clock source lock feature is not available on all parts, see Section 23.1).
MACRUM	6:40e873bbc5f7	1674	#define WDMOD_WDRESET_WDRESET (1 << 1) // Watchdog reset enable bit (Set Only). When 1, og time-out will cause a chip reset.
MACRUM	6:40e873bbc5f7	1675	#define WDMOD_WDTOF (1 << 2) // WDTOF Watchdog time-out flag. Set when the watchdog
MACRUM	6:40e873bbc5f7	1676	#define WDMOD_WDINT (1 << 3) // WDINT Watchdog interrupt flag (Read Only, not clearable by software).
MACRUM	6:40e873bbc5f7	1677
MACRUM	6:40e873bbc5f7	1678	/* WDTC - address 0x4000 4004 */
MACRUM	6:40e873bbc5f7	1679	#define WDTC_COUNT_MASK 0xFFFFFF // Watchdog time-out interval.
MACRUM	6:40e873bbc5f7	1680	#define WDTC_COUNT_SHIFT 0
MACRUM	6:40e873bbc5f7	1681
MACRUM	6:40e873bbc5f7	1682	/* WDFEED - address 0x4000 4008 */
MACRUM	6:40e873bbc5f7	1683	#define WDFEED_FEED_MASK 0x00FF // Feed value should be 0xAA followed by 0x55.
MACRUM	6:40e873bbc5f7	1684	#define WDFEED_FEED_SHIFT 0
MACRUM	6:40e873bbc5f7	1685
MACRUM	6:40e873bbc5f7	1686	/* WDTV - address 0x4000 000C */
MACRUM	6:40e873bbc5f7	1687	#define WDTV_COUNT_MASK 0xFFFFFF // Counter timer value.
MACRUM	6:40e873bbc5f7	1688	#define WDTV_COUNT_SHIFT 0
MACRUM	6:40e873bbc5f7	1689
MACRUM	6:40e873bbc5f7	1690	/* SYST_CSR - 0xE000 E010 */
MACRUM	6:40e873bbc5f7	1691	#define SYST_CSR_ENABLE (1 << 0) // System Tick counter enable. When 1, the counter is enabled. When 0, the counter is disabled.
MACRUM	6:40e873bbc5f7	1692	#define SYST_CSR_TICKINT (1 << 1) // System Tick interrupt enable. When 1, the System Tick interrupt 0 is enabled. When 0, the System Tick interrupt is disabled. When enabled, the interrupt is generated when the System Tick counter counts down to 0.
MACRUM	6:40e873bbc5f7	1693	#define SYST_CSR_CLKSOURCE (1 << 2) // System Tick clock source selection. When 1, the system clock (CPU) clock is selected. When 0, the system clock/2 is selected as the reference clock.
MACRUM	6:40e873bbc5f7	1694	#define SYST_CSR_COUNTFLAG (1 << 16) // Returns 1 if the SysTick timer counted to 0 since the last read of this register. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
MACRUM	6:40e873bbc5f7	1695
MACRUM	6:40e873bbc5f7	1696	/* SYST_RVR - 0xE000 E014 */
MACRUM	6:40e873bbc5f7	1697	#define SYST_RVR_RELOAD_MASK 0xFFFFFF // This is the value that is loaded into the System Tick counter when it 0 counts down to 0.
MACRUM	6:40e873bbc5f7	1698	#define SYST_RVR_RELOAD_SHIFT 0
MACRUM	6:40e873bbc5f7	1699
MACRUM	6:40e873bbc5f7	1700	/* SYST_CVR - 0xE000 E018 */
MACRUM	6:40e873bbc5f7	1701	#define SYST_CVR_CURRENT_MASK 0xFFFFFF // Reading this register returns the current value of the System Tick counter. Writing any value clears the System Tick counter and the COUNTFLAG bit in STCTRL.
MACRUM	6:40e873bbc5f7	1702	#define SYST_CVR_CURRENT_SHIFT 0
MACRUM	6:40e873bbc5f7	1703
MACRUM	6:40e873bbc5f7	1704	/* SYST_CALIB - 0xE000 E01C */
MACRUM	6:40e873bbc5f7	1705	#define SYST_CALIB_TENMS_MASK 0xFFFFFF // See Table 461.
MACRUM	6:40e873bbc5f7	1706	#define SYST_CALIB_TENMS_SHIFT 0
MACRUM	6:40e873bbc5f7	1707	#define SYST_CALIB_SKEW (1 << 30) // See Table 461.
MACRUM	6:40e873bbc5f7	1708	#define SYST_CALIB_NOREF (1 << 31) // See Table 461.
MACRUM	6:40e873bbc5f7	1709
MACRUM	6:40e873bbc5f7	1710	/* AD0CR - address 0x4001 C000 */
MACRUM	6:40e873bbc5f7	1711	#define AD0CR_SEL_MASK 0x00FF // Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin 0x00 AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01).
MACRUM	6:40e873bbc5f7	1712	#define AD0CR_SEL_SHIFT 0
MACRUM	6:40e873bbc5f7	1713	#define AD0CR_CLKDIV_MASK 0xFF00 // The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which 0 should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
MACRUM	6:40e873bbc5f7	1714	#define AD0CR_CLKDIV_SHIFT 8
MACRUM	6:40e873bbc5f7	1715	#define AD0CR_BURST (1 << 16) // Burst mode Remark: If BURST is set to 1, the ADGINTEN bit in the AD0INTEN register (Table 365) must be set to 0.
MACRUM	6:40e873bbc5f7	1716	#define AD0CR_CLKS_MASK 0xE0000 // This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
MACRUM	6:40e873bbc5f7	1717	#define AD0CR_CLKS_SHIFT 17
MACRUM	6:40e873bbc5f7	1718	#define AD0CR_START_MASK 0x7000000 // When the BURST bit is 0, these bits control whether and when an A/D conversion is started:
MACRUM	6:40e873bbc5f7	1719	#define AD0CR_START_SHIFT 24
MACRUM	6:40e873bbc5f7	1720	#define AD0CR_EDGE (1 << 27) // This bit is significant only when the START field contains 010-111. In these cases:
MACRUM	6:40e873bbc5f7	1721
MACRUM	6:40e873bbc5f7	1722	/* AD0GDR - address 0x4001 C004 */
MACRUM	6:40e873bbc5f7	1723	#define AD0GDR_V_VREF_MASK 0xFFC0 // When DONE is 1, this field contains a binary fraction representing X the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
MACRUM	6:40e873bbc5f7	1724	#define AD0GDR_V_VREF_SHIFT 6
MACRUM	6:40e873bbc5f7	1725	#define AD0GDR_CHN_MASK 0x7000000 // These bits contain the channel from which the result bits V_VREF X were converted.
MACRUM	6:40e873bbc5f7	1726	#define AD0GDR_CHN_SHIFT 24
MACRUM	6:40e873bbc5f7	1727	#define AD0GDR_OVERRUN (1 << 30) // This bit is 1 in burst mode if the results of one or more conversions 0 was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.
MACRUM	6:40e873bbc5f7	1728	#define AD0GDR_DONE (1 << 31) // This bit is set to 1 when an A/D conversion completes. It is cleared 0 when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
MACRUM	6:40e873bbc5f7	1729
MACRUM	6:40e873bbc5f7	1730	/* AD0INTEN - address 0x4001 C00C */
MACRUM	6:40e873bbc5f7	1731	#define AD0INTEN_ADINTEN_MASK 0x00FF // These bits allow control over which A/D channels generate 0x00 interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
MACRUM	6:40e873bbc5f7	1732	#define AD0INTEN_ADINTEN_SHIFT 0
MACRUM	6:40e873bbc5f7	1733	#define AD0INTEN_ADGINTEN (1 << 8) // When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. Remark: This bit must be set to 0 in burst mode (BURST = 1 in the AD0CR register). Reserved. Unused, always 0.
MACRUM	6:40e873bbc5f7	1734
MACRUM	6:40e873bbc5f7	1735	/* AD0DR0 to AD0DR7 - addresses 0x4001 C010 to 0x4001 C02C */
MACRUM	6:40e873bbc5f7	1736	#define AD0DRn_V_VREF_MASK 0xFFC0 // When DONE is 1, this field contains a binary fraction representing the NA voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. Reserved.
MACRUM	6:40e873bbc5f7	1737	#define AD0DRn_V_VREF_SHIFT 6
MACRUM	6:40e873bbc5f7	1738	#define AD0DRn_OVERRUN (1 << 30) // This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
MACRUM	6:40e873bbc5f7	1739	#define AD0DRn_DONE (1 << 31) // This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
MACRUM	6:40e873bbc5f7	1740
MACRUM	6:40e873bbc5f7	1741	/* AD0STAT - address 0x4001 C030 */
MACRUM	6:40e873bbc5f7	1742	#define AD0STAT_DONE_MASK 0x00FF // These bits mirror the DONE status flags that appear in the result register for each A/D channel n.
MACRUM	6:40e873bbc5f7	1743	#define AD0STAT_DONE_SHIFT 0
MACRUM	6:40e873bbc5f7	1744	#define AD0STAT_OVERRUN_MASK 0xFF00 // These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
MACRUM	6:40e873bbc5f7	1745	#define AD0STAT_OVERRUN_SHIFT 8
MACRUM	6:40e873bbc5f7	1746	#define AD0STAT_ADINT (1 << 16) // This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. Reserved. Unused, always 0.
MACRUM	6:40e873bbc5f7	1747
MACRUM	6:40e873bbc5f7	1748	/* FLASHCFG, address 0x4003 C010 */
MACRUM	6:40e873bbc5f7	1749	#define FLASHCFG_FLASHTIM_MASK 0x0003 // Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
MACRUM	6:40e873bbc5f7	1750	#define FLASHCFG_FLASHTIM_SHIFT 0
MACRUM	6:40e873bbc5f7	1751
MACRUM	6:40e873bbc5f7	1752	/* FMSSTART - 0x4003 C020 */
MACRUM	6:40e873bbc5f7	1753	#define FMSSTART_START_MASK 0x1FFFF // Signature generation start address (corresponds to AHB byte address bits[20:4]).
MACRUM	6:40e873bbc5f7	1754	#define FMSSTART_START_SHIFT 0
MACRUM	6:40e873bbc5f7	1755
MACRUM	6:40e873bbc5f7	1756	/* FMSSTOP - 0x4003 C024 */
MACRUM	6:40e873bbc5f7	1757	#define FMSSTOP_STOP_MASK 0x1FFFF // BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).
MACRUM	6:40e873bbc5f7	1758	#define FMSSTOP_STOP_SHIFT 0
MACRUM	6:40e873bbc5f7	1759	#define FMSSTOP_SIG_START (1 << 17) // Start control bit for signature generation.
MACRUM	6:40e873bbc5f7	1760
MACRUM	6:40e873bbc5f7	1761	/* FMSTAT - 0x4003 CFE0 */
MACRUM	6:40e873bbc5f7	1762	#define FMSTAT_SIG_DONE (1 << 2) // When 1, a previously started signature generation has 0 completed. See FMSTATCLR register description for clearing this flag.
MACRUM	6:40e873bbc5f7	1763
MACRUM	6:40e873bbc5f7	1764	/* FMSTATCLR - 0x0x4003 CFE8 */
MACRUM	6:40e873bbc5f7	1765	#define FMSTATCLR_SIG_DONE_CLR (1 << 2) // Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.
MACRUM	6:40e873bbc5f7	1766
MACRUM	6:40e873bbc5f7	1767
MACRUM	6:40e873bbc5f7	1768	#endif

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Type:	Program
Mbed OS support:	Mbed OS
Created:	10 Nov 2014
Imports:	18
Forks:	0
Commits:	12
Dependents:	0
Dependencies:	0
Followers:	2

The code in this repository is Apache licensed.

mbed/TARGET_LPC1114/TARGET_NXP/TARGET_LPC11XX_11CXX/device/bitfields.h@6:40e873bbc5f7, 2017-03-16 (annotated)

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