stm32l4xx_ll_tim.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_tim.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    16-September-2015
00007   * @brief   Header file of TIM LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_TIM_H
00040 #define __STM32L4xx_LL_TIM_H
00041 
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048 
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052 
00053 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
00054 
00055 /** @defgroup TIM_LL TIM
00056   * @{
00057   */
00058 
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
00062   * @{
00063   */
00064 static const uint8_t OFFSET_TAB_CCMRx[] = 
00065   {
00066     0x00,   /* 0: TIMx_CH1  */
00067     0x00,   /* 1: TIMx_CH1N */
00068     0x00,   /* 2: TIMx_CH2  */
00069     0x00,   /* 3: TIMx_CH2N */
00070     0x04,   /* 4: TIMx_CH3  */
00071     0x04,   /* 5: TIMx_CH3N */    
00072     0x04,   /* 6: TIMx_CH4  */
00073     0x3C,   /* 7: TIMx_CH5  */
00074     0x3C    /* 8: TIMx_CH6  */
00075   };
00076 
00077 static const uint8_t SHIFT_TAB_OCxx[] =
00078 {
00079   0,            /* 0: OC1M, OC1FE, OC1PE */
00080   0,            /* 1: - NA */
00081   8,            /* 2: OC2M, OC2FE, OC2PE */
00082   0,            /* 3: - NA */
00083   0,            /* 4: OC3M, OC3FE, OC3PE */
00084   0,            /* 5: - NA */
00085   8,            /* 6: OC4M, OC4FE, OC4PE */
00086   0,            /* 7: OC5M, OC5FE, OC5PE */
00087   8             /* 8: OC6M, OC6FE, OC6PE */
00088 };
00089 
00090 static const uint8_t SHIFT_TAB_ICxx[] =
00091 {
00092   0,            /* 0: CC1S, IC1PSC, IC1F */
00093   0,            /* 1: - NA */
00094   8,            /* 2: CC2S, IC2PSC, IC2F */
00095   0,            /* 3: - NA */
00096   0,            /* 4: CC3S, IC3PSC, IC3F */
00097   0,            /* 5: - NA */
00098   8,            /* 6: CC4S, IC4PSC, IC4F */
00099   0,            /* 7: - NA */
00100   0             /* 8: - NA */
00101 };
00102 
00103 static const uint8_t SHIFT_TAB_CCxP[] =
00104 {
00105   0,            /* 0: CC1P */
00106   2,            /* 1: CC1NP */
00107   4,            /* 2: CC2P */
00108   6,            /* 3: CC2NP */
00109   8,            /* 4: CC3P */
00110   10,           /* 5: CC3NP */
00111   12,           /* 6: CC4P */
00112   16,           /* 7: CC5P */
00113   20            /* 8: CC6P */
00114 };
00115 
00116 static const uint8_t SHIFT_TAB_OISx[] =
00117 {
00118   0,            /* 0: OIS1 */
00119   1,            /* 1: OIS1N */
00120   2,            /* 2: OIS2 */
00121   3,            /* 3: OIS2N */
00122   4,            /* 4: OIS3 */
00123   5,            /* 5: OIS3N */
00124   6,            /* 6: OIS4 */
00125   8,            /* 7: OIS5 */
00126   10            /* 8: OIS6 */
00127 };
00128 /**
00129   * @}
00130   */
00131 
00132 
00133 /* Private constants ---------------------------------------------------------*/
00134 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
00135   * @{
00136   */
00137 /* Generic bit definitions for TIMx_OR2 register */
00138 #define TIMx_OR2_BKINE     TIM1_OR2_BKINE     /*!< BRK BKIN input enable */
00139 #define TIMx_OR2_BKCOMP1E  TIM1_OR2_BKCMP1E   /*!< BRK COMP1 enable */
00140 #define TIMx_OR2_BKCOMP2E  TIM1_OR2_BKCMP2E   /*!< BRK COMP2 enable */
00141 #define TIMx_OR2_BKDFBK0E  TIM1_OR2_BKDFBK0E  /*!< BRK DFSDM_BREAK[0] enable */
00142 #define TIMx_OR2_BKINP     TIM1_OR2_BKINP     /*!< BRK BKIN input polarity */
00143 #define TIMx_OR2_BKCOMP1P  TIM1_OR2_BKCMP1P   /*!< BRK COMP1 input polarity */
00144 #define TIMx_OR2_BKCOMP2P  TIM1_OR2_BKCMP2P   /*!< BRK COMP2 input polarity */
00145 #define TIMx_OR2_ETRSEL    TIM1_OR2_ETRSEL    /*!< TIMx ETR source selection */
00146 
00147 /* Generic bit definitions for TIMx_OR3 register */
00148 #define TIMx_OR3_BK2INE    TIM1_OR3_BK2INE     /*!< BRK2 BKIN2 input enable */
00149 #define TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E   /*!< BRK2 COMP1 enable */
00150 #define TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E   /*!< BRK2 COMP2 enable */
00151 #define TIMx_OR3_BK2DFBK1E TIM1_OR3_BK2DFBK1E  /*!< BRK2 DFSDM_BREAK[1] enable */
00152 #define TIMx_OR3_BK2INP    TIM1_OR3_BK2INP     /*!< BRK2 BKIN2 input polarity */
00153 #define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P   /*!< BRK2 COMP1 input polarity */
00154 #define TIMx_OR3_BK2COMP2P  TIM1_OR3_BK2CMP2P  /*!< BRK2 COMP2 input polarity */
00155 
00156 /* Remap mask definitions */
00157 #define TIMx_OR1_RMP_SHIFT ((uint32_t)16)
00158 #define TIMx_OR1_RMP_MASK  ((uint32_t)0x0000FFFF)
00159 #define TIM1_OR1_RMP_MASK  ((uint32_t)((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
00160 #define TIM2_OR1_RMP_MASK  ((uint32_t)((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT))
00161 #define TIM3_OR1_RMP_MASK  ((uint32_t)(TIM3_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
00162 #define TIM8_OR1_RMP_MASK  ((uint32_t)((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
00163 #define TIM15_OR1_RMP_MASK ((uint32_t)((TIM15_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
00164 #define TIM16_OR1_RMP_MASK ((uint32_t)((TIM16_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
00165 #define TIM17_OR1_RMP_MASK ((uint32_t)((TIM17_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
00166 
00167 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
00168 #define DT_DELAY_1 ((uint8_t)0x7F)
00169 #define DT_DELAY_2 ((uint8_t)0x3F)
00170 #define DT_DELAY_3 ((uint8_t)0x1F)
00171 #define DT_DELAY_4 ((uint8_t)0x1F)
00172     
00173 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
00174 #define DT_RANGE_1 ((uint8_t)0x00)
00175 #define DT_RANGE_2 ((uint8_t)0x80)
00176 #define DT_RANGE_3 ((uint8_t)0xC0)
00177 #define DT_RANGE_4 ((uint8_t)0xE0)
00178 /**
00179   * @}
00180   */
00181 
00182 
00183 /* Private macros ------------------------------------------------------------*/
00184 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
00185   * @{
00186   */
00187 /** @brief  Convert channel id into channel index
00188   * @param  __CHANNEL__: This parameter can be one of the following values: 
00189   *         @arg @ref LL_TIM_CHANNEL_CH1
00190   *         @arg @ref LL_TIM_CHANNEL_CH1N
00191   *         @arg @ref LL_TIM_CHANNEL_CH2
00192   *         @arg @ref LL_TIM_CHANNEL_CH2N
00193   *         @arg @ref LL_TIM_CHANNEL_CH3
00194   *         @arg @ref LL_TIM_CHANNEL_CH3N
00195   *         @arg @ref LL_TIM_CHANNEL_CH4
00196   *         @arg @ref LL_TIM_CHANNEL_CH5
00197   *         @arg @ref LL_TIM_CHANNEL_CH6
00198   * @retval none
00199   */
00200 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__)  \
00201   (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ?  0 :\
00202    ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1 :\
00203    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ?  2 :\
00204    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3 :\
00205    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ?  4 :\
00206    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5 :\
00207    ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ?  6 :\
00208    ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ?  7 : 8)
00209 
00210 /** @brief  Calculate the deadtime sampling period(in ps)
00211   * @param  __TIMCLK__: timer input clock frequency (in Hz).
00212   * @param  __CKD__: This parameter can be one of the following values: 
00213   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
00214   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
00215   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
00216   * @retval none
00217   */
00218 #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                       \
00219     (((int)(__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000/(__TIMCLK__))        : \
00220      ((int)(__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000/((__TIMCLK__) >> 1)) : \
00221      ((uint64_t)1000000000000/((__TIMCLK__) >> 2)))
00222 /**
00223   * @}
00224   */
00225 
00226 
00227 /* Exported types ------------------------------------------------------------*/
00228 /* Exported constants --------------------------------------------------------*/
00229 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
00230   * @{
00231   */
00232 
00233 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
00234   * @brief    Flags defines which can be used with LL_TIM_ReadReg function
00235   * @{
00236   */
00237 #define LL_TIM_SR_UIF                          TIM_SR_UIF
00238 #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF
00239 #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF
00240 #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF
00241 #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF
00242 #define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF
00243 #define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF
00244 #define LL_TIM_SR_COMIF                        TIM_SR_COMIF
00245 #define LL_TIM_SR_TIF                          TIM_SR_TIF
00246 #define LL_TIM_SR_BIF                          TIM_SR_BIF
00247 #define LL_TIM_SR_B2IF                         TIM_SR_B2IF
00248 #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF
00249 #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF
00250 #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF
00251 #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF
00252 #define LL_TIM_SR_SBIF                         TIM_SR_SBIF
00253 /**
00254   * @}
00255   */
00256 
00257 /** @defgroup TIM_LL_EC_IT IT Defines
00258   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions
00259   * @{
00260   */
00261 #define LL_TIM_DIER_UIE                        TIM_DIER_UIE
00262 #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE
00263 #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE
00264 #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE
00265 #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE
00266 #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE
00267 #define LL_TIM_DIER_TIE                        TIM_DIER_TIE
00268 #define LL_TIM_DIER_BIE                        TIM_DIER_BIE
00269 /**
00270   * @}
00271   */
00272 
00273 /** @defgroup TIM_LL_EC_UPDATESOURCE UPDATESOURCE
00274   * @{
00275   */
00276 #define LL_TIM_UPDATESOURCE_REGULAR            ((uint32_t)0x00000000) /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ 
00277 #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS            /*!< Only counter overflow/underflow generates an update request */  
00278 /**
00279   * @}
00280   */
00281 
00282 /** @defgroup TIM_LL_EC_ONEPULSEMODE ONEPULSEMODE
00283   * @{
00284   */
00285 #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM            /*!< Counter is not stopped at update event */ 
00286 #define LL_TIM_ONEPULSEMODE_REPETITIVE         ((uint32_t)0x00000000) /*!< Counter stops counting at the next update event */ 
00287 /**
00288   * @}
00289   */
00290 
00291 /** @defgroup TIM_LL_EC_COUNTERMODE COUNTERMODE
00292   * @{
00293   */
00294 #define LL_TIM_COUNTERMODE_UP                  ((uint32_t)0x00000000)/*!<Counter used as upcounter */ 
00295 #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR           /*!< Counter used as downcounter */ 
00296 #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0         /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */ 
00297 #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1         /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */ 
00298 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS           /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */ 
00299 /**
00300   * @}
00301   */
00302 
00303 /** @defgroup TIM_LL_EC_CLOCKDIVISION CLOCKDIVISION
00304   * @{
00305   */
00306 #define LL_TIM_CLOCKDIVISION_DIV1              ((uint32_t)0x00000000) /*!< tDTS=tCK_INT */ 
00307 #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0          /*!< tDTS=2*tCK_INT */ 
00308 #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1          /*!< tDTS=4*tCK_INT */ 
00309 /**
00310   * @}
00311   */
00312 
00313 /** @defgroup TIM_LL_EC_COUNTERDIRECTION COUNTERDIRECTION
00314   * @{
00315   */
00316 #define LL_TIM_COUNTERDIRECTION_UP             ((uint32_t)0x00000000) /*!< Timer counter counts up */
00317 #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR  /*!< Timer counter counts down */
00318 /**
00319   * @}
00320   */
00321 
00322 /** @defgroup TIM_LL_EC_CCUPDATESOURCE CCUPDATESOURCE
00323   * @{
00324   */
00325 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        ((uint32_t)0x00000000) /*!< Capture/compare control bits are updated by setting the COMG bit only */ 
00326 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS           /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ 
00327 /**
00328   * @}
00329   */
00330 
00331 /** @defgroup TIM_LL_EC_CCDMAREQUEST CCDMAREQUEST
00332   * @{
00333   */
00334 #define LL_TIM_CCDMAREQUEST_CC                 ((uint32_t)0x00000000) /*!< CCx DMA request sent when CCx event occurs */ 
00335 #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS           /*!< CCx DMA requests sent when update event occurs */ 
00336 /**
00337   * @}
00338   */
00339 
00340 /** @defgroup TIM_LL_EC_LOCKLEVEL LOCKLEVEL
00341   * @{
00342   */
00343 #define LL_TIM_LOCKLEVEL_OFF                   ((uint32_t)0x00000000) /*!< LOCK OFF - No bit is write protected */ 
00344 #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0        /*!< LOCK Level 1 */         
00345 #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1        /*!< LOCK Level 2 */          
00346 #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK          /*!< LOCK Level 3 */ 
00347 /**
00348   * @}
00349   */
00350 
00351 /** @defgroup TIM_LL_EC_CHANNEL CHANNEL
00352   * @{
00353   */
00354 #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E /*!< Timer input/output channel 1 */
00355 #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
00356 #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E /*!< Timer input/output channel 2 */
00357 #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
00358 #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E /*!< Timer input/output channel 3 */
00359 #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
00360 #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E /*!< Timer input/output channel 4 */
00361 #define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E /*!< Timer output channel 5 */
00362 #define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E /*!< Timer output channel 6 */
00363 /**
00364   * @}
00365   */
00366 
00367 /** @defgroup TIM_LL_EC_OCMODE OCMODE
00368   * @{
00369   */
00370 #define LL_TIM_OCMODE_FROZEN                   ((uint32_t)0x00000000)                                   /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ 
00371 #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/ 
00372 #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/ 
00373 #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/ 
00374 #define LL_TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)                                       /*!<OCyREF is forced low*/ 
00375 #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/ 
00376 #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ 
00377 #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ 
00378 #define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/ 
00379 #define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/ 
00380 #define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/ 
00381 #define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/ 
00382 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/ 
00383 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/ 
00384 /**
00385   * @}
00386   */
00387 
00388 /** @defgroup TIM_LL_EC_OCPOLARITY OCPOLARITY
00389   * @{
00390   */
00391 #define LL_TIM_OCPOLARITY_HIGH                 ((uint32_t)0x00000000) /*!< OCx active high*/ 
00392 #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P          /*!<OCxactive low*/ 
00393 /**
00394   * @}
00395   */
00396 
00397 /** @defgroup TIM_LL_EC_OCIDLESTATE OCIDLESTATE
00398   * @{
00399   */
00400 #define LL_TIM_OCIDLESTATE_LOW                 ((uint32_t)0x00000000) /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ 
00401 #define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1        /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ 
00402 /**
00403   * @}
00404   */
00405 
00406 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
00407   * @{
00408   */
00409 #define LL_TIM_GROUPCH5_NONE                   (uint32_t)0x00000000  /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00410 #define LL_TIM_GROUPCH5_OC1REFC                (TIM_CCR5_GC5C1)      /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
00411 #define LL_TIM_GROUPCH5_OC2REFC                (TIM_CCR5_GC5C2)      /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
00412 #define LL_TIM_GROUPCH5_OC3REFC                (TIM_CCR5_GC5C3)      /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
00413 /**
00414   * @}
00415   */
00416 
00417 /** @defgroup TIM_LL_EC_ACTIVEINPUT ACTIVEINPUT
00418   * @{
00419   */
00420 #define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16) /*!< ICx is mapped on TIx */ 
00421 #define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16) /*!< ICx is mapped on TIy */ 
00422 #define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16)   /*!< ICx is mapped on TRC */ 
00423 /**
00424   * @}
00425   */
00426 
00427 /** @defgroup TIM_LL_EC_ICPSC ICPSC
00428   * @{
00429   */
00430 #define LL_TIM_ICPSC_DIV1                      ((uint32_t)0x00000000) /*!< No prescaler, capture is done each time an edge is detected on the capture input */ 
00431 #define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16)    /*!< Capture is done once every 2 events */ 
00432 #define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16)    /*!< Capture is done once every 4 events */ 
00433 #define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16)      /*!< Capture is done once every 8 events */ 
00434 /**
00435   * @}
00436   */
00437 
00438 /** @defgroup TIM_LL_EC_IC_FILTER IC FILTER
00439   * @{
00440   */
00441 #define LL_TIM_IC_FILTER_FDIV1                 ((uint32_t)0x00000000)                                    /*!< No filter, sampling is done at fDTS */ 
00442 #define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16)                                          /*!< fSAMPLING=fCK_INT, N=2 */ 
00443 #define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16)                                          /*!< fSAMPLING=fCK_INT, N=4 */ 
00444 #define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16)                     /*!< fSAMPLING=fCK_INT, N=8 */ 
00445 #define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16)                                          /*!< fSAMPLING=fDTS/2, N=6 */ 
00446 #define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16)                     /*!< fSAMPLING=fDTS/2, N=8 */ 
00447 #define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16)                     /*!< fSAMPLING=fDTS/4, N=6 */ 
00448 #define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16)  /*!< fSAMPLING=fDTS/4, N=8 */ 
00449 #define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16)                                          /*!< fSAMPLING=fDTS/8, N=6 */ 
00450 #define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16)                     /*!< fSAMPLING=fDTS/8, N=8 */ 
00451 #define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16)                     /*!< fSAMPLING=fDTS/16, N=5 */ 
00452 #define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16)  /*!< fSAMPLING=fDTS/16, N=6 */ 
00453 #define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16)                     /*!< fSAMPLING=fDTS/16, N=8 */ 
00454 #define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16)  /*!< fSAMPLING=fDTS/32, N=5 */ 
00455 #define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16)  /*!< fSAMPLING=fDTS/32, N=6 */ 
00456 #define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16)                                            /*!< fSAMPLING=fDTS/32, N=8 */ 
00457 /**
00458   * @}
00459   */
00460 
00461 /** @defgroup TIM_LL_EC_IC_POLARITY IC POLARITY
00462   * @{
00463   */
00464 #define LL_TIM_IC_POLARITY_RISING              ((uint32_t)0x00000000)           /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ 
00465 #define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ 
00466 #define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ 
00467 /**
00468   * @}
00469   */
00470 
00471 /** @defgroup TIM_LL_EC_CLOCKSOURCE CLOCKSOURCE
00472   * @{
00473   */
00474 #define LL_TIM_CLOCKSOURCE_INTERNAL            ((uint32_t)0x00000000)                               /*!< The timer is clocked by the internal clock provided from the RCC */
00475 #define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 ) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
00476 #define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                        /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
00477 /**
00478   * @}
00479   */
00480 
00481 /** @defgroup TIM_LL_EC_ENCODERMODE_X2 ENCODERMODE X2
00482   * @{
00483   */
00484 #define LL_TIM_ENCODERMODE_X2_TI1              TIM_SMCR_SMS_0                    /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ 
00485 #define LL_TIM_ENCODERMODE_X2_TI2              TIM_SMCR_SMS_1                    /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ 
00486 #define LL_TIM_ENCODERMODE_X4_TI12             (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges                                                                                                                                                                   depending on the level of the other input l */
00487 /**
00488   * @}
00489   */
00490 
00491 /** @defgroup TIM_LL_EC_TRGO TRGO
00492   * @{
00493   */
00494 #define LL_TIM_TRGO_RESET                      ((uint32_t)0x00000000)                          /*!< UG bit from the TIMx_EGR register is used as trigger output */ 
00495 #define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */ 
00496 #define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */ 
00497 #define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is usd as trigger output */ 
00498 #define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */ 
00499 #define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */ 
00500 #define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */ 
00501 #define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ 
00502 /**
00503   * @}
00504   */
00505 
00506 /** @defgroup TIM_LL_EC_TRGO2 TRGO2
00507   * @{
00508   */
00509 #define LL_TIM_TRGO2_RESET                     ((uint32_t)0x00000000)                                              /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */ 
00510 #define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */ 
00511 #define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */ 
00512 #define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */ 
00513 #define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */ 
00514 #define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */ 
00515 #define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */ 
00516 #define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */ 
00517 #define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */ 
00518 #define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */ 
00519 #define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */ 
00520 #define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */ 
00521 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */ 
00522 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */ 
00523 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */ 
00524 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */ 
00525 /**
00526   * @}
00527   */
00528 
00529 /** @defgroup TIM_LL_EC_SLAVEMODE SLAVEMODE
00530   * @{
00531   */
00532 #define LL_TIM_SLAVEMODE_DISABLED              ((uint32_t)0x00000000)              /*!< Slave mode disabled */ 
00533 #define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ 
00534 #define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ 
00535 #define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ 
00536 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */ 
00537 /**
00538   * @}
00539   */
00540 
00541 /** @defgroup TIM_LL_EC_TS TS
00542   * @{
00543   */
00544 #define LL_TIM_TS_ITR0                         ((uint32_t)0x00000000)          /*!< Internal Trigger 0 (ITR0) is used as trigger input */ 
00545 #define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */ 
00546 #define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */ 
00547 #define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ 
00548 #define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ 
00549 #define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ 
00550 #define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ 
00551 #define LL_TIM_TS_ETRF                         TIM_SMCR_TS                     /*!< Filtered external Trigger (ETRF) is used as trigger input */ 
00552 /**
00553   * @}
00554   */
00555 
00556 /** @defgroup TIM_LL_EC_ETR_POLARITY ETR POLARITY
00557   * @{
00558   */
00559 #define LL_TIM_ETR_POLARITY_NONINVERTED        ((uint32_t)0x00000000) /*!< ETR is non-inverted, active at high level or rising edge */ 
00560 #define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP           /*!< ETR is inverted, active at low level or falling edge */ 
00561 /**
00562   * @}
00563   */
00564 
00565 /** @defgroup TIM_LL_EC_ETR_PRESCALER ETR PRESCALER
00566   * @{
00567   */
00568 #define LL_TIM_ETR_PRESCALER_DIV1              ((uint32_t)0x00000000) /*!< ETR prescaler OFF */ 
00569 #define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0        /*!< ETR frequency is divided by 2 */ 
00570 #define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1        /*!< ETR frequency is divided by 4 */ 
00571 #define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS          /*!< ETR frequency is divided by 8 */ 
00572 /**
00573   * @}
00574   */
00575 
00576 /** @defgroup TIM_LL_EC_ETR_FILTER ETR FILTER
00577   * @{
00578   */
00579 #define LL_TIM_ETR_FILTER_FDIV1                ((uint32_t)0x00000000)                               /*!< No filter, sampling is done at fDTS */ 
00580 #define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */ 
00581 #define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */ 
00582 #define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */ 
00583 #define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */ 
00584 #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */ 
00585 #define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 )                   /*!< fSAMPLING=fDTS/4, N=6 */ 
00586 #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */ 
00587 #define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */ 
00588 #define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */ 
00589 #define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 )                   /*!< fSAMPLING=fDTS/16, N=6 */ 
00590 #define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */ 
00591 #define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 )                   /*!< fSAMPLING=fDTS/16, N=5 */ 
00592 #define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2  | TIM_SMCR_ETF_0)  /*!< fSAMPLING=fDTS/32, N=5 */ 
00593 #define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2  | TIM_SMCR_ETF_1)  /*!< fSAMPLING=fDTS/32, N=6 */ 
00594 #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */ 
00595 /**
00596   * @}
00597   */
00598 
00599 /** @defgroup TIM_LL_EC_ETRSOURCE ETRSOURCE
00600   * @{
00601   */
00602 #define LL_TIM_ETRSOURCE_LEGACY                ((uint32_t)(0x00000000)) /*!< ETR legacy mode */ 
00603 #define LL_TIM_ETRSOURCE_COMP1                 TIM1_OR2_ETRSEL_0        /*!< COMP1 output connected to ETR input */ 
00604 #define LL_TIM_ETRSOURCE_COMP2                 TIM1_OR2_ETRSEL_1        /*!< COMP2 output connected to ETR input */ 
00605 /**
00606   * @}
00607   */
00608 
00609 /** @defgroup TIM_LL_EC_BREAK_POLARITY BREAK POLARITY
00610   * @{
00611   */
00612 #define LL_TIM_BREAK_POLARITY_LOW              ((uint32_t)0x00000000)   /*!< Break input BRK is active low */ 
00613 #define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */ 
00614 /**
00615   * @}
00616   */
00617 
00618 /** @defgroup TIM_LL_EC_BREAK_FILTER BREAK FILTER
00619   * @{
00620   */
00621 #define LL_TIM_BREAK_FILTER_FDIV1              ((uint32_t)0x00000000)   /*!< No filter, BRK acts asynchronously */ 
00622 #define LL_TIM_BREAK_FILTER_FDIV1_N2           ((uint32_t)0x00010000)   /*!< fSAMPLING=fCK_INT, N=2 */ 
00623 #define LL_TIM_BREAK_FILTER_FDIV1_N4           ((uint32_t)0x00020000)   /*!< fSAMPLING=fCK_INT, N=4 */ 
00624 #define LL_TIM_BREAK_FILTER_FDIV1_N8           ((uint32_t)0x00030000)   /*!< fSAMPLING=fCK_INT, N=8 */ 
00625 #define LL_TIM_BREAK_FILTER_FDIV2_N6           ((uint32_t)0x00040000)   /*!< fSAMPLING=fDTS/2, N=6 */ 
00626 #define LL_TIM_BREAK_FILTER_FDIV2_N8           ((uint32_t)0x00050000)   /*!< fSAMPLING=fDTS/2, N=8 */ 
00627 #define LL_TIM_BREAK_FILTER_FDIV4_N6           ((uint32_t)0x00060000)   /*!< fSAMPLING=fDTS/4, N=6 */ 
00628 #define LL_TIM_BREAK_FILTER_FDIV4_N8           ((uint32_t)0x00070000)   /*!< fSAMPLING=fDTS/4, N=8 */ 
00629 #define LL_TIM_BREAK_FILTER_FDIV8_N6           ((uint32_t)0x00080000)   /*!< fSAMPLING=fDTS/8, N=6 */ 
00630 #define LL_TIM_BREAK_FILTER_FDIV8_N8           ((uint32_t)0x00090000)   /*!< fSAMPLING=fDTS/8, N=8 */ 
00631 #define LL_TIM_BREAK_FILTER_FDIV16_N5          ((uint32_t)0x000A0000)   /*!< fSAMPLING=fDTS/16, N=5 */ 
00632 #define LL_TIM_BREAK_FILTER_FDIV16_N6          ((uint32_t)0x000B0000)   /*!< fSAMPLING=fDTS/16, N=6 */ 
00633 #define LL_TIM_BREAK_FILTER_FDIV16_N8          ((uint32_t)0x000C0000)   /*!< fSAMPLING=fDTS/16, N=8 */ 
00634 #define LL_TIM_BREAK_FILTER_FDIV32_N5          ((uint32_t)0x000D0000)   /*!< fSAMPLING=fDTS/32, N=5 */ 
00635 #define LL_TIM_BREAK_FILTER_FDIV32_N6          ((uint32_t)0x000E0000)   /*!< fSAMPLING=fDTS/32, N=6 */ 
00636 #define LL_TIM_BREAK_FILTER_FDIV32_N8          ((uint32_t)0x000F0000)   /*!< fSAMPLING=fDTS/32, N=8 */ 
00637 /**
00638   * @}
00639   */
00640 
00641 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
00642   * @{
00643   */
00644 #define LL_TIM_BREAK2_POLARITY_LOW             ((uint32_t)0x00000000) /*!< Break input BRK2 is active low */ 
00645 #define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P          /*!< Break input BRK2 is active high */ 
00646 /**
00647   * @}
00648   */
00649 
00650 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
00651   * @{
00652   */
00653 #define LL_TIM_BREAK2_FILTER_FDIV1             ((uint32_t)0x00000000)   /*!< No filter, BRK acts asynchronously */ 
00654 #define LL_TIM_BREAK2_FILTER_FDIV1_N2          ((uint32_t)0x00100000)   /*!< fSAMPLING=fCK_INT, N=2 */ 
00655 #define LL_TIM_BREAK2_FILTER_FDIV1_N4          ((uint32_t)0x00200000)   /*!< fSAMPLING=fCK_INT, N=4 */ 
00656 #define LL_TIM_BREAK2_FILTER_FDIV1_N8          ((uint32_t)0x00300000)   /*!< fSAMPLING=fCK_INT, N=8 */ 
00657 #define LL_TIM_BREAK2_FILTER_FDIV2_N6          ((uint32_t)0x00400000)   /*!< fSAMPLING=fDTS/2, N=6 */ 
00658 #define LL_TIM_BREAK2_FILTER_FDIV2_N8          ((uint32_t)0x00500000)   /*!< fSAMPLING=fDTS/2, N=8 */ 
00659 #define LL_TIM_BREAK2_FILTER_FDIV4_N6          ((uint32_t)0x00600000)   /*!< fSAMPLING=fDTS/4, N=6 */ 
00660 #define LL_TIM_BREAK2_FILTER_FDIV4_N8          ((uint32_t)0x00700000)   /*!< fSAMPLING=fDTS/4, N=8 */ 
00661 #define LL_TIM_BREAK2_FILTER_FDIV8_N6          ((uint32_t)0x00800000)   /*!< fSAMPLING=fDTS/8, N=6 */ 
00662 #define LL_TIM_BREAK2_FILTER_FDIV8_N8          ((uint32_t)0x00900000)   /*!< fSAMPLING=fDTS/8, N=8 */ 
00663 #define LL_TIM_BREAK2_FILTER_FDIV16_N5         ((uint32_t)0x00A00000)   /*!< fSAMPLING=fDTS/16, N=5 */ 
00664 #define LL_TIM_BREAK2_FILTER_FDIV16_N6         ((uint32_t)0x00B00000)   /*!< fSAMPLING=fDTS/16, N=6 */ 
00665 #define LL_TIM_BREAK2_FILTER_FDIV16_N8         ((uint32_t)0x00C00000)   /*!< fSAMPLING=fDTS/16, N=8 */ 
00666 #define LL_TIM_BREAK2_FILTER_FDIV32_N5         ((uint32_t)0x00D00000)   /*!< fSAMPLING=fDTS/32, N=5 */ 
00667 #define LL_TIM_BREAK2_FILTER_FDIV32_N6         ((uint32_t)0x00E00000)   /*!< fSAMPLING=fDTS/32, N=6 */ 
00668 #define LL_TIM_BREAK2_FILTER_FDIV32_N8         ((uint32_t)0x00F00000)   /*!< fSAMPLING=fDTS/32, N=8 */ 
00669 /**
00670   * @}
00671   */
00672 
00673 /** @defgroup TIM_LL_EC_OSSI OSSI
00674   * @{
00675   */
00676 #define LL_TIM_OSSI_DISABLE                    ((uint32_t)0x00000000) /*!< When inactive, OCx/OCxN outputs are disabled */ 
00677 #define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI          /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ 
00678 /**
00679   * @}
00680   */
00681 
00682 /** @defgroup TIM_LL_EC_OSSR OSSR
00683   * @{
00684   */
00685 #define LL_TIM_OSSR_DISABLE                    ((uint32_t)0x00000000) /*!< When inactive, OCx/OCxN outputs are disabled */ 
00686 #define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR          /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ 
00687 /**
00688   * @}
00689   */
00690 
00691 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
00692   * @{
00693   */
00694 #define LL_TIM_BREAK_INPUT_BKIN                ((uint32_t)0x00000000)  /*!< TIMx_BKIN input */
00695 #define LL_TIM_BREAK_INPUT_BKIN2               ((uint32_t)0x00000004)  /*!< TIMx_BKIN2 input */
00696 /**
00697   * @}
00698   */
00699 
00700 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
00701   * @{
00702   */
00703 #define LL_TIM_BKIN_SOURCE_BKIN                TIM1_OR2_BKINE     /*!< BKIN input from AF controller */
00704 #define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_OR2_BKCMP1E   /*!< internal signal: COMP1 output */
00705 #define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_OR2_BKCMP2E   /*!< internal signal: COMP2 output */
00706 #define LL_TIM_BKIN_SOURCE_DFBK                TIM1_OR2_BKDFBK0E  /*!< internal signal: DFSDM break output */
00707 /**
00708   * @}
00709   */
00710 
00711 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
00712   * @{
00713   */
00714 #define LL_TIM_BKIN_POLARITY_LOW               ((uint32_t)0x00000000) /*!< BRK BKIN input is active low */ 
00715 #define LL_TIM_BKIN_POLARITY_HIGH              TIM1_OR2_BKINP         /*!< BRK BKIN input is active high */ 
00716 /**
00717   * @}
00718   */
00719 
00720 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMABURST BASEADDR
00721   * @{
00722   */
00723 #define LL_TIM_DMABURST_BASEADDR_CR1           ((uint32_t)0x00000000)                                                                                                                               /*!< TIMx_CR1 register is the DMA base address for DMA burst */ 
00724 #define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */ 
00725 #define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */ 
00726 #define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */ 
00727 #define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */ 
00728 #define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */ 
00729 #define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ 
00730 #define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ 
00731 #define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */ 
00732 #define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */ 
00733 #define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */ 
00734 #define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */ 
00735 #define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */ 
00736 #define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ 
00737 #define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ 
00738 #define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ 
00739 #define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ 
00740 #define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */ 
00741 #define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ 
00742 #define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ 
00743 #define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ 
00744 #define LL_TIM_DMABURST_BASEADDR_OR1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_OR1 register is the DMA base address for DMA burst */ 
00745 #define LL_TIM_DMABURST_BASEADDR_OR2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_OR2 register is the DMA base address for DMA burst */ 
00746 #define LL_TIM_DMABURST_BASEADDR_OR3           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */ 
00747 /**
00748   * @}
00749   */
00750 
00751 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMABURST LENGTH
00752   * @{
00753   */
00754 #define LL_TIM_DMABURST_LENGTH_1TRANSFER       ((uint32_t)0x00000000)                                          /*!< Transfer is done to 1 register starting from the DMA busrt base address */ 
00755 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA busrt base address */ 
00756 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA busrt base address */ 
00757 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA busrt base address */ 
00758 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA busrt base address */ 
00759 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA busrt base address */ 
00760 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA busrt base address */ 
00761 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA busrt base address */ 
00762 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA busrt base address */ 
00763 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA busrt base address */ 
00764 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA busrt base address */ 
00765 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA busrt base address */ 
00766 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA busrt base address */ 
00767 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA busrt base address */ 
00768 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA busrt base address */ 
00769 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA busrt base address */ 
00770 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA busrt base address */ 
00771 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA busrt base address */ 
00772 /**
00773   * @}
00774   */
00775 
00776 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP  TIM1 ETR ADC1 RMP
00777 * @{
00778 */
00779 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC   ((uint32_t)0x00000000 | TIM1_OR1_RMP_MASK)    /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */  
00780 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */  
00781 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK)  /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */  
00782 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK)   /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */ 
00783 /**
00784   * @}
00785   */
00786 
00787 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP  TIM1 ETR ADC3 RMP
00788 * @{
00789 */
00790 #define LL_TIM_TIM1_ETR_ADC3_RMP_NC   ((uint32_t)0x00000000 | TIM1_OR1_RMP_MASK)    /*!< TIM1_ETR is not connected to ADC3 analog watchdog  x*/  
00791 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 1 */  
00792 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 2 */  
00793 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK)   /*!< TIM1_ETR is connected to ADC3 analog watchdog 3 */  
00794 /**
00795   * @}
00796   */
00797 
00798 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 TI1 RMP
00799 * @{
00800 */
00801 #define LL_TIM_TIM1_TI1_RMP_GPIO  ((uint32_t)0x00000000 | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to GPIO */  
00802 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK)     /*!< TIM1 input capture 1 is connected to COMP1 output */  
00803 /**
00804   * @}
00805   */
00806 
00807 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8  TIM2 ITR1 RMP TIM8
00808 * @{
00809 */
00810 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO  ((uint32_t)0x00000000 | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to TIM8_TRGO */  
00811 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK)   /*!< TIM2_ITR1 is connected to OTG_FS SOF */  
00812 #define LL_TIM_TIM2_ETR_RMP_GPIO ((uint32_t)0x00000000 | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to GPIO */  
00813 #define LL_TIM_TIM2_ETR_RMP_LSE  (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK)    /*!< TIM2_ETR is connected to LSE  */  
00814 /**
00815   * @}
00816   */
00817 
00818 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 TI4 RMP
00819 * @{
00820 */
00821 #define LL_TIM_TIM2_TI4_RMP_GPIO        ((uint32_t)0x00000000 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to GPIO */  
00822 #define LL_TIM_TIM2_TI4_RMP_COMP1       (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK)   /*!< TIM2 input capture 4 is connected to COMP1_OUT */  
00823 #define LL_TIM_TIM2_TI4_RMP_COMP2       (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK)   /*!< TIM2 input capture 4 is connected to COMP2_OUT */  
00824 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK)     /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */  
00825 /**
00826   * @}
00827   */
00828 
00829 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 TI1 RMP
00830 * @{
00831 */
00832 #define LL_TIM_TIM3_TI1_RMP_GPIO         ((uint32_t)0x00000000 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to GPIO */  
00833 #define LL_TIM_TIM3_TI1_RMP_COMP1        (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK)   /*!< TIM3 input capture 1 is connected to COMP1_OUT */  
00834 #define LL_TIM_TIM3_TI1_RMP_COMP2        (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK)   /*!< TIM3 input capture 1 is connected to COMP2_OUT */  
00835 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2  (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK)     /*!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT */  
00836 /**
00837   * @}
00838   */
00839 
00840 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP  TIM8 ETR ADC2 RMP
00841 * @{
00842 */
00843 #define LL_TIM_TIM8_ETR_ADC2_RMP_NC   ((uint32_t)0x00000000 | TIM8_OR1_RMP_MASK)    /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */  
00844 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */  
00845 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */  
00846 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK)   /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */  
00847 /**
00848   * @}
00849   */
00850 
00851 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP  TIM8 ETR ADC3 RMP
00852 * @{
00853 */
00854 #define LL_TIM_TIM8_ETR_ADC3_RMP_NC   ((uint32_t)0x00000000 | TIM8_OR1_RMP_MASK)    /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */  
00855 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */  
00856 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */  
00857 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK)   /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */  
00858 /**
00859   * @}
00860   */
00861 
00862 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 TI1 RMP
00863 * @{
00864 */
00865 #define LL_TIM_TIM8_TI1_RMP_GPIO  ((uint32_t)0x00000000 | TIM8_OR1_RMP_MASK) /*!< TIM8 input capture 1 is connected to GPIO */  
00866 #define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK)     /*!< TIM8 input capture 1 is connected to COMP2 output */  
00867 /**
00868   * @}
00869   */
00870 
00871 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 TI1 RMP
00872 * @{
00873 */
00874 #define LL_TIM_TIM15_TI1_RMP_GPIO ((uint32_t)0x00000000 | TIM15_OR1_RMP_MASK) /*!< TIM15 input capture 1 is connected to GPIO */  
00875 #define LL_TIM_TIM15_TI1_RMP_LSE  (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK)    /*!< TIM15 input capture 1 is connected to LSE */  
00876 /**
00877   * @}
00878   */
00879 
00880 /** @defgroup TIM_LL_EC_TIM15_ENCODERMODE  TIM15 ENCODERMODE
00881 * @{
00882 */
00883 #define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION ((uint32_t)0x00000000 | TIM15_OR1_RMP_MASK)     /*!< No redirection*/  
00884 #define LL_TIM_TIM15_ENCODERMODE_TIM2          (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */  
00885 #define LL_TIM_TIM15_ENCODERMODE_TIM3          (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y*/  
00886 #define LL_TIM_TIM15_ENCODERMODE_TIM4          (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK)   /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */  
00887 /**
00888   * @}
00889   */
00890 
00891 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 TI1 RMP
00892 * @{
00893 */
00894 #define LL_TIM_TIM16_TI1_RMP_GPIO ((uint32_t)0x00000000 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to GPIO */  
00895 #define LL_TIM_TIM16_TI1_RMP_LSI  (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK)  /*!< TIM16 input capture 1 is connected to LSI */  
00896 #define LL_TIM_TIM16_TI1_RMP_LSE  (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK)  /*!< TIM16 input capture 1 is connected to LSE */  
00897 #define LL_TIM_TIM16_TI1_RMP_RTC  (TIM16_OR1_TI1_RMP | TIM16_OR1_RMP_MASK)    /*!< TIM16 input capture 1 is connected to RTC wakeup iterrupt */  
00898 /**
00899   * @}
00900   */
00901 
00902 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 TI1 RMP
00903 * @{
00904 */
00905 #define LL_TIM_TIM17_TI1_RMP_GPIO   ((uint32_t)0x00000000 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to GPIO */  
00906 #define LL_TIM_TIM17_TI1_RMP_MSI    (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK)  /*!< TIM17 input capture 1 is connected to MSI */  
00907 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK)  /*!< TIM17 input capture 1 is connected to HSE/32 */  
00908 #define LL_TIM_TIM17_TI1_RMP_MCO    (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK)    /*!< TIM17 input capture 1 is connected to MCO */  
00909 /**
00910   * @}
00911   */
00912 
00913 /**
00914   * @}
00915   */
00916   
00917 /* Exported macro ------------------------------------------------------------*/
00918 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
00919   * @{
00920   */
00921 
00922 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
00923   * @{
00924   */
00925 /**
00926   * @brief  Write a value in TIM register
00927   * @param  __INSTANCE__ TIM Instance
00928   * @param  __REG__ Register to be written
00929   * @param  __VALUE__ Value to be written in the register
00930   * @retval None
00931   */
00932 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00933 
00934 /**
00935   * @brief  Read a value in TIM register
00936   * @param  __INSTANCE__ TIM Instance
00937   * @param  __REG__ Register to be read
00938   * @retval Register value
00939   */
00940 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00941 /**
00942   * @}
00943   */
00944 
00945 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
00946   * @{
00947   */
00948 /**
00949   * @brief  HELPER macro retrieving the UIFCPY flag from the counter value
00950   * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
00951   * to TIMx_CNT register bit 31)
00952   * @param  __CNT__ Counter value
00953   * @retval UIF status bit
00954   */
00955 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
00956    (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> POSITION_VAL(TIM_CNT_UIFCPY))
00957 
00958 /**
00959   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to 
00960   * achieve the requested dead time duration
00961   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00962   * @param  __CKD__ This parameter can be one of the following values:
00963   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
00964   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
00965   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
00966   * @param  __DT__ deadtime duration (in us)
00967   * @retval DTG[0:7]
00968   */
00969 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
00970     ( (((uint64_t)((__DT__)*1000)) < ((DT_DELAY_1+1) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))           ? ((uint8_t)(((uint64_t)((__DT__)*1000)) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) :                            \
00971       (((uint64_t)((__DT__)*1000)) < (64 + (DT_DELAY_2+1)) * 2 * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (DT_RANGE_2 | ((uint8_t)(((((uint64_t)((__DT__)*1000))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1) - 64) & DT_DELAY_2)) :\
00972       (((uint64_t)((__DT__)*1000)) < (32 + (DT_DELAY_3+1)) * 8 * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (DT_RANGE_3 | ((uint8_t)(((((uint64_t)((__DT__)*1000))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3) - 32) & DT_DELAY_3)) :\
00973       (((uint64_t)((__DT__)*1000)) < (32 + (DT_DELAY_4+1)) * 16 * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (DT_RANGE_4 | ((uint8_t)(((((uint64_t)((__DT__)*1000))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4) - 32) & DT_DELAY_4)) :\
00974        0) 
00975 
00976 /**
00977   * @brief  HELPER macro calculating the prescaler value to achieve the required
00978   * counter clock frequency
00979   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00980   * @param  __CNTCLK__ counter clock frequency (in Hz)
00981   * @retval Prescaler value
00982   */
00983 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
00984    ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1) : 0
00985 
00986 /**
00987   * @brief  HELPER macro calculating the auto-reload value to achieve the
00988   * required output signal frequency
00989   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00990   * @param  __PSC__ prescaler
00991   * @param  __FREQ__ output signal frequency (in Hz)
00992   * @retval  Auto-reload value
00993   */
00994 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
00995      (((__TIMCLK__)/((__PSC__) + 1)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1)) - 1) : 0
00996 
00997 /**
00998   * @brief  HELPER macro calculating the compare value required to achieve the
00999   * required timer output compare active/inactive delay
01000   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01001   * @param  __PSC__ prescaler
01002   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01003   * @retval Compare value
01004   */
01005 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
01006 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
01007           / ((uint64_t)1000000 * (uint64_t)((__PSC__) + 1))))
01008 
01009 /**
01010   * @brief  HELPER macro calculating the auto-reload value to achieve the  
01011   *   *         required pulse duration (when the timer operates in one pulse mode)
01012   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01013   * @param  __PSC__ prescaler
01014   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01015   * @param  __PULSE__ pulse duration (in us)
01016   * @retval Auto-reload value
01017   */
01018 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
01019  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
01020            + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
01021 
01022 /**
01023   * @brief  HELPER macro retrieving the ratio of the input capture prescaler 
01024   * @param  __ICPSC__ Input capture prescaler value
01025   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
01026   */
01027 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
01028    ((uint32_t)(0x01 << (((__ICPSC__) >> 16) >> POSITION_VAL(TIM_CCMR1_IC1PSC))))
01029 
01030 /**
01031   * @}
01032   */
01033 
01034 
01035 /**
01036   * @}
01037   */
01038 
01039 /* Exported functions --------------------------------------------------------*/
01040 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
01041   * @{
01042   */
01043 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
01044   * @{
01045   */
01046 /**
01047   * @brief  Enable timer counter.
01048   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
01049   * @param  TIMx Timer instance
01050   * @retval None
01051   */
01052 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef * TIMx)
01053 {
01054   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
01055 }
01056 
01057 /**
01058   * @brief  Disable timer counter.
01059   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
01060   * @param  TIMx Timer instance
01061   * @retval None
01062   */
01063 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef * TIMx)
01064 {
01065   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
01066 }
01067 
01068 /**
01069   * @brief  Indicates whether the timer counter is enabled.
01070   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
01071   * @param  TIMx Timer instance
01072   * @retval State of bit (1 or 0).
01073   */
01074 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)
01075 {
01076   return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
01077 }
01078 
01079 /**
01080   * @brief  Enable update event generation.
01081   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
01082   * @param  TIMx Timer instance
01083   * @retval None
01084   */
01085 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)
01086 {
01087   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
01088 }
01089 
01090 /**
01091   * @brief  Disable update event generation.
01092   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
01093   * @param  TIMx Timer instance
01094   * @retval None
01095   */
01096 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)
01097 {
01098   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
01099 }
01100 
01101 /**
01102   * @brief  Indicates whether update event generation is enabled.
01103   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
01104   * @param  TIMx Timer instance
01105   * @retval State of bit (1 or 0).
01106   */
01107 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)
01108 {
01109   return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
01110 }
01111 
01112 /**
01113   * @brief  Set update event source
01114   * @note
01115   *   Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events 
01116   *   generate an update interrupt or DMA request if enabled:
01117   *     Counter overflow/underflow
01118   *     Setting the UG bit
01119   *     Update generation through the slave mode controller
01120   *   Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter 
01121   *   overflow/underflow generates an update interrupt or DMA request if enabled.
01122   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
01123   * @param  TIMx Timer instance
01124   * @param  UpdateSource This parameter can be one of the following values:
01125   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01126   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01127   * @retval None
01128   */
01129 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx, uint32_t UpdateSource)
01130 {
01131   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
01132 }
01133 
01134 /**
01135   * @brief  Get actual event update source
01136   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
01137   * @param  TIMx Timer instance
01138   * @retval Returned value can be one of the following values:
01139   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01140   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01141   */
01142 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)
01143 {
01144   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
01145 }
01146 
01147 /**
01148   * @brief  Set one pulse mode (one shot v.s. repetitive).
01149   * @rmtoll CR1          OPM           LL_TIM_GetUpdateSource
01150   * @param  TIMx Timer instance
01151   * @param  OnePulseMode This parameter can be one of the following values:
01152   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01153   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01154   * @retval None
01155   */
01156 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx, uint32_t OnePulseMode)
01157 {
01158   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
01159 }
01160 
01161 /**
01162   * @brief  Get actual one pulse mode.
01163   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
01164   * @param  TIMx Timer instance
01165   * @retval Returned value can be one of the following values:
01166   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01167   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01168   */
01169 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)
01170 {
01171   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
01172 }
01173 
01174 /**
01175   * @brief  Set the timer counter counting mode.
01176   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
01177   * the counter mode selection feature is supported by a timer instance.
01178   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
01179   *         CR1          CMS           LL_TIM_SetCounterMode
01180   * @param  TIMx Timer instance
01181   * @param  CounterMode This parameter can be one of the following values:
01182   *         @arg @ref LL_TIM_COUNTERMODE_UP
01183   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01184   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01185   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01186   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01187   * @retval None
01188   */
01189 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef * TIMx, uint32_t CounterMode)
01190 {
01191   MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
01192 }
01193 
01194 /**
01195   * @brief  Get actual counter mode.
01196   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
01197   * the counter mode selection feature is supported by a timer instance.
01198   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
01199   *         CR1          CMS           LL_TIM_GetCounterMode
01200   * @param  TIMx Timer instance
01201   * @retval Returned value can be one of the following values:
01202   *         @arg @ref LL_TIM_COUNTERMODE_UP
01203   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01204   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01205   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01206   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01207   */
01208 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)
01209 {
01210   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
01211 }
01212 
01213 /**
01214   * @brief  Enable auto-reload (ARR) preload.
01215   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
01216   * @param  TIMx Timer instance
01217   * @retval None
01218   */
01219 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)
01220 {
01221   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
01222 }
01223 
01224 /**
01225   * @brief  Disable auto-reload (ARR) preload.
01226   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
01227   * @param  TIMx Timer instance
01228   * @retval None
01229   */
01230 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)
01231 {
01232   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
01233 }
01234 
01235 /**
01236   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
01237   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
01238   * @param  TIMx Timer instance
01239   * @retval State of bit (1 or 0).
01240   */
01241 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)
01242 {
01243   return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
01244 }
01245 
01246 /**
01247   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01248   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 
01249   * whether or not the clock division feature is supported by the a timer
01250   * instance.
01251   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
01252   * @param  TIMx Timer instance
01253   * @param  ClockDivision This parameter can be one of the following values:
01254   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01255   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01256   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01257   * @retval None
01258   */
01259 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef * TIMx, uint32_t ClockDivision)
01260 {
01261   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
01262 }
01263 
01264 /**
01265   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01266   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 
01267   * whether or not the clock division feature is supported by the a timer
01268   * instance.
01269   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
01270   * @param  TIMx Timer instance
01271   * @retval Returned value can be one of the following values:
01272   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01273   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01274   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01275   */
01276 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)
01277 {
01278   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
01279 }
01280 
01281 /**
01282   * @brief  Set the counter value.
01283   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
01284   * whether or not a timer instance supports a 32 bits counter.
01285   * @rmtoll CNT          CNT           LL_TIM_SetCounter
01286   * @param  TIMx Timer instance
01287   * @param  Counter Counter value
01288   * @retval None
01289   */
01290 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef * TIMx, uint32_t Counter)
01291 {
01292   WRITE_REG(TIMx->CNT, Counter);
01293 }
01294 
01295 /**
01296   * @brief  Get the counter value.
01297   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
01298   * whether or not a timer instance supports a 32 bits counter.
01299   * counter.
01300   * @rmtoll CNT          CNT           LL_TIM_GetCounter
01301   * @param  TIMx Timer instance
01302   * @retval Counter value
01303   */
01304 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef * TIMx)
01305 {
01306   return (uint32_t)(READ_REG(TIMx->CNT));
01307 }
01308 
01309 /**
01310   * @brief  Get the current direction of the counter
01311   * @rmtoll CR1          DIR           LL_TIM_GetDirection
01312   * @param  TIMx Timer instance
01313   * @retval Returned value can be one of the following values:
01314   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
01315   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
01316   */
01317 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef * TIMx)
01318 {
01319   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
01320 }
01321 
01322 /**
01323   * @brief  Set the prescaler value.
01324   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
01325   * @note The prescaler can be changed on the fly as this control register is buffered. The new
01326   * prescaler ratio is taken into account at the next update event.
01327   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
01328   * @param  TIMx Timer instance
01329   * @param  Prescaler Between 0 and 65535
01330   * @retval None
01331   */
01332 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef * TIMx, uint32_t Prescaler)
01333 {
01334   WRITE_REG(TIMx->PSC, Prescaler);
01335 }
01336 
01337 /**
01338   * @brief  Get the prescaler value.
01339   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
01340   * @param  TIMx Timer instance
01341   * @retval Prescaler value
01342   */
01343 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)
01344 {
01345   return (uint32_t)(READ_REG(TIMx->PSC));
01346 }
01347 
01348 /**
01349   * @brief  Set the auto-reload value.
01350   * @note The counter is blocked while the auto-reload value is null.
01351   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
01352   * whether or not a timer instance supports a 32 bits counter.
01353   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
01354   * @param  TIMx Timer instance
01355   * @param  AutoReload Between 0 and 65535
01356   * @retval None
01357   */
01358 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef * TIMx, uint32_t AutoReload)
01359 {
01360   WRITE_REG(TIMx->ARR, AutoReload);
01361 }
01362 
01363 /**
01364   * @brief  Get the auto-reload value.
01365   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
01366   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
01367   * whether or not a timer instance supports a 32 bits counter.
01368   * @param  TIMx Timer instance
01369   * @retval Auto-reload value
01370   */
01371 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)
01372 {
01373   return (uint32_t)(READ_REG(TIMx->ARR));
01374 }
01375 
01376 /**
01377   * @brief  Set the repetition counter value.
01378   * @note For advanced timer instances RepetitionCounter can be up to 65535.
01379   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 
01380   * whether or not a timer instance supports a repetition counter.
01381   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
01382   * @param  TIMx Timer instance
01383   * @param  RepetitionCounter Between 0 and 255
01384   * @retval None
01385   */
01386 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx, uint32_t RepetitionCounter)
01387 {
01388   WRITE_REG(TIMx->RCR, RepetitionCounter);
01389 }
01390 
01391 /**
01392   * @brief  Get the repetition counter value.
01393   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 
01394   * whether or not a timer instance supports a repetition counter.
01395   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
01396   * @param  TIMx Timer instance
01397   * @retval Repetition counter value
01398   */
01399 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx)
01400 {
01401   return (uint32_t)(READ_REG(TIMx->RCR));
01402 }
01403 
01404 /**
01405   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 
01406   * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
01407   * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
01408   * @param  TIMx Timer instance
01409   * @retval None
01410   */
01411 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)
01412 {
01413   SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01414 }
01415 
01416 /**
01417   * @brief  Disable update interrupt flag (UIF) remapping.
01418   * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
01419   * @param  TIMx Timer instance
01420   * @retval None
01421   */
01422 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)
01423 {
01424   CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01425 }
01426 
01427 /**
01428   * @}
01429   */
01430 
01431 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
01432   * @{
01433   */
01434 /**
01435   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01436   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, 
01437   * they are updated only when a commutation event (COM) occurs.
01438   * @note Only on channels that have a complementary output.
01439   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 
01440   * whether or not a timer instance is able to generate a commutation event.
01441   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
01442   * @param  TIMx Timer instance
01443   * @retval None
01444   */
01445 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)
01446 {
01447   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
01448 }
01449 
01450 /**
01451   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01452   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 
01453   * whether or not a timer instance is able to generate a commutation event.
01454   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
01455   * @param  TIMx Timer instance
01456   * @retval None
01457   */
01458 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)
01459 {
01460   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
01461 }
01462 
01463 /**
01464   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
01465   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 
01466   * whether or not a timer instance is able to generate a commutation event.
01467   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
01468   * @param  TIMx Timer instance
01469   * @param  CCUpdateSource This parameter can be one of the following values:
01470   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
01471   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
01472   * @retval None
01473   */
01474 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx, uint32_t CCUpdateSource)
01475 {
01476   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
01477 }
01478 
01479 /**
01480   * @brief  Set the trigger of the capture/compare DMA request.
01481   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
01482   * @param  TIMx Timer instance
01483   * @param  DMAReqTrigger This parameter can be one of the following values:
01484   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01485   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01486   * @retval None
01487   */
01488 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx, uint32_t DMAReqTrigger)
01489 {
01490   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
01491 }
01492 
01493 /**
01494   * @brief  Set the lock level to freeze the
01495   * configuration of several  capture/compare parameters.
01496   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
01497   * the lock mechanism is supported by a timer instance.
01498   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
01499   * @param  TIMx Timer instance
01500   * @param  LockLevel This parameter can be one of the following values:
01501   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
01502   *         @arg @ref LL_TIM_LOCKLEVEL_1
01503   *         @arg @ref LL_TIM_LOCKLEVEL_2
01504   *         @arg @ref LL_TIM_LOCKLEVEL_3
01505   * @retval None
01506   */
01507 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx, uint32_t LockLevel)
01508 {
01509   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
01510 }
01511 
01512 /**
01513   * @brief  Enable capture/compare channels.
01514   * @note Macros IS_TIM_CCX_INSTANCE(TIMx, Channel) or 
01515   * IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether or not
01516   * a channel is supported by the a timer instance.
01517   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
01518   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
01519   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
01520   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
01521   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
01522   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
01523   *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
01524   *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
01525   *         CCER         CC6E          LL_TIM_CC_EnableChannel\n
01526   * @param  TIMx Timer instance
01527   * @param  Channels This parameter can be a combination of the following values:
01528   *         @arg @ref LL_TIM_CHANNEL_CH1
01529   *         @arg @ref LL_TIM_CHANNEL_CH1N
01530   *         @arg @ref LL_TIM_CHANNEL_CH2
01531   *         @arg @ref LL_TIM_CHANNEL_CH2N
01532   *         @arg @ref LL_TIM_CHANNEL_CH3
01533   *         @arg @ref LL_TIM_CHANNEL_CH3N
01534   *         @arg @ref LL_TIM_CHANNEL_CH4
01535   *         @arg @ref LL_TIM_CHANNEL_CH5
01536   *         @arg @ref LL_TIM_CHANNEL_CH6
01537   * @retval None
01538   */
01539 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx, uint32_t Channels)
01540 {
01541   SET_BIT(TIMx->CCER, Channels);
01542 }
01543 
01544 /**
01545   * @brief  Disable capture/compare channels.
01546   * @note Macros IS_TIM_CCX_INSTANCE(TIMx, Channel) or 
01547   * IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether or not
01548   * a channel is supported by the a timer instance.
01549   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
01550   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
01551   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
01552   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
01553   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
01554   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
01555   *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
01556   *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
01557   *         CCER         CC6E          LL_TIM_CC_EnableChannel\n
01558   * @param  TIMx Timer instance
01559   * @param  Channels This parameter can be a combination of the following values:
01560   *         @arg @ref LL_TIM_CHANNEL_CH1
01561   *         @arg @ref LL_TIM_CHANNEL_CH1N
01562   *         @arg @ref LL_TIM_CHANNEL_CH2
01563   *         @arg @ref LL_TIM_CHANNEL_CH2N
01564   *         @arg @ref LL_TIM_CHANNEL_CH3
01565   *         @arg @ref LL_TIM_CHANNEL_CH3N
01566   *         @arg @ref LL_TIM_CHANNEL_CH4
01567   *         @arg @ref LL_TIM_CHANNEL_CH5
01568   *         @arg @ref LL_TIM_CHANNEL_CH6
01569   * @retval None
01570   */
01571 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx, uint32_t Channels)
01572 {
01573   CLEAR_BIT(TIMx->CCER, Channels);
01574 }
01575 
01576 /**
01577   * @}
01578   */
01579 
01580 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
01581   * @{
01582   */
01583 /**
01584   * @brief  Configure an output channel.
01585   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
01586   * or not a channel is supported by the a timer instance.
01587   * @rmtoll CCMR1        OC1M          LL_TIM_OC_ConfigOutput\n
01588   *         CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
01589   *         CCMR1        OC2M          LL_TIM_OC_ConfigOutput\n
01590   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
01591   *         CCMR2        OC3M          LL_TIM_OC_ConfigOutput\n
01592   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
01593   *         CCMR2        OC4M          LL_TIM_OC_ConfigOutput\n
01594   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
01595   *         CCMR3        OC5M          LL_TIM_OC_ConfigOutput\n
01596   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
01597   *         CCMR3        OC6M          LL_TIM_OC_ConfigOutput\n
01598   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
01599   *         CCER         OC1P          LL_TIM_OC_ConfigOutput\n
01600   *         CCER         OC2P          LL_TIM_OC_ConfigOutput\n
01601   *         CCER         OC3P          LL_TIM_OC_ConfigOutput\n
01602   *         CCER         OC4P          LL_TIM_OC_ConfigOutput\n
01603   *         CCER         OC5P          LL_TIM_OC_ConfigOutput\n
01604   *         CCER         OC6P          LL_TIM_OC_ConfigOutput\n
01605   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
01606   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
01607   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
01608   *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
01609   *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
01610   *         CR2          OIS6          LL_TIM_OC_ConfigOutput\n
01611   * @param  TIMx Timer instance
01612   * @param  Channel This parameter can be one of the following values:
01613   *         @arg @ref LL_TIM_CHANNEL_CH1
01614   *         @arg @ref LL_TIM_CHANNEL_CH2
01615   *         @arg @ref LL_TIM_CHANNEL_CH3
01616   *         @arg @ref LL_TIM_CHANNEL_CH4
01617   *         @arg @ref LL_TIM_CHANNEL_CH5
01618   *         @arg @ref LL_TIM_CHANNEL_CH6
01619   * @param  Configuration This parameter must be a combination of all the following values:
01620   *         @arg @ref LL_TIM_OCMODE_FROZEN or ... or @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
01621   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
01622   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
01623   * @retval None
01624   */
01625 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Configuration)
01626 {
01627   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01628   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
01629   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  (Configuration & (TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S)) << SHIFT_TAB_OCxx[iChannel]);
01630   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
01631   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
01632 }
01633 
01634 /**
01635   * @brief  Configure a complementary output channel.
01636   * @note Macro IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether
01637   * or not a complementary channel is supported by the a timer instance.
01638   * @rmtoll CCER         CC1NP          LL_TIM_OC_ConfigOutputN\n
01639   *         CCER         CC2NP          LL_TIM_OC_ConfigOutputN\n
01640   *         CCER         CC3NP          LL_TIM_OC_ConfigOutputN\n
01641   *         CR2          OIS1N          LL_TIM_OC_ConfigOutputN\n
01642   *         CR2          OIS2N          LL_TIM_OC_ConfigOutputN\n
01643   *         CR2          OIS3N          LL_TIM_OC_ConfigOutputN\n
01644   * @param  TIMx Timer instance
01645   * @param  Channel This parameter can be one of the following values:
01646   *         @arg @ref LL_TIM_CHANNEL_CH1N
01647   *         @arg @ref LL_TIM_CHANNEL_CH2N
01648   *         @arg @ref LL_TIM_CHANNEL_CH3N
01649   * @param  Polarity This parameter can be one of the following values:
01650   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
01651   *         @arg @ref LL_TIM_OCPOLARITY_LOW
01652   * @param  IdleState This parameter can be one of the following values:
01653   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
01654   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
01655   * @retval None
01656   */
01657 __STATIC_INLINE void LL_TIM_OC_ConfigOutputN(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Polarity, uint32_t IdleState)
01658 {
01659   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01660   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
01661   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
01662 }
01663 
01664 /**
01665   * @brief  Set the output compare mode of an output channel.
01666   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
01667   * or not a channel is supported by the a timer instance.
01668   * @rmtoll CCMR1        OC1M          LL_TIM_OC_ConfigOutput\n
01669   *         CCMR1        OC2M          LL_TIM_OC_ConfigOutput\n
01670   *         CCMR2        OC3M          LL_TIM_OC_ConfigOutput\n
01671   *         CCMR2        OC4M          LL_TIM_OC_ConfigOutput\n
01672   *         CCMR3        OC5M          LL_TIM_OC_ConfigOutput\n
01673   *         CCMR3        OC6M          LL_TIM_OC_ConfigOutput\n
01674   * @param  TIMx Timer instance
01675   * @param  Channel This parameter can be one of the following values:
01676   *         @arg @ref LL_TIM_CHANNEL_CH1
01677   *         @arg @ref LL_TIM_CHANNEL_CH2
01678   *         @arg @ref LL_TIM_CHANNEL_CH3
01679   *         @arg @ref LL_TIM_CHANNEL_CH4
01680   *         @arg @ref LL_TIM_CHANNEL_CH5
01681   *         @arg @ref LL_TIM_CHANNEL_CH6
01682   * @param  Mode This parameter can be one of the following values:
01683   *         @arg @ref LL_TIM_OCMODE_FROZEN
01684   *         @arg @ref LL_TIM_OCMODE_ACTIVE
01685   *         @arg @ref LL_TIM_OCMODE_INACTIVE
01686   *         @arg @ref LL_TIM_OCMODE_TOGGLE
01687   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
01688   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
01689   *         @arg @ref LL_TIM_OCMODE_PWM1
01690   *         @arg @ref LL_TIM_OCMODE_PWM2
01691   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
01692   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
01693   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
01694   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
01695   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
01696   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
01697   * @retval None
01698   */
01699 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Mode)
01700 {
01701   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01702   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
01703   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  Mode << SHIFT_TAB_OCxx[iChannel]);
01704 }
01705 
01706 /**
01707   * @brief  Get the output compare mode of an output channel.
01708   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
01709   * or not a channel is supported by the a timer instance.
01710   * @rmtoll CCMR1        OC1M          LL_TIM_OC_ConfigOutput\n
01711   *         CCMR1        OC2M          LL_TIM_OC_ConfigOutput\n
01712   *         CCMR2        OC3M          LL_TIM_OC_ConfigOutput\n
01713   *         CCMR2        OC4M          LL_TIM_OC_ConfigOutput\n
01714   *         CCMR3        OC5M          LL_TIM_OC_ConfigOutput\n
01715   *         CCMR3        OC6M          LL_TIM_OC_ConfigOutput\n
01716   * @param  TIMx Timer instance
01717   * @param  Channel This parameter can be one of the following values:
01718   *         @arg @ref LL_TIM_CHANNEL_CH1
01719   *         @arg @ref LL_TIM_CHANNEL_CH2
01720   *         @arg @ref LL_TIM_CHANNEL_CH3
01721   *         @arg @ref LL_TIM_CHANNEL_CH4
01722   *         @arg @ref LL_TIM_CHANNEL_CH5
01723   *         @arg @ref LL_TIM_CHANNEL_CH6
01724   * @retval Returned value can be one of the following values:
01725   *         @arg @ref LL_TIM_OCMODE_FROZEN
01726   *         @arg @ref LL_TIM_OCMODE_ACTIVE
01727   *         @arg @ref LL_TIM_OCMODE_INACTIVE
01728   *         @arg @ref LL_TIM_OCMODE_TOGGLE
01729   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
01730   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
01731   *         @arg @ref LL_TIM_OCMODE_PWM1
01732   *         @arg @ref LL_TIM_OCMODE_PWM2
01733   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
01734   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
01735   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
01736   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
01737   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
01738   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
01739   */
01740 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef * TIMx, uint32_t Channel)
01741 {
01742   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01743   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));  
01744   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
01745 }
01746 
01747 /**
01748   * @brief  Set the polarity of an output channel.
01749   * @note Macros IS_TIM_CCX_INSTANCE(TIMx, Channel) or 
01750   * IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether or not
01751   * a channel is supported by the a timer instance.
01752   * @rmtoll CCER         CC1P          LL_TIM_CC_EnableChannel\n
01753   *         CCER         CC1NP         LL_TIM_CC_EnableChannel\n
01754   *         CCER         CC2P          LL_TIM_CC_EnableChannel\n
01755   *         CCER         CC2NP         LL_TIM_CC_EnableChannel\n
01756   *         CCER         CC3P          LL_TIM_CC_EnableChannel\n
01757   *         CCER         CC3NP         LL_TIM_CC_EnableChannel\n
01758   *         CCER         CC4P          LL_TIM_CC_EnableChannel\n
01759   *         CCER         CC5P          LL_TIM_CC_EnableChannel\n
01760   *         CCER         CC6P          LL_TIM_CC_EnableChannel\n
01761   * @param  TIMx Timer instance
01762   * @param  Channel This parameter can be one of the following values:
01763   *         @arg @ref LL_TIM_CHANNEL_CH1
01764   *         @arg @ref LL_TIM_CHANNEL_CH1N
01765   *         @arg @ref LL_TIM_CHANNEL_CH2
01766   *         @arg @ref LL_TIM_CHANNEL_CH2N
01767   *         @arg @ref LL_TIM_CHANNEL_CH3
01768   *         @arg @ref LL_TIM_CHANNEL_CH3N
01769   *         @arg @ref LL_TIM_CHANNEL_CH4
01770   *         @arg @ref LL_TIM_CHANNEL_CH5
01771   *         @arg @ref LL_TIM_CHANNEL_CH6
01772   * @param  Polarity This parameter can be one of the following values:
01773   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
01774   *         @arg @ref LL_TIM_OCPOLARITY_LOW
01775   * @retval None
01776   */
01777 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Polarity)
01778 {
01779   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01780   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
01781 }
01782 
01783 /**
01784   * @brief  Get the polarity of an output channel.
01785   * @note Macros IS_TIM_CCX_INSTANCE(TIMx, Channel) or 
01786   * IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether or not
01787   * a channel is supported by the a timer instance.
01788   * @rmtoll CCER         CC1P          LL_TIM_CC_EnableChannel\n
01789   *         CCER         CC1NP         LL_TIM_CC_EnableChannel\n
01790   *         CCER         CC2P          LL_TIM_CC_EnableChannel\n
01791   *         CCER         CC2NP         LL_TIM_CC_EnableChannel\n
01792   *         CCER         CC3P          LL_TIM_CC_EnableChannel\n
01793   *         CCER         CC3NP         LL_TIM_CC_EnableChannel\n
01794   *         CCER         CC4P          LL_TIM_CC_EnableChannel\n
01795   *         CCER         CC5P          LL_TIM_CC_EnableChannel\n
01796   *         CCER         CC6P          LL_TIM_CC_EnableChannel\n
01797   * @param  TIMx Timer instance
01798   * @param  Channel This parameter can be one of the following values:
01799   *         @arg @ref LL_TIM_CHANNEL_CH1
01800   *         @arg @ref LL_TIM_CHANNEL_CH1N
01801   *         @arg @ref LL_TIM_CHANNEL_CH2
01802   *         @arg @ref LL_TIM_CHANNEL_CH2N
01803   *         @arg @ref LL_TIM_CHANNEL_CH3
01804   *         @arg @ref LL_TIM_CHANNEL_CH3N
01805   *         @arg @ref LL_TIM_CHANNEL_CH4
01806   *         @arg @ref LL_TIM_CHANNEL_CH5
01807   *         @arg @ref LL_TIM_CHANNEL_CH6
01808   * @retval Returned value can be one of the following values:
01809   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
01810   *         @arg @ref LL_TIM_OCPOLARITY_LOW
01811   */
01812 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx, uint32_t Channel)
01813 {
01814   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01815   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
01816 }
01817 
01818 /**
01819   * @brief  Set the IDLE state of an output channel
01820   * @note Macros IS_TIM_CCX_INSTANCE(TIMx, Channel) or 
01821   * IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether or not
01822   * a channel is supported by the a timer instance.
01823   * @rmtoll CR2         OIS1          LL_TIM_CC_EnableChannel\n
01824   *         CR2         OIS2N         LL_TIM_CC_EnableChannel\n
01825   *         CR2         OIS2          LL_TIM_CC_EnableChannel\n
01826   *         CR2         OIS2N         LL_TIM_CC_EnableChannel\n
01827   *         CR2         OIS3          LL_TIM_CC_EnableChannel\n
01828   *         CR2         OIS3N         LL_TIM_CC_EnableChannel\n
01829   *         CR2         OIS4          LL_TIM_CC_EnableChannel\n
01830   *         CR2         OIS5          LL_TIM_CC_EnableChannel\n
01831   *         CR2         OIS6          LL_TIM_CC_EnableChannel\n
01832   * @param  TIMx Timer instance
01833   * @param  Channel This parameter can be one of the following values:
01834   *         @arg @ref LL_TIM_CHANNEL_CH1
01835   *         @arg @ref LL_TIM_CHANNEL_CH1N
01836   *         @arg @ref LL_TIM_CHANNEL_CH2
01837   *         @arg @ref LL_TIM_CHANNEL_CH2N
01838   *         @arg @ref LL_TIM_CHANNEL_CH3
01839   *         @arg @ref LL_TIM_CHANNEL_CH3N
01840   *         @arg @ref LL_TIM_CHANNEL_CH4
01841   *         @arg @ref LL_TIM_CHANNEL_CH5
01842   *         @arg @ref LL_TIM_CHANNEL_CH6
01843   * @param  IdleState This parameter can be one of the following values:
01844   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
01845   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
01846   * @retval None
01847   */
01848 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t IdleState)
01849 {
01850   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01851   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
01852 }
01853 
01854 /**
01855   * @brief  Get the IDLE state of an output channel
01856   * @note Macros IS_TIM_CCX_INSTANCE(TIMx, Channel) or 
01857   * IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether or not
01858   * a channel is supported by the a timer instance.
01859   * @rmtoll CR2         OIS1          LL_TIM_CC_EnableChannel\n
01860   *         CR2         OIS2N         LL_TIM_CC_EnableChannel\n
01861   *         CR2         OIS2          LL_TIM_CC_EnableChannel\n
01862   *         CR2         OIS2N         LL_TIM_CC_EnableChannel\n
01863   *         CR2         OIS3          LL_TIM_CC_EnableChannel\n
01864   *         CR2         OIS3N         LL_TIM_CC_EnableChannel\n
01865   *         CR2         OIS4          LL_TIM_CC_EnableChannel\n
01866   *         CR2         OIS5          LL_TIM_CC_EnableChannel\n
01867   *         CR2         OIS6          LL_TIM_CC_EnableChannel\n
01868   * @param  TIMx Timer instance
01869   * @param  Channel This parameter can be one of the following values:
01870   *         @arg @ref LL_TIM_CHANNEL_CH1
01871   *         @arg @ref LL_TIM_CHANNEL_CH1N
01872   *         @arg @ref LL_TIM_CHANNEL_CH2
01873   *         @arg @ref LL_TIM_CHANNEL_CH2N
01874   *         @arg @ref LL_TIM_CHANNEL_CH3
01875   *         @arg @ref LL_TIM_CHANNEL_CH3N
01876   *         @arg @ref LL_TIM_CHANNEL_CH4
01877   *         @arg @ref LL_TIM_CHANNEL_CH5
01878   *         @arg @ref LL_TIM_CHANNEL_CH6
01879   * @retval Returned value can be one of the following values:
01880   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
01881   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
01882   */
01883 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx, uint32_t Channel)
01884 {
01885   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01886   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
01887 }
01888 
01889 /**
01890   * @brief  Enable fast mode for the output channel.
01891   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
01892   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
01893   * or not a channel is supported by the a timer instance.
01894   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_ConfigOutput\n
01895   *         CCMR1        OC2FE          LL_TIM_OC_ConfigOutput\n
01896   *         CCMR2        OC3FE          LL_TIM_OC_ConfigOutput\n
01897   *         CCMR2        OC4FE          LL_TIM_OC_ConfigOutput\n
01898   *         CCMR3        OC5FE          LL_TIM_OC_ConfigOutput\n
01899   *         CCMR3        OC6FE          LL_TIM_OC_ConfigOutput\n
01900   * @param  TIMx Timer instance
01901   * @param  Channel This parameter can be one of the following values:
01902   *         @arg @ref LL_TIM_CHANNEL_CH1
01903   *         @arg @ref LL_TIM_CHANNEL_CH2
01904   *         @arg @ref LL_TIM_CHANNEL_CH3
01905   *         @arg @ref LL_TIM_CHANNEL_CH4
01906   *         @arg @ref LL_TIM_CHANNEL_CH5
01907   *         @arg @ref LL_TIM_CHANNEL_CH6
01908   * @retval None
01909   */
01910 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx, uint32_t Channel)
01911 {
01912   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01913   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
01914   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
01915 
01916 }
01917 
01918 /**
01919   * @brief  Disable fast mode for the output channel.
01920   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
01921   * or not a channel is supported by the a timer instance.
01922   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_ConfigOutput\n
01923   *         CCMR1        OC2FE          LL_TIM_OC_ConfigOutput\n
01924   *         CCMR2        OC3FE          LL_TIM_OC_ConfigOutput\n
01925   *         CCMR2        OC4FE          LL_TIM_OC_ConfigOutput\n
01926   *         CCMR3        OC5FE          LL_TIM_OC_ConfigOutput\n
01927   *         CCMR3        OC6FE          LL_TIM_OC_ConfigOutput\n
01928   * @param  TIMx Timer instance
01929   * @param  Channel This parameter can be one of the following values:
01930   *         @arg @ref LL_TIM_CHANNEL_CH1
01931   *         @arg @ref LL_TIM_CHANNEL_CH2
01932   *         @arg @ref LL_TIM_CHANNEL_CH3
01933   *         @arg @ref LL_TIM_CHANNEL_CH4
01934   *         @arg @ref LL_TIM_CHANNEL_CH5
01935   *         @arg @ref LL_TIM_CHANNEL_CH6
01936   * @retval None
01937   */
01938 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx, uint32_t Channel)
01939 {
01940   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01941   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
01942   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
01943 
01944 }
01945 
01946 /**
01947   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
01948   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
01949   * or not a channel is supported by the a timer instance.
01950   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_ConfigOutput\n
01951   *         CCMR1        OC2PE          LL_TIM_OC_ConfigOutput\n
01952   *         CCMR2        OC3PE          LL_TIM_OC_ConfigOutput\n
01953   *         CCMR2        OC4PE          LL_TIM_OC_ConfigOutput\n
01954   *         CCMR3        OC5PE          LL_TIM_OC_ConfigOutput\n
01955   *         CCMR3        OC6PE          LL_TIM_OC_ConfigOutput\n
01956   * @param  TIMx Timer instance
01957   * @param  Channel This parameter can be one of the following values:
01958   *         @arg @ref LL_TIM_CHANNEL_CH1
01959   *         @arg @ref LL_TIM_CHANNEL_CH2
01960   *         @arg @ref LL_TIM_CHANNEL_CH3
01961   *         @arg @ref LL_TIM_CHANNEL_CH4
01962   *         @arg @ref LL_TIM_CHANNEL_CH5
01963   *         @arg @ref LL_TIM_CHANNEL_CH6
01964   * @retval None
01965   */
01966 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx, uint32_t Channel)
01967 {
01968   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01969   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
01970   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
01971 }
01972 
01973 /**
01974   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
01975   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
01976   * or not a channel is supported by the a timer instance.
01977   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_ConfigOutput\n
01978   *         CCMR1        OC2PE          LL_TIM_OC_ConfigOutput\n
01979   *         CCMR2        OC3PE          LL_TIM_OC_ConfigOutput\n
01980   *         CCMR2        OC4PE          LL_TIM_OC_ConfigOutput\n
01981   *         CCMR3        OC5PE          LL_TIM_OC_ConfigOutput\n
01982   *         CCMR3        OC6PE          LL_TIM_OC_ConfigOutput\n
01983   * @param  TIMx Timer instance
01984   * @param  Channel This parameter can be one of the following values:
01985   *         @arg @ref LL_TIM_CHANNEL_CH1
01986   *         @arg @ref LL_TIM_CHANNEL_CH2
01987   *         @arg @ref LL_TIM_CHANNEL_CH3
01988   *         @arg @ref LL_TIM_CHANNEL_CH4
01989   *         @arg @ref LL_TIM_CHANNEL_CH5
01990   *         @arg @ref LL_TIM_CHANNEL_CH6
01991   * @retval None
01992   */
01993 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx, uint32_t Channel)
01994 {
01995   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01996   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
01997   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
01998 
01999 }
02000 
02001 /**
02002   * @brief  Enable clearing the output channel on an external event.
02003   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02004   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02005   * or not a timer instance can clear the OCxREF signal on an external event.
02006   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
02007   * or not a channel is supported by the a timer instance.
02008   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_ConfigOutput\n
02009   *         CCMR1        OC2CE          LL_TIM_OC_ConfigOutput\n
02010   *         CCMR2        OC3CE          LL_TIM_OC_ConfigOutput\n
02011   *         CCMR2        OC4CE          LL_TIM_OC_ConfigOutput\n
02012   *         CCMR3        OC5CE          LL_TIM_OC_ConfigOutput\n
02013   *         CCMR3        OC6CE          LL_TIM_OC_ConfigOutput\n
02014   * @param  TIMx Timer instance
02015   * @param  Channel This parameter can be one of the following values:
02016   *         @arg @ref LL_TIM_CHANNEL_CH1
02017   *         @arg @ref LL_TIM_CHANNEL_CH2
02018   *         @arg @ref LL_TIM_CHANNEL_CH3
02019   *         @arg @ref LL_TIM_CHANNEL_CH4
02020   *         @arg @ref LL_TIM_CHANNEL_CH5
02021   *         @arg @ref LL_TIM_CHANNEL_CH6
02022   * @retval None
02023   */
02024 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx, uint32_t Channel)
02025 {
02026   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02027   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02028   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02029 }
02030 
02031 /**
02032   * @brief  Disable clearing the output channel on an external event.
02033   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02034   * or not a timer instance can clear the OCxREF signal on an external event.
02035   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
02036   * or not a channel is supported by the a timer instance.
02037   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_ConfigOutput\n
02038   *         CCMR1        OC2CE          LL_TIM_OC_ConfigOutput\n
02039   *         CCMR2        OC3CE          LL_TIM_OC_ConfigOutput\n
02040   *         CCMR2        OC4CE          LL_TIM_OC_ConfigOutput\n
02041   *         CCMR3        OC5CE          LL_TIM_OC_ConfigOutput\n
02042   *         CCMR3        OC6CE          LL_TIM_OC_ConfigOutput\n
02043   * @param  TIMx Timer instance
02044   * @param  Channel This parameter can be one of the following values:
02045   *         @arg @ref LL_TIM_CHANNEL_CH1
02046   *         @arg @ref LL_TIM_CHANNEL_CH2
02047   *         @arg @ref LL_TIM_CHANNEL_CH3
02048   *         @arg @ref LL_TIM_CHANNEL_CH4
02049   *         @arg @ref LL_TIM_CHANNEL_CH5
02050   *         @arg @ref LL_TIM_CHANNEL_CH6
02051   * @retval None
02052   */
02053 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx, uint32_t Channel)
02054 {
02055   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02056   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02057   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02058 }
02059 
02060 /**
02061   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
02062   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02063   * dead-time insertion feature is supported by a timer instance.
02064   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
02065   * @param  TIMx Timer instance
02066   * @param  DeadTime Between 0 and 255
02067   * @retval None
02068   */
02069 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx, uint32_t DeadTime)
02070 {
02071   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
02072 }
02073 
02074 /**
02075   * @brief  Set compare value for output channel 1 (TIMx_CCR1)
02076   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02077   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
02078   * whether or not a timer instance supports a 32 bits counter.
02079   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02080   * output channel 1 is supported by a timer instance.
02081   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
02082   * @param  TIMx Timer instance
02083   * @param  CompareValue Between 0 and 65535
02084   * @retval None
02085   */
02086 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx, uint32_t CompareValue)
02087 {
02088   WRITE_REG(TIMx->CCR1, CompareValue);
02089 }
02090 
02091 /**
02092   * @brief  Set compare value for output channel 2 (TIMx_CCR2)
02093   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02094   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
02095   * whether or not a timer instance supports a 32 bits counter.
02096   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02097   * output channel 2 is supported by a timer instance.
02098   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
02099   * @param  TIMx Timer instance
02100   * @param  CompareValue Between 0 and 65535
02101   * @retval None
02102   */
02103 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx, uint32_t CompareValue)
02104 {
02105   WRITE_REG(TIMx->CCR2, CompareValue);
02106 }
02107 
02108 /**
02109   * @brief  Set compare value for output channel 3 (TIMx_CCR3)
02110   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02111   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
02112   * whether or not a timer instance supports a 32 bits counter.
02113   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02114   * output channel is supported by a timer instance.
02115   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
02116   * @param  TIMx Timer instance
02117   * @param  CompareValue Between 0 and 65535
02118   * @retval None
02119   */
02120 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx, uint32_t CompareValue)
02121 {
02122   WRITE_REG(TIMx->CCR3, CompareValue);
02123 }
02124 
02125 /**
02126   * @brief  Set compare value for output channel 4 (TIMx_CCR4)
02127   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02128   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
02129   * whether or not a timer instance supports a 32 bits counter.
02130   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02131   * output channel 4 is supported by a timer instance.
02132   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
02133   * @param  TIMx Timer instance
02134   * @param  CompareValue Between 0 and 65535
02135   * @retval None
02136   */
02137 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx, uint32_t CompareValue)
02138 {
02139   WRITE_REG(TIMx->CCR4, CompareValue);
02140 }
02141 
02142 /**
02143   * @brief  Set compare value for output channel 5 (TIMx_CCR5)
02144   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02145   * output channel 5 is supported by a timer instance.
02146   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
02147   * @param  TIMx Timer instance
02148   * @param  CompareValue Between 0 and 65535
02149   * @retval None
02150   */
02151 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx, uint32_t CompareValue)
02152 {
02153   WRITE_REG(TIMx->CCR5, CompareValue);
02154 }
02155 
02156 /**
02157   * @brief  Set compare value for output channel 6 (TIMx_CCR6)
02158   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02159   * output channel 6 is supported by a timer instance.
02160   * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
02161   * @param  TIMx Timer instance
02162   * @param  CompareValue Between 0 and 65535
02163   * @retval None
02164   */
02165 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx, uint32_t CompareValue)
02166 {
02167   WRITE_REG(TIMx->CCR6, CompareValue);
02168 }
02169 
02170 /**
02171   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1
02172   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02173   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
02174   * whether or not a timer instance supports a 32 bits counter.
02175   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02176   * output channel 1 is supported by a timer instance.
02177   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
02178   * @param  TIMx Timer instance
02179   * @retval CompareValue
02180   */
02181 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)
02182 {
02183   return (uint32_t)(READ_REG(TIMx->CCR1));
02184 }
02185 
02186 /**
02187   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2
02188   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02189   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
02190   * whether or not a timer instance supports a 32 bits counter.
02191   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02192   * output channel 2 is supported by a timer instance.
02193   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
02194   * @param  TIMx Timer instance
02195   * @retval CompareValue
02196   */
02197 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)
02198 {
02199   return (uint32_t)(READ_REG(TIMx->CCR2));
02200 }
02201 
02202 /**
02203   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3
02204   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02205   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
02206   * whether or not a timer instance supports a 32 bits counter.
02207   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02208   * output channel 3 is supported by a timer instance.
02209   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
02210   * @param  TIMx Timer instance
02211   * @retval CompareValue
02212   */
02213 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)
02214 {
02215   return (uint32_t)(READ_REG(TIMx->CCR3));
02216 }
02217 
02218 /**
02219   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4
02220   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02221   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
02222   * whether or not a timer instance supports a 32 bits counter.
02223   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02224   * output channel 4 is supported by a timer instance.
02225   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
02226   * @param  TIMx Timer instance
02227   * @retval CompareValue
02228   */
02229 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)
02230 {
02231   return (uint32_t)(READ_REG(TIMx->CCR4));
02232 }
02233 
02234 /**
02235   * @brief  Get compare value (TIMx_CCR5) set for  output channel 5
02236   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02237   * output channel 5 is supported by a timer instance.
02238   * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
02239   * @param  TIMx Timer instance
02240   * @retval CompareValue
02241   */
02242 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef * TIMx)
02243 {
02244   return (uint32_t)(READ_REG(TIMx->CCR5));
02245 }
02246 
02247 /**
02248   * @brief  Get compare value (TIMx_CCR6) set for  output channel 6
02249   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02250   * output channel 6 is supported by a timer instance.
02251   * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
02252   * @param  TIMx Timer instance
02253   * @retval CompareValue
02254   */
02255 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef * TIMx)
02256 {
02257   return (uint32_t)(READ_REG(TIMx->CCR6));
02258 }
02259 
02260 /**
02261   * @brief  Select on which reference signal the OC5REF is combined to.
02262   * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check 
02263   * whether or not a timer instance supports the combined 3-phase PWM mode.
02264   * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
02265   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
02266   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels\n
02267   * @param  TIMx Timer instance
02268   * @param  GroupCH5 This parameter can be one of the following values:
02269   *         @arg @ref LL_TIM_GROUPCH5_NONE
02270   *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
02271   *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
02272   *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
02273   * @retval None
02274   */
02275 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx, uint32_t GroupCH5)
02276 {
02277   MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
02278 }
02279 
02280 /**
02281   * @}
02282   */
02283 
02284 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
02285   * @{
02286   */
02287 /**
02288   * @brief  Configure input channel.
02289   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
02290   * or not a channel is supported by the a timer instance.
02291   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
02292   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
02293   *         CCMR1        IC1F          LL_TIM_IC_Config\n
02294   *         CCMR1        CC2S          LL_TIM_IC_Config\n
02295   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
02296   *         CCMR1        IC2F          LL_TIM_IC_Config\n
02297   *         CCMR2        CC3S          LL_TIM_IC_Config\n
02298   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
02299   *         CCMR2        IC3F          LL_TIM_IC_Config\n
02300   *         CCMR2        CC4S          LL_TIM_IC_Config\n
02301   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
02302   *         CCMR2        IC4F          LL_TIM_IC_Config\n
02303   *         CCER         CC1P          LL_TIM_IC_Config\n
02304   *         CCER         CC1NP         LL_TIM_IC_Config\n
02305   *         CCER         CC2P          LL_TIM_IC_Config\n
02306   *         CCER         CC2NP         LL_TIM_IC_Config\n
02307   *         CCER         CC3P          LL_TIM_IC_Config\n
02308   *         CCER         CC3NP         LL_TIM_IC_Config\n
02309   *         CCER         CC4P          LL_TIM_IC_Config\n
02310   *         CCER         CC4NP         LL_TIM_IC_Config\n
02311   * @param  TIMx Timer instance
02312   * @param  Channel This parameter can be one of the following values:
02313   *         @arg @ref LL_TIM_CHANNEL_CH1
02314   *         @arg @ref LL_TIM_CHANNEL_CH2
02315   *         @arg @ref LL_TIM_CHANNEL_CH3
02316   *         @arg @ref LL_TIM_CHANNEL_CH4
02317   * @param  Configuration This parameter must be a combination of all the following values:
02318   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
02319   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
02320   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
02321   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
02322   * @retval None
02323   */
02324 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Configuration)
02325 {
02326   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02327   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02328   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),  ((Configuration >> 16) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))  << SHIFT_TAB_ICxx[iChannel]);
02329   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),  (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
02330 }
02331 
02332 /**
02333   * @brief  Set the active input
02334   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
02335   * or not a channel is supported by the a timer instance.
02336   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
02337   *         CCMR1        CC2S          LL_TIM_IC_Config\n
02338   *         CCMR2        CC3S          LL_TIM_IC_Config\n
02339   *         CCMR2        CC4S          LL_TIM_IC_Config\n
02340   * @param  TIMx Timer instance
02341   * @param  Channel This parameter can be one of the following values:
02342   *         @arg @ref LL_TIM_CHANNEL_CH1
02343   *         @arg @ref LL_TIM_CHANNEL_CH2
02344   *         @arg @ref LL_TIM_CHANNEL_CH3
02345   *         @arg @ref LL_TIM_CHANNEL_CH4
02346   * @param  ICActiveInput This parameter can be one of the following values:
02347   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02348   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02349   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02350   * @retval None
02351   */
02352 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICActiveInput)
02353 {
02354   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02355   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02356   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),  (ICActiveInput >> 16) << SHIFT_TAB_ICxx[iChannel]);
02357 }
02358 
02359 /**
02360   * @brief  Get the current active input
02361   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
02362   * or not a channel is supported by the a timer instance.
02363   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
02364   *         CCMR1        CC2S          LL_TIM_IC_Config\n
02365   *         CCMR2        CC3S          LL_TIM_IC_Config\n
02366   *         CCMR2        CC4S          LL_TIM_IC_Config\n
02367   * @param  TIMx Timer instance
02368   * @param  Channel This parameter can be one of the following values:
02369   *         @arg @ref LL_TIM_CHANNEL_CH1
02370   *         @arg @ref LL_TIM_CHANNEL_CH2
02371   *         @arg @ref LL_TIM_CHANNEL_CH3
02372   *         @arg @ref LL_TIM_CHANNEL_CH4
02373   * @retval Returned value can be one of the following values:
02374   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02375   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02376   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02377   */
02378 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx, uint32_t Channel)
02379 {
02380   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02381   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));  
02382   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16);
02383 }
02384 
02385 /**
02386   * @brief  Set the prescaler of input channel
02387   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
02388   * or not a channel is supported by the a timer instance.
02389   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_Config\n
02390   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
02391   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
02392   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
02393   * @param  TIMx Timer instance
02394   * @param  Channel This parameter can be one of the following values:
02395   *         @arg @ref LL_TIM_CHANNEL_CH1
02396   *         @arg @ref LL_TIM_CHANNEL_CH2
02397   *         @arg @ref LL_TIM_CHANNEL_CH3
02398   *         @arg @ref LL_TIM_CHANNEL_CH4
02399   * @param  ICPrescaler This parameter can be one of the following values:
02400   *         @arg @ref LL_TIM_ICPSC_DIV1
02401   *         @arg @ref LL_TIM_ICPSC_DIV2
02402   *         @arg @ref LL_TIM_ICPSC_DIV4
02403   *         @arg @ref LL_TIM_ICPSC_DIV8
02404   * @retval None
02405   */
02406 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICPrescaler)
02407 {
02408   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02409   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02410   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]),  (ICPrescaler >> 16) << SHIFT_TAB_ICxx[iChannel]);
02411 }
02412 
02413 /**
02414   * @brief  Get the current prescaler value acting on an  input channel
02415   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
02416   * or not a channel is supported by the a timer instance.
02417   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_Config\n
02418   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
02419   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
02420   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
02421   * @param  TIMx Timer instance
02422   * @param  Channel This parameter can be one of the following values:
02423   *         @arg @ref LL_TIM_CHANNEL_CH1
02424   *         @arg @ref LL_TIM_CHANNEL_CH2
02425   *         @arg @ref LL_TIM_CHANNEL_CH3
02426   *         @arg @ref LL_TIM_CHANNEL_CH4
02427   * @retval Returned value can be one of the following values:
02428   *         @arg @ref LL_TIM_ICPSC_DIV1
02429   *         @arg @ref LL_TIM_ICPSC_DIV2
02430   *         @arg @ref LL_TIM_ICPSC_DIV4
02431   *         @arg @ref LL_TIM_ICPSC_DIV8
02432   */
02433 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx, uint32_t Channel)
02434 {
02435   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02436   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));  
02437   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16);
02438 }
02439 
02440 /**
02441   * @brief  Set the input filter duration
02442   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
02443   * or not a channel is supported by the a timer instance.
02444   * @rmtoll CCMR1        IC1F          LL_TIM_IC_Config\n
02445   *         CCMR1        IC2F          LL_TIM_IC_Config\n
02446   *         CCMR2        IC3F          LL_TIM_IC_Config\n
02447   *         CCMR2        IC4F          LL_TIM_IC_Config\n
02448   * @param  TIMx Timer instance
02449   * @param  Channel This parameter can be one of the following values:
02450   *         @arg @ref LL_TIM_CHANNEL_CH1
02451   *         @arg @ref LL_TIM_CHANNEL_CH2
02452   *         @arg @ref LL_TIM_CHANNEL_CH3
02453   *         @arg @ref LL_TIM_CHANNEL_CH4
02454   * @param  ICFilter This parameter can be one of the following values:
02455   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
02456   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
02457   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
02458   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
02459   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
02460   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
02461   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
02462   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
02463   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
02464   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
02465   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
02466   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
02467   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
02468   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
02469   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
02470   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
02471   * @retval None
02472   */
02473 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICFilter)
02474 {
02475   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02476   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02477   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]),  (ICFilter >> 16) << SHIFT_TAB_ICxx[iChannel]);
02478 }
02479 
02480 /**
02481   * @brief  Get the input filter duration
02482   * @rmtoll CCMR1        IC1F          LL_TIM_IC_Config\n
02483   *         CCMR1        IC2F          LL_TIM_IC_Config\n
02484   *         CCMR2        IC3F          LL_TIM_IC_Config\n
02485   *         CCMR2        IC4F          LL_TIM_IC_Config\n
02486   * @param  TIMx Timer instance
02487   * @param  Channel This parameter can be one of the following values:
02488   *         @arg @ref LL_TIM_CHANNEL_CH1
02489   *         @arg @ref LL_TIM_CHANNEL_CH2
02490   *         @arg @ref LL_TIM_CHANNEL_CH3
02491   *         @arg @ref LL_TIM_CHANNEL_CH4
02492   * @retval Returned value can be one of the following values:
02493   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
02494   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
02495   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
02496   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
02497   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
02498   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
02499   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
02500   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
02501   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
02502   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
02503   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
02504   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
02505   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
02506   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
02507   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
02508   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
02509   */
02510 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx, uint32_t Channel)
02511 {
02512   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02513   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));  
02514   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16 );
02515 }
02516 
02517 /**
02518   * @brief  Set the input channel polarity
02519   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
02520   * or not a channel is supported by the a timer instance.
02521   * @rmtoll CCER         CC1P          LL_TIM_IC_Config\n
02522   *         CCER         CC1NP         LL_TIM_IC_Config\n
02523   *         CCER         CC2P          LL_TIM_IC_Config\n
02524   *         CCER         CC2NP         LL_TIM_IC_Config\n
02525   *         CCER         CC3P          LL_TIM_IC_Config\n
02526   *         CCER         CC3NP         LL_TIM_IC_Config\n
02527   *         CCER         CC4P          LL_TIM_IC_Config\n
02528   *         CCER         CC4NP         LL_TIM_IC_Config\n
02529   * @param  TIMx Timer instance
02530   * @param  Channel This parameter can be one of the following values:
02531   *         @arg @ref LL_TIM_CHANNEL_CH1
02532   *         @arg @ref LL_TIM_CHANNEL_CH2
02533   *         @arg @ref LL_TIM_CHANNEL_CH3
02534   *         @arg @ref LL_TIM_CHANNEL_CH4
02535   * @param  ICPolarity This parameter can be one of the following values:
02536   *         @arg @ref LL_TIM_IC_POLARITY_RISING
02537   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
02538   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
02539   * @retval None
02540   */
02541 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICPolarity)
02542 {
02543   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02544   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),  ICPolarity << SHIFT_TAB_CCxP[iChannel]);
02545 }
02546 
02547 /**
02548   * @brief  Get the current input channel polarity
02549   * @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
02550   * or not a channel is supported by the a timer instance.
02551   * @rmtoll CCER         CC1P          LL_TIM_IC_Config\n
02552   *         CCER         CC1NP         LL_TIM_IC_Config\n
02553   *         CCER         CC2P          LL_TIM_IC_Config\n
02554   *         CCER         CC2NP         LL_TIM_IC_Config\n
02555   *         CCER         CC3P          LL_TIM_IC_Config\n
02556   *         CCER         CC3NP         LL_TIM_IC_Config\n
02557   *         CCER         CC4P          LL_TIM_IC_Config\n
02558   *         CCER         CC4NP         LL_TIM_IC_Config\n
02559   * @param  TIMx Timer instance
02560   * @param  Channel This parameter can be one of the following values:
02561   *         @arg @ref LL_TIM_CHANNEL_CH1
02562   *         @arg @ref LL_TIM_CHANNEL_CH2
02563   *         @arg @ref LL_TIM_CHANNEL_CH3
02564   *         @arg @ref LL_TIM_CHANNEL_CH4
02565   * @retval Returned value can be one of the following values:
02566   *         @arg @ref LL_TIM_IC_POLARITY_RISING
02567   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
02568   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
02569   */
02570 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx, uint32_t Channel)
02571 {
02572   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02573   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
02574 }
02575 
02576 /**
02577   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
02578   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02579   * a timer instance provides an XOR input.
02580   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
02581   * @param  TIMx Timer instance
02582   * @retval None
02583   */
02584 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)
02585 {
02586   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
02587 }
02588 
02589 /**
02590   * @brief  Connect the TIMx_CH1 pin to TI1 input.
02591   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02592   * a timer instance provides an XOR input.
02593   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
02594   * @param  TIMx Timer instance
02595   * @retval None
02596   */
02597 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)
02598 {
02599   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
02600 }
02601 
02602 /**
02603   * @brief  Get captured value for input channel 1.
02604   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02605   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
02606   * whether or not a timer instance supports a 32 bits counter.
02607   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02608   * input channel 1 is supported by a timer instance.
02609   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
02610   * @param  TIMx Timer instance
02611   * @retval CapturedValue
02612   */
02613 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)
02614 {
02615   return (uint32_t)(READ_REG(TIMx->CCR1));
02616 }
02617 
02618 /**
02619   * @brief  Get captured value for input channel 2.
02620   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02621   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
02622   * whether or not a timer instance supports a 32 bits counter.
02623   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02624   * input channel 2 is supported by a timer instance.
02625   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
02626   * @param  TIMx Timer instance
02627   * @retval CapturedValue
02628   */
02629 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)
02630 {
02631   return (uint32_t)(READ_REG(TIMx->CCR2));
02632 }
02633 
02634 /**
02635   * @brief  Get captured value for input channel 3.
02636   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02637   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
02638   * whether or not a timer instance supports a 32 bits counter.
02639   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02640   * input channel 3 is supported by a timer instance.
02641   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
02642   * @param  TIMx Timer instance
02643   * @retval CapturedValue
02644   */
02645 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)
02646 {
02647   return (uint32_t)(READ_REG(TIMx->CCR3));
02648 }
02649 
02650 /**
02651   * @brief  Get captured value for input channel 4.
02652   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02653   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 
02654   * whether or not a timer instance supports a 32 bits counter.
02655   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02656   * input channel 4 is supported by a timer instance.
02657   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
02658   * @param  TIMx Timer instance
02659   * @retval CapturedValue
02660   */
02661 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)
02662 {
02663   return (uint32_t)(READ_REG(TIMx->CCR4));
02664 }
02665 
02666 /**
02667   * @}
02668   */
02669 
02670 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
02671   * @{
02672   */
02673 /**
02674   * @brief  Set the clock source of the counter clock.
02675   * @ when selected clock source is external clock mode 1, the timer input the external clock is applied is selected by calling the LL_TIM_SetTriggerInput() function. This timer input must be configured by calling the LL_TIM_IC_Config() function.
02676   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check 
02677   * whether or not a timer instance supports external clock mode1.
02678   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 
02679   * whether or not a timer instance supports external clock mode2.
02680   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
02681   *         SMCR         ECE           LL_TIM_SetClockSource\n
02682   * @param  TIMx Timer instance
02683   * @param  ClockSource This parameter can be one of the following values:
02684   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
02685   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
02686   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
02687   * @retval None
02688   */
02689 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef * TIMx, uint32_t ClockSource)
02690 {
02691   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
02692 }
02693 
02694 /**
02695   * @brief  Set the encoder interface mode.
02696   * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check 
02697   * whether or not a timer instance supports the encoder mode.
02698   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
02699   * @param  TIMx Timer instance
02700   * @param  EncoderMode This parameter can be one of the following values:
02701   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
02702   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
02703   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
02704   * @retval None
02705   */
02706 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx, uint32_t EncoderMode)
02707 {
02708   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
02709 }
02710 
02711 /**
02712   * @}
02713   */
02714 
02715 /** @defgroup TIM_LL_EF_Timer_Synchronization timer synchronisation configuration
02716   * @{
02717   */
02718 /**
02719   * @brief  Set the trigger output (TRGO) used for timer synchronization .
02720   * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check 
02721   * whether or not a timer instance can operate as a master timer.
02722   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
02723   * @param  TIMx Timer instance
02724   * @param  TimerSynchronization This parameter can be one of the following values:
02725   *         @arg @ref LL_TIM_TRGO_RESET
02726   *         @arg @ref LL_TIM_TRGO_ENABLE
02727   *         @arg @ref LL_TIM_TRGO_UPDATE
02728   *         @arg @ref LL_TIM_TRGO_CC1IF
02729   *         @arg @ref LL_TIM_TRGO_OC1REF
02730   *         @arg @ref LL_TIM_TRGO_OC2REF
02731   *         @arg @ref LL_TIM_TRGO_OC3REF
02732   *         @arg @ref LL_TIM_TRGO_OC4REF
02733   * @retval None
02734   */
02735 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx, uint32_t TimerSynchronization)
02736 {
02737   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
02738 }
02739 
02740 /**
02741   * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
02742   * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check 
02743   * whether or not a timer instance can be used for ADC synchronization.
02744   * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
02745   * @param  TIMx Timer Instance
02746   * @param  ADCSynchronization This parameter can be one of the following values:
02747   *         @arg @ref LL_TIM_TRGO2_RESET
02748   *         @arg @ref LL_TIM_TRGO2_ENABLE
02749   *         @arg @ref LL_TIM_TRGO2_UPDATE
02750   *         @arg @ref LL_TIM_TRGO2_CC1F
02751   *         @arg @ref LL_TIM_TRGO2_OC1
02752   *         @arg @ref LL_TIM_TRGO2_OC2
02753   *         @arg @ref LL_TIM_TRGO2_OC3
02754   *         @arg @ref LL_TIM_TRGO2_OC4
02755   *         @arg @ref LL_TIM_TRGO2_OC5
02756   *         @arg @ref LL_TIM_TRGO2_OC6
02757   *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
02758   *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
02759   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
02760   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
02761   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
02762   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
02763   * @retval None
02764   */
02765 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx, uint32_t ADCSynchronization)
02766 {
02767   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
02768 }
02769 
02770 /**
02771   * @brief  Set the synchronization mode of a slave timer.
02772   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 
02773   * a timer instance can operate as a slave timer.
02774   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
02775   * @param  TIMx Timer instance
02776   * @param  SlaveMode This parameter can be one of the following values:
02777   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
02778   *         @arg @ref LL_TIM_SLAVEMODE_RESET
02779   *         @arg @ref LL_TIM_SLAVEMODE_GATED
02780   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
02781   *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER (not supported by STM32F373xC and STM32F378xx devices)
02782   * @retval None
02783   */
02784 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx, uint32_t SlaveMode)
02785 {
02786   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
02787 }
02788 
02789 /**
02790   * @brief  Set the selects the trigger input to be used to synchronize the counter.
02791   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 
02792   * a timer instance can operate as a slave timer.
02793   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
02794   * @param  TIMx Timer instance
02795   * @param  TriggerInput This parameter can be one of the following values:
02796   *         @arg @ref LL_TIM_TS_ITR0
02797   *         @arg @ref LL_TIM_TS_ITR1
02798   *         @arg @ref LL_TIM_TS_ITR2
02799   *         @arg @ref LL_TIM_TS_ITR3
02800   *         @arg @ref LL_TIM_TS_TI1F_ED
02801   *         @arg @ref LL_TIM_TS_TI1FP1
02802   *         @arg @ref LL_TIM_TS_TI2FP2
02803   *         @arg @ref LL_TIM_TS_ETRF
02804   * @retval None
02805   */
02806 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx, uint32_t TriggerInput)
02807 {
02808   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
02809 }
02810 
02811 /**
02812   * @brief  Enable the Master/Slave mode.
02813   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 
02814   * a timer instance can operate as a slave timer.
02815   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
02816   * @param  TIMx Timer instance
02817   * @retval None
02818   */
02819 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)
02820 {
02821   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
02822 }
02823 
02824 /**
02825   * @brief  Disable the Master/Slave mode.
02826   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 
02827   * a timer instance can operate as a slave timer.
02828   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
02829   * @param  TIMx Timer instance
02830   * @retval None
02831   */
02832 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)
02833 {
02834   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
02835 }
02836 
02837 /**
02838   * @brief  Configure the external trigger (ETR) input.
02839   * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not 
02840   * a timer instance provides an external trigger input.
02841   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
02842   *         SMCR         ETPS          LL_TIM_ConfigETR\n
02843   *         SMCR         ETF           LL_TIM_ConfigETR
02844   * @param  TIMx Timer instance
02845   * @param  ETRPolarity This parameter can be one of the following values:
02846   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
02847   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
02848   * @param  ETRPrescaler This parameter can be one of the following values:
02849   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
02850   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
02851   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
02852   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
02853   * @param  ETRFilter This parameter can be one of the following values:
02854   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
02855   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
02856   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
02857   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
02858   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
02859   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
02860   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
02861   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
02862   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
02863   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
02864   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
02865   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
02866   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
02867   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
02868   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
02869   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
02870   * @retval None
02871   */
02872 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef * TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
02873 {
02874   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
02875 }
02876 
02877 /**
02878   * @brief  Select the external trigger (ETR) input source.
02879   * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
02880   * not a timer instance supports ETR source selection.
02881   * @rmtoll OR2          ETRSEL        LL_TIM_SetETRSource
02882   * @param  TIMx Timer instance
02883   * @param  ETRSource This parameter can be one of the following values:
02884   *         @arg @ref LL_TIM_ETRSOURCE_LEGACY
02885   *         @arg @ref LL_TIM_ETRSOURCE_COMP1
02886   *         @arg @ref LL_TIM_ETRSOURCE_COMP2
02887   * @retval None
02888   */
02889 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef * TIMx, uint32_t ETRSource)
02890 {
02891 
02892   MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
02893 }
02894 
02895 /**
02896   * @}
02897   */
02898 
02899 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
02900   * @{
02901   */
02902 /**
02903   * @brief  Enable the break function.
02904   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 
02905   * a timer instance provides a break input.
02906   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
02907   * @param  TIMx Timer instance
02908   * @retval None
02909   */
02910 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef * TIMx)
02911 {
02912   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
02913 }
02914 
02915 /**
02916   * @brief  Disable the break function.
02917   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
02918   * @param  TIMx Timer instance
02919   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 
02920   * a timer instance provides a break input.
02921   * @retval None
02922   */
02923 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef * TIMx)
02924 {
02925   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
02926 }
02927 
02928 /**
02929   * @brief  Configure the break input.
02930   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 
02931   * a timer instance provides a break input.
02932   * @param  TIMx Timer instance
02933   * @param  BreakPolarity This parameter can be one of the following values:
02934   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
02935   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
02936   * @param  BreakFilter This parameter can be one of the following values:
02937   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
02938   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
02939   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
02940   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
02941   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
02942   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
02943   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
02944   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
02945   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
02946   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
02947   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
02948   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
02949   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
02950   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
02951   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
02952   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
02953   * @retval None
02954   */
02955 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef * TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
02956 {
02957   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
02958 }
02959 
02960 /**
02961   * @brief  Enable the break 2 function.
02962   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 
02963   * a timer instance provides a second break input.
02964   * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
02965   * @param  TIMx Timer instance
02966   * @retval None
02967   */
02968 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)
02969 {
02970   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
02971 }
02972 
02973 /**
02974   * @brief  Disable the break  2 function.
02975   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 
02976   * a timer instance provides a second break input.
02977   * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
02978   * @param  TIMx Timer instance
02979   * @retval None
02980   */
02981 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)
02982 {
02983   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
02984 }
02985 
02986 /**
02987   * @brief  Configure the break 2 input.
02988   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 
02989   * a timer instance provides a second break input.
02990   * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
02991   *         BDTR         BK2F          LL_TIM_ConfigBRK2
02992   * @param  TIMx Timer instance
02993   * @param  Break2Polarity This parameter can be one of the following values:
02994   *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
02995   *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
02996   * @param  Break2Filter This parameter can be one of the following values:
02997   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
02998   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
02999   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
03000   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
03001   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
03002   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
03003   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
03004   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
03005   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
03006   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
03007   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
03008   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
03009   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
03010   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
03011   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
03012   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
03013   * @retval None
03014   */
03015 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
03016 {
03017   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
03018 }
03019 
03020 /**
03021   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
03022   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 
03023   * a timer instance provides a break input.
03024   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
03025   *         BDTR         OSSR          LL_TIM_SetOffStates
03026   * @param  TIMx Timer instance
03027   * @param  OffStateIdle This parameter can be one of the following values:
03028   *         @arg @ref LL_TIM_OSSI_DISABLE
03029   *         @arg @ref LL_TIM_OSSI_ENABLE
03030   * @param  OffStateRun This parameter can be one of the following values:
03031   *         @arg @ref LL_TIM_OSSR_DISABLE
03032   *         @arg @ref LL_TIM_OSSR_ENABLE
03033   * @retval None
03034   */
03035 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef * TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
03036 {
03037   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
03038 }
03039 
03040 /**
03041   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
03042   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 
03043   * a timer instance provides a break input.
03044   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
03045   * @param  TIMx Timer instance
03046   * @retval None
03047   */
03048 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)
03049 {
03050   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03051 }
03052 
03053 /**
03054   * @brief  Disable automatic output (MOE can be set only by software).
03055   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 
03056   * a timer instance provides a break input.
03057   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
03058   * @param  TIMx Timer instance
03059   * @retval None
03060   */
03061 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)
03062 {
03063   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03064 }
03065 
03066 /**
03067   * @brief  Indicate whether automatic output is enabled.
03068   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 
03069   * a timer instance provides a break input.
03070   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
03071   * @param  TIMx Timer instance
03072   * @retval State of bit (1 or 0).
03073   */
03074 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx)
03075 {
03076   return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
03077 }
03078 
03079 /**
03080   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
03081   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03082   * software and is reset in case of break or break2 event
03083   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 
03084   * a timer instance provides a break input.
03085   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
03086   * @param  TIMx Timer instance
03087   * @retval None
03088   */
03089 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)
03090 {
03091   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03092 }
03093 
03094 /**
03095   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
03096   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03097   * software and is reset in case of break or break2 event.
03098   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 
03099   * a timer instance provides a break input.
03100   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
03101   * @param  TIMx Timer instance
03102   * @retval None
03103   */
03104 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)
03105 {
03106   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03107 }
03108 
03109 /**
03110   * @brief  Indicates whether outputs are enabled.
03111   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 
03112   * a timer instance provides a break input.
03113   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
03114   * @param  TIMx Timer instance
03115   * @retval State of bit (1 or 0).
03116   */
03117 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx)
03118 {
03119   return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
03120 }
03121 
03122 /**
03123   * @brief  Enable the signals connected to the designated timer break input.
03124   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03125   * or not a timer instance allows for break input selection.
03126   * @rmtoll OR2          BKINE         LL_TIM_EnableBreakInputSource\n
03127   *         OR2          BKCMP1E       LL_TIM_EnableBreakInputSource\n
03128   *         OR2          BKCMP2E       LL_TIM_EnableBreakInputSource\n
03129   *         OR2          BKDFBK0E      LL_TIM_EnableBreakInputSource\n
03130   *         OR3          BKINE         LL_TIM_EnableBreakInputSource\n
03131   *         OR3          BKCMP1E       LL_TIM_EnableBreakInputSource\n
03132   *         OR3          BKCMP2E       LL_TIM_EnableBreakInputSource\n
03133   *         OR3          BKDFBK0E      LL_TIM_EnableBreakInputSource
03134   * @param  TIMx Timer instance
03135   * @param  BreakInput This parameter can be one of the following values:
03136   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03137   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03138   * @param  Source This parameter can be one of the following values:
03139   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03140   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03141   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03142   *         @arg @ref LL_TIM_BKIN_SOURCE_DFBK
03143   * @retval None
03144   */
03145 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source)
03146 {
03147   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput));
03148   SET_BIT(*pReg , Source); 
03149 }
03150 
03151 /**
03152   * @brief  Disable the signals connected to the designated timer break input.
03153   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03154   * or not a timer instance allows for break input selection.
03155   * @rmtoll OR2          BKINE         LL_TIM_DisableBreakInputSource\n
03156   *         OR2          BKCMP1E       LL_TIM_DisableBreakInputSource\n
03157   *         OR2          BKCMP2E       LL_TIM_DisableBreakInputSource\n
03158   *         OR2          BKDFBK0E      LL_TIM_DisableBreakInputSource\n
03159   *         OR3          BKINE         LL_TIM_DisableBreakInputSource\n
03160   *         OR3          BKCMP1E       LL_TIM_DisableBreakInputSource\n
03161   *         OR3          BKCMP2E       LL_TIM_DisableBreakInputSource\n
03162   *         OR3          BKDFBK0E      LL_TIM_DisableBreakInputSource
03163   * @param  TIMx Timer instance
03164   * @param  BreakInput This parameter can be one of the following values:
03165   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03166   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03167   * @param  Source This parameter can be one of the following values:
03168   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03169   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03170   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03171   *         @arg @ref LL_TIM_BKIN_SOURCE_DFBK
03172   * @retval None
03173   */
03174 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source)
03175 {
03176   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput));
03177   CLEAR_BIT(*pReg, Source); 
03178 }
03179 
03180 /**
03181   * @brief  Set the polarity of the break signal for the timer break input.
03182   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03183   * or not a timer instance allows for break input selection.
03184   * @rmtoll OR2          BKINE         LL_TIM_SetBreakInputSourcePolarity\n
03185   *         OR2          BKCMP1E       LL_TIM_SetBreakInputSourcePolarity\n
03186   *         OR2          BKCMP2E       LL_TIM_SetBreakInputSourcePolarity\n
03187   *         OR2          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
03188   *         OR3          BKINE         LL_TIM_SetBreakInputSourcePolarity\n
03189   *         OR3          BKCMP1E       LL_TIM_SetBreakInputSourcePolarity\n
03190   *         OR3          BKCMP2E       LL_TIM_SetBreakInputSourcePolarity\n
03191   *         OR3          BKINP         LL_TIM_SetBreakInputSourcePolarity
03192   * @param  TIMx Timer instance
03193   * @param  BreakInput This parameter can be one of the following values:
03194   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03195   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03196   * @param  Source This parameter can be one of the following values:
03197   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03198   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03199   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03200   * @param  Polarity This parameter can be one of the following values:
03201   *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
03202   *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
03203   * @retval None
03204   */
03205 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
03206 {
03207   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput));
03208   MODIFY_REG(*pReg, (TIMx_OR2_BKINP << (POSITION_VAL(Source))) , (Polarity << (POSITION_VAL(Source))));
03209 }
03210 
03211 /**
03212   * @}
03213   */
03214 
03215 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burs mode configuration
03216   * @{
03217   */
03218 /**
03219   * @brief  Configures the timer DMA burst feature.
03220   * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
03221   * not a timer instance supports the DMA burst mode.
03222   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
03223   *         DCR          DBA           LL_TIM_ConfigDMABurst
03224   * @param  TIMx Timer instance
03225   * @param  DMABurstBaseAddress This parameter can be one of the following values:
03226   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
03227   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
03228   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
03229   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
03230   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
03231   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
03232   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
03233   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
03234   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
03235   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
03236   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
03237   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
03238   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
03239   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
03240   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
03241   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
03242   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
03243   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
03244   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
03245   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
03246   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
03247   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
03248   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
03249   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
03250   * @param  DMABurstLength This parameter can be one of the following values:
03251   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
03252   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
03253   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
03254   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
03255   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
03256   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
03257   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
03258   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
03259   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
03260   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
03261   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
03262   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
03263   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
03264   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
03265   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
03266   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
03267   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
03268   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
03269   * @retval None
03270   */
03271 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
03272 {
03273   MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
03274 }
03275 
03276 /**
03277   * @}
03278   */
03279 
03280 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
03281   * @{
03282   */
03283 /**
03284   * @brief  Remap TIM inputs (input channel, internal/external triggers).
03285   * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
03286   * a some timer inputs can be remapped.
03287   * @rmtoll TIM1_OR1    ETR_ADC1_RMP      LL_TIM_SetRemap\n
03288   * @rmtoll TIM1_OR1    ETR_ADC3_RMP      LL_TIM_SetRemap\n
03289   * @rmtoll TIM1_OR1    TI1_RMP           LL_TIM_SetRemap\n
03290   * @rmtoll TIM8_OR1    ETR_ADC2_RMP      LL_TIM_SetRemap\n
03291   * @rmtoll TIM8_OR1    ETR_ADC3_RMP      LL_TIM_SetRemap\n
03292   * @rmtoll TIM8_OR1    TI1_RMP           LL_TIM_SetRemap\n
03293   * @rmtoll TIM2_OR1    ITR1_RMP          LL_TIM_SetRemap\n
03294   * @rmtoll TIM2_OR1    ETR1_RMP          LL_TIM_SetRemap\n
03295   * @rmtoll TIM2_OR1    TI4_RMP           LL_TIM_SetRemap\n
03296   * @rmtoll TIM3_OR1    TI1_RMP           LL_TIM_SetRemap\n
03297   * @rmtoll TIM15_OR1   TI1_RMP           LL_TIM_SetRemap\n
03298   * @rmtoll TIM15_OR1   ENCODER_MODE      LL_TIM_SetRemap\n
03299   * @rmtoll TIM16_OR1   TI1_RMP           LL_TIM_SetRemap\n
03300   * @rmtoll TIM17_OR1   TI1_RMP           LL_TIM_SetRemap
03301   * @param  TIMx: Timer instance 
03302   * @param  Remap: This parameter can be one of the following values:
03303   *
03304   *         TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
03305   *            ADC1_RMP can be one of the following values
03306   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
03307   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
03308   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
03309   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
03310   *            ADC3_RMP can be one of the following values
03311   *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC
03312   *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1
03313   *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2
03314   *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3
03315   *            TI1_RMP can be one of the following values
03316   *            @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
03317   *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
03318   *
03319   *         TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
03320   *            ITR1_RMP can be one of the following values
03321   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
03322   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
03323   *            ETR1_RMP can be one of the following values
03324   *            @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
03325   *            @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
03326   *            TI4_RMP can be one of the following values
03327   *            @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
03328   *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
03329   *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
03330   *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
03331   *
03332   *         TIM3: one of the following values
03333   *            @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
03334   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
03335   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
03336   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
03337   *
03338   *         TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
03339   *            ADC1_RMP can be one of the following values
03340   *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC
03341   *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1
03342   *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2
03343   *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3
03344   *            ADC3_RMP can be one of the following values
03345   *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC
03346   *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1
03347   *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2
03348   *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3
03349   *            TI1_RMP can be one of the following values
03350   *            @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
03351   *            @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
03352   *
03353   *         TIM15: any combination of TI1_RMP, ENCODER_MODE where
03354   *            TI1_RMP can be one of the following values
03355   *            @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
03356   *            @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
03357   *            ENCODER_MODE can be one of the following values
03358   *            @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
03359   *            @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2  
03360   *            @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
03361   *            @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
03362   *
03363   *         TIM16: one of the following values
03364   *            @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
03365   *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
03366   *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
03367   *            @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
03368   *
03369   *         TIM17: one of the following values
03370   *            @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
03371   *            @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
03372   *            @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
03373   *            @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
03374   * @retval None
03375   */
03376 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef * TIMx, uint32_t Remap)
03377 {
03378   MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
03379 }
03380 
03381 /**
03382   * @}
03383   */
03384 
03385 /** @defgroup TIM_LL_EF_FLAG_Management FLAG_Management
03386   * @{
03387   */
03388 /**
03389   * @brief  Clear the update interrupt flag (UIF).
03390   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
03391   * @param  TIMx Timer instance
03392   * @retval None
03393   */
03394 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)
03395 {
03396   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
03397 }
03398 
03399 /**
03400   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
03401   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
03402   * @param  TIMx Timer instance
03403   * @retval State of bit (1 or 0).
03404   */
03405 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)
03406 {
03407   return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
03408 }
03409 
03410 /**
03411   * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
03412   * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
03413   * @param  TIMx Timer instance
03414   * @retval None
03415   */
03416 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)
03417 {
03418   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
03419 }
03420 
03421 /**
03422   * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
03423   * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
03424   * @param  TIMx Timer instance
03425   * @retval State of bit (1 or 0).
03426   */
03427 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)
03428 {
03429   return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
03430 }
03431 
03432 /**
03433   * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
03434   * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
03435   * @param  TIMx Timer instance
03436   * @retval None
03437   */
03438 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)
03439 {
03440   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
03441 }
03442 
03443 /**
03444   * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
03445   * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
03446   * @param  TIMx Timer instance
03447   * @retval State of bit (1 or 0).
03448   */
03449 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)
03450 {
03451   return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
03452 }
03453 
03454 /**
03455   * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
03456   * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
03457   * @param  TIMx Timer instance
03458   * @retval None
03459   */
03460 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)
03461 {
03462   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
03463 }
03464 
03465 /**
03466   * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
03467   * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
03468   * @param  TIMx Timer instance
03469   * @retval State of bit (1 or 0).
03470   */
03471 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)
03472 {
03473   return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
03474 }
03475 
03476 /**
03477   * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
03478   * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
03479   * @param  TIMx Timer instance
03480   * @retval None
03481   */
03482 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)
03483 {
03484   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
03485 }
03486 
03487 /**
03488   * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
03489   * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
03490   * @param  TIMx Timer instance
03491   * @retval State of bit (1 or 0).
03492   */
03493 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)
03494 {
03495   return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
03496 }
03497 
03498 /**
03499   * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
03500   * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
03501   * @param  TIMx Timer instance
03502   * @retval None
03503   */
03504 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)
03505 {
03506   WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
03507 }
03508 
03509 /**
03510   * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
03511   * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
03512   * @param  TIMx Timer instance
03513   * @retval State of bit (1 or 0).
03514   */
03515 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef * TIMx)
03516 {
03517   return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
03518 }
03519 /**
03520   * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
03521   * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
03522   * @param  TIMx Timer instance
03523   * @retval None
03524   */
03525 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)
03526 {
03527   WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
03528 }
03529 
03530 /**
03531   * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
03532   * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
03533   * @param  TIMx Timer instance
03534   * @retval State of bit (1 or 0).
03535   */
03536 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef * TIMx)
03537 {
03538   return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
03539 }
03540 
03541 /**
03542   * @brief  Clear the commutation interrupt flag (COMIF).
03543   * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
03544   * @param  TIMx Timer instance
03545   * @retval None
03546   */
03547 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)
03548 {
03549   WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
03550 }
03551 
03552 /**
03553   * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
03554   * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
03555   * @param  TIMx Timer instance
03556   * @retval State of bit (1 or 0).
03557   */
03558 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx)
03559 {
03560   return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
03561 }
03562 
03563 /**
03564   * @brief  Clear the trigger interrupt flag (TIF).
03565   * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
03566   * @param  TIMx Timer instance
03567   * @retval None
03568   */
03569 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)
03570 {
03571   WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
03572 }
03573 
03574 /**
03575   * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
03576   * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
03577   * @param  TIMx Timer instance
03578   * @retval State of bit (1 or 0).
03579   */
03580 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)
03581 {
03582   return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
03583 }
03584 
03585 /**
03586   * @brief  Clear the break interrupt flag (BIF).
03587   * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
03588   * @param  TIMx Timer instance
03589   * @retval None
03590   */
03591 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)
03592 {
03593   WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
03594 }
03595 
03596 /**
03597   * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
03598   * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
03599   * @param  TIMx Timer instance
03600   * @retval State of bit (1 or 0).
03601   */
03602 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx)
03603 {
03604   return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
03605 }
03606 
03607 /**
03608   * @brief  Clear the break 2 interrupt flag (B2IF).
03609   * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
03610   * @param  TIMx Timer instance
03611   * @retval None
03612   */
03613 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)
03614 {
03615   WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
03616 }
03617 
03618 /**
03619   * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
03620   * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
03621   * @param  TIMx Timer instance
03622   * @retval State of bit (1 or 0).
03623   */
03624 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef * TIMx)
03625 {
03626   return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
03627 }
03628 
03629 /**
03630   * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
03631   * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
03632   * @param  TIMx Timer instance
03633   * @retval None
03634   */
03635 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)
03636 {
03637   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
03638 }
03639 
03640 /**
03641   * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
03642   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
03643   * @param  TIMx Timer instance
03644   * @retval State of bit (1 or 0).
03645   */
03646 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)
03647 {
03648   return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
03649 }
03650 
03651 /**
03652   * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
03653   * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
03654   * @param  TIMx Timer instance
03655   * @retval None
03656   */
03657 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)
03658 {
03659   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
03660 }
03661 
03662 /**
03663   * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
03664   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
03665   * @param  TIMx Timer instance
03666   * @retval State of bit (1 or 0).
03667   */
03668 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)
03669 {
03670   return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
03671 }
03672 
03673 /**
03674   * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
03675   * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
03676   * @param  TIMx Timer instance
03677   * @retval None
03678   */
03679 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)
03680 {
03681   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
03682 }
03683 
03684 /**
03685   * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
03686   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
03687   * @param  TIMx Timer instance
03688   * @retval State of bit (1 or 0).
03689   */
03690 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)
03691 {
03692   return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
03693 }
03694 
03695 /**
03696   * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
03697   * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
03698   * @param  TIMx Timer instance
03699   * @retval None
03700   */
03701 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)
03702 {
03703   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
03704 }
03705 
03706 /**
03707   * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
03708   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
03709   * @param  TIMx Timer instance
03710   * @retval State of bit (1 or 0).
03711   */
03712 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)
03713 {
03714   return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
03715 }
03716 
03717 /**
03718   * @brief  Clear the system break interrupt flag (SBIF).
03719   * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
03720   * @param  TIMx Timer instance
03721   * @retval None
03722   */
03723 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)
03724 {
03725   WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
03726 }
03727 
03728 /**
03729   * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
03730   * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
03731   * @param  TIMx Timer instance
03732   * @retval State of bit (1 or 0).
03733   */
03734 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef * TIMx)
03735 {
03736   return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF));
03737 }
03738 
03739 /**
03740   * @}
03741   */
03742 
03743 /** @defgroup TIM_LL_EF_IT_Management IT_Management
03744   * @{
03745   */
03746 /**
03747   * @brief  Enable update interrupt (UIE).
03748   * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
03749   * @param  TIMx Timer instance
03750   * @retval None
03751   */
03752 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)
03753 {
03754   SET_BIT(TIMx->DIER, TIM_DIER_UIE);
03755 }
03756 
03757 /**
03758   * @brief  Disable update interrupt (UIE).
03759   * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
03760   * @param  TIMx Timer instance
03761   * @retval None
03762   */
03763 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)
03764 {
03765   CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
03766 }
03767 
03768 /**
03769   * @brief  Indicates whether the update interrupt (UIE) is enabled.
03770   * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
03771   * @param  TIMx Timer instance
03772   * @retval State of bit (1 or 0).
03773   */
03774 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)
03775 {
03776   return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
03777 }
03778 
03779 /**
03780   * @brief  Enable capture/compare 1 interrupt (CC1IE).
03781   * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
03782   * @param  TIMx Timer instance
03783   * @retval None
03784   */
03785 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)
03786 {
03787   SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
03788 }
03789 
03790 /**
03791   * @brief  Disable capture/compare 1  interrupt (CC1IE).
03792   * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
03793   * @param  TIMx Timer instance
03794   * @retval None
03795   */
03796 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)
03797 {
03798   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
03799 }
03800 
03801 /**
03802   * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
03803   * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
03804   * @param  TIMx Timer instance
03805   * @retval State of bit (1 or 0).
03806   */
03807 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)
03808 {
03809   return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
03810 }
03811 
03812 /**
03813   * @brief  Enable capture/compare 2 interrupt (CC2IE).
03814   * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
03815   * @param  TIMx Timer instance
03816   * @retval None
03817   */
03818 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)
03819 {
03820   SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
03821 }
03822 
03823 /**
03824   * @brief  Disable capture/compare 2  interrupt (CC2IE).
03825   * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
03826   * @param  TIMx Timer instance
03827   * @retval None
03828   */
03829 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)
03830 {
03831   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
03832 }
03833 
03834 /**
03835   * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
03836   * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
03837   * @param  TIMx Timer instance
03838   * @retval State of bit (1 or 0).
03839   */
03840 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)
03841 {
03842   return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
03843 }
03844 
03845 /**
03846   * @brief  Enable capture/compare 3 interrupt (CC3IE).
03847   * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
03848   * @param  TIMx Timer instance
03849   * @retval None
03850   */
03851 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)
03852 {
03853   SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
03854 }
03855 
03856 /**
03857   * @brief  Disable capture/compare 3  interrupt (CC3IE).
03858   * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
03859   * @param  TIMx Timer instance
03860   * @retval None
03861   */
03862 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)
03863 {
03864   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
03865 }
03866 
03867 /**
03868   * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
03869   * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
03870   * @param  TIMx Timer instance
03871   * @retval State of bit (1 or 0).
03872   */
03873 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)
03874 {
03875   return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
03876 }
03877 
03878 /**
03879   * @brief  Enable capture/compare 4 interrupt (CC4IE).
03880   * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
03881   * @param  TIMx Timer instance
03882   * @retval None
03883   */
03884 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)
03885 {
03886   SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
03887 }
03888 
03889 /**
03890   * @brief  Disable capture/compare 4  interrupt (CC4IE).
03891   * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
03892   * @param  TIMx Timer instance
03893   * @retval None
03894   */
03895 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)
03896 {
03897   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
03898 }
03899 
03900 /**
03901   * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
03902   * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
03903   * @param  TIMx Timer instance
03904   * @retval State of bit (1 or 0).
03905   */
03906 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)
03907 {
03908   return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
03909 }
03910 
03911 /**
03912   * @brief  Enable commutation interrupt (COMIE).
03913   * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
03914   * @param  TIMx Timer instance
03915   * @retval None
03916   */
03917 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)
03918 {
03919   SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
03920 }
03921 
03922 /**
03923   * @brief  Disable commutation interrupt (COMIE).
03924   * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
03925   * @param  TIMx Timer instance
03926   * @retval None
03927   */
03928 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)
03929 {
03930   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
03931 }
03932 
03933 /**
03934   * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
03935   * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
03936   * @param  TIMx Timer instance
03937   * @retval State of bit (1 or 0).
03938   */
03939 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx)
03940 {
03941   return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
03942 }
03943 
03944 /**
03945   * @brief  Enable trigger interrupt (TIE).
03946   * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
03947   * @param  TIMx Timer instance
03948   * @retval None
03949   */
03950 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)
03951 {
03952   SET_BIT(TIMx->DIER, TIM_DIER_TIE);
03953 }
03954 
03955 /**
03956   * @brief  Disable trigger interrupt (TIE).
03957   * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
03958   * @param  TIMx Timer instance
03959   * @retval None
03960   */
03961 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)
03962 {
03963   CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
03964 }
03965 
03966 /**
03967   * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
03968   * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
03969   * @param  TIMx Timer instance
03970   * @retval State of bit (1 or 0).
03971   */
03972 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)
03973 {
03974   return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
03975 }
03976 
03977 /**
03978   * @brief  Enable break interrupt (BIE).
03979   * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
03980   * @param  TIMx Timer instance
03981   * @retval None
03982   */
03983 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)
03984 {
03985   SET_BIT(TIMx->DIER, TIM_DIER_BIE);
03986 }
03987 
03988 /**
03989   * @brief  Disable break interrupt (BIE).
03990   * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
03991   * @param  TIMx Timer instance
03992   * @retval None
03993   */
03994 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)
03995 {
03996   CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
03997 }
03998 
03999 /**
04000   * @brief  Indicates whether the break interrupt (BIE) is enabled.
04001   * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
04002   * @param  TIMx Timer instance
04003   * @retval State of bit (1 or 0).
04004   */
04005 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx)
04006 {
04007   return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
04008 }
04009 
04010 /**
04011   * @}
04012   */
04013 
04014 /** @defgroup TIM_LL_EF_DMA_Management DMA_Management
04015   * @{
04016   */
04017 /**
04018   * @brief  Enable update DMA request (UDE).
04019   * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
04020   * @param  TIMx Timer instance
04021   * @retval None
04022   */
04023 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)
04024 {
04025   SET_BIT(TIMx->DIER, TIM_DIER_UDE);
04026 }
04027 
04028 /**
04029   * @brief  Disable update DMA request (UDE).
04030   * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
04031   * @param  TIMx Timer instance
04032   * @retval None
04033   */
04034 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)
04035 {
04036   CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
04037 }
04038 
04039 /**
04040   * @brief  Indicates whether the update DMA request  (UDE) is enabled.
04041   * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
04042   * @param  TIMx Timer instance
04043   * @retval State of bit (1 or 0).
04044   */
04045 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)
04046 {
04047   return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
04048 }
04049 
04050 /**
04051   * @brief  Enable capture/compare 1 DMA request (CC1DE).
04052   * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
04053   * @param  TIMx Timer instance
04054   * @retval None
04055   */
04056 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)
04057 {
04058   SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04059 }
04060 
04061 /**
04062   * @brief  Disable capture/compare 1  DMA request (CC1DE).
04063   * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
04064   * @param  TIMx Timer instance
04065   * @retval None
04066   */
04067 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)
04068 {
04069   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04070 }
04071 
04072 /**
04073   * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
04074   * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
04075   * @param  TIMx Timer instance
04076   * @retval State of bit (1 or 0).
04077   */
04078 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)
04079 {
04080   return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
04081 }
04082 
04083 /**
04084   * @brief  Enable capture/compare 2 DMA request (CC2DE).
04085   * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
04086   * @param  TIMx Timer instance
04087   * @retval None
04088   */
04089 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)
04090 {
04091   SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04092 }
04093 
04094 /**
04095   * @brief  Disable capture/compare 2  DMA request (CC2DE).
04096   * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
04097   * @param  TIMx Timer instance
04098   * @retval None
04099   */
04100 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)
04101 {
04102   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04103 }
04104 
04105 /**
04106   * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
04107   * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
04108   * @param  TIMx Timer instance
04109   * @retval State of bit (1 or 0).
04110   */
04111 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)
04112 {
04113   return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
04114 }
04115 
04116 /**
04117   * @brief  Enable capture/compare 3 DMA request (CC3DE).
04118   * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
04119   * @param  TIMx Timer instance
04120   * @retval None
04121   */
04122 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)
04123 {
04124   SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
04125 }
04126 
04127 /**
04128   * @brief  Disable capture/compare 3  DMA request (CC3DE).
04129   * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
04130   * @param  TIMx Timer instance
04131   * @retval None
04132   */
04133 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)
04134 {
04135   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
04136 }
04137 
04138 /**
04139   * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
04140   * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
04141   * @param  TIMx Timer instance
04142   * @retval State of bit (1 or 0).
04143   */
04144 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)
04145 {
04146   return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
04147 }
04148 
04149 /**
04150   * @brief  Enable capture/compare 4 DMA request (CC4DE).
04151   * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
04152   * @param  TIMx Timer instance
04153   * @retval None
04154   */
04155 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)
04156 {
04157   SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
04158 }
04159 
04160 /**
04161   * @brief  Disable capture/compare 4  DMA request (CC4DE).
04162   * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
04163   * @param  TIMx Timer instance
04164   * @retval None
04165   */
04166 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)
04167 {
04168   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
04169 }
04170 
04171 /**
04172   * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
04173   * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
04174   * @param  TIMx Timer instance
04175   * @retval State of bit (1 or 0).
04176   */
04177 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)
04178 {
04179   return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
04180 }
04181 
04182 /**
04183   * @brief  Enable commutation DMA request (COMDE).
04184   * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
04185   * @param  TIMx Timer instance
04186   * @retval None
04187   */
04188 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)
04189 {
04190   SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
04191 }
04192 
04193 /**
04194   * @brief  Disable commutation DMA request (COMDE).
04195   * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
04196   * @param  TIMx Timer instance
04197   * @retval None
04198   */
04199 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)
04200 {
04201   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
04202 }
04203 
04204 /**
04205   * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
04206   * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
04207   * @param  TIMx Timer instance
04208   * @retval State of bit (1 or 0).
04209   */
04210 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx)
04211 {
04212   return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
04213 }
04214 
04215 /**
04216   * @brief  Enable trigger interrupt (TDE).
04217   * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
04218   * @param  TIMx Timer instance
04219   * @retval None
04220   */
04221 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)
04222 {
04223   SET_BIT(TIMx->DIER, TIM_DIER_TDE);
04224 }
04225 
04226 /**
04227   * @brief  Disable trigger interrupt (TDE).
04228   * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
04229   * @param  TIMx Timer instance
04230   * @retval None
04231   */
04232 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)
04233 {
04234   CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
04235 }
04236 
04237 /**
04238   * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
04239   * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
04240   * @param  TIMx Timer instance
04241   * @retval State of bit (1 or 0).
04242   */
04243 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)
04244 {
04245   return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
04246 }
04247 
04248 /**
04249   * @}
04250   */
04251 
04252 /** @defgroup TIM_LL_EF_EVENT_Management EVENT_Management
04253   * @{
04254   */
04255 /**
04256   * @brief  Generate an update event.
04257   * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
04258   * @param  TIMx Timer instance
04259   * @retval None
04260   */
04261 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)
04262 {
04263   SET_BIT(TIMx->EGR, TIM_EGR_UG);
04264 }
04265 
04266 /**
04267   * @brief  Generate Capture/Compare 1 event.
04268   * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
04269   * @param  TIMx Timer instance
04270   * @retval None
04271   */
04272 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)
04273 {
04274   SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
04275 }
04276 
04277 /**
04278   * @brief  Generate Capture/Compare 2 event.
04279   * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
04280   * @param  TIMx Timer instance
04281   * @retval None
04282   */
04283 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)
04284 {
04285   SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
04286 }
04287 
04288 /**
04289   * @brief  Generate Capture/Compare 3 event.
04290   * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
04291   * @param  TIMx Timer instance
04292   * @retval None
04293   */
04294 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)
04295 {
04296   SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
04297 }
04298 
04299 /**
04300   * @brief  Generate Capture/Compare 4 event.
04301   * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
04302   * @param  TIMx Timer instance
04303   * @retval None
04304   */
04305 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)
04306 {
04307   SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
04308 }
04309 
04310 /**
04311   * @brief  Generate commutation event.
04312   * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
04313   * @param  TIMx Timer instance
04314   * @retval None
04315   */
04316 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)
04317 {
04318   SET_BIT(TIMx->EGR, TIM_EGR_COMG);
04319 }
04320 
04321 /**
04322   * @brief  Generate trigger event.
04323   * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
04324   * @param  TIMx Timer instance
04325   * @retval None
04326   */
04327 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)
04328 {
04329   SET_BIT(TIMx->EGR, TIM_EGR_TG);
04330 }
04331 
04332 /**
04333   * @brief  Generate break event.
04334   * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
04335   * @param  TIMx Timer instance
04336   * @retval None
04337   */
04338 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)
04339 {
04340   SET_BIT(TIMx->EGR, TIM_EGR_BG);
04341 }
04342 
04343 /**
04344   * @brief  Generate break 2 event.
04345   * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
04346   * @param  TIMx Timer instance
04347   * @retval None
04348   */
04349 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)
04350 {
04351   SET_BIT(TIMx->EGR, TIM_EGR_B2G);
04352 }
04353 
04354 /**
04355   * @}
04356   */
04357 
04358 /**
04359   * @}
04360   */
04361 
04362 /**
04363   * @}
04364   */
04365 
04366 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
04367 
04368 /**
04369   * @}
04370   */
04371 
04372 #ifdef __cplusplus
04373 }
04374 #endif
04375 
04376 #endif /* __STM32L4xx_LL_TIM_H */
04377 
04378 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
04379