Eric Lewiston
Hal Drivers for L4
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stm32l4xx_ll_spi.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_spi.h 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief Header file of SPI LL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_LL_SPI_H 00040 #define __STM32L4xx_LL_SPI_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx.h" 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined (SPI1) || defined (SPI2) || defined (SPI3) 00054 00055 /** @defgroup SPI_LL SPI 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 00062 /* Private constants ---------------------------------------------------------*/ 00063 00064 /* Private macros ------------------------------------------------------------*/ 00065 00066 /* Exported types ------------------------------------------------------------*/ 00067 /* Exported constants --------------------------------------------------------*/ 00068 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants 00069 * @{ 00070 */ 00071 00072 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines 00073 * @brief Flags defines which can be used with LL_SPI_ReadReg function 00074 * @{ 00075 */ 00076 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ 00077 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ 00078 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ 00079 #define LL_SPI_SR_UDR SPI_SR_UDR /*!< Underrun flag */ 00080 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ 00081 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ 00082 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ 00083 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ 00084 /** 00085 * @} 00086 */ 00087 00088 /** @defgroup SPI_LL_EC_IT IT Defines 00089 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions 00090 * @{ 00091 */ 00092 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ 00093 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ 00094 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ 00095 /** 00096 * @} 00097 */ 00098 00099 /** @defgroup SPI_LL_EC_MODE MODE 00100 * @{ 00101 */ 00102 #define LL_SPI_MODE_MASTER ((uint32_t)0x00000104) /*!< Master configuration */ 00103 #define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000) /*!< Slave configuration */ 00104 /** 00105 * @} 00106 */ 00107 00108 /** @defgroup SPI_LL_EC_PROTOCOL PROTOCOL 00109 * @{ 00110 */ 00111 #define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000) /*!< Motorola mode. Used as default value */ 00112 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ 00113 /** 00114 * @} 00115 */ 00116 00117 /** @defgroup SPI_LL_EC_PHASE PHASE 00118 * @{ 00119 */ 00120 #define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000) /*!< First clock transition is the first data capture edge */ 00121 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ 00122 /** 00123 * @} 00124 */ 00125 00126 /** @defgroup SPI_LL_EC_POLARITY POLARITY 00127 * @{ 00128 */ 00129 #define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000) /*!< Clock to 0 when idle */ 00130 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ 00131 /** 00132 * @} 00133 */ 00134 00135 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER BAUDRATEPRESCALER 00136 * @{ 00137 */ 00138 #define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000) /*!< Baudrate control equal to fPCLK/2 */ 00139 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< Baudrate control equal to fPCLK/4 */ 00140 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< Baudrate control equal to fPCLK/8 */ 00141 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baudrate control equal to fPCLK/16 */ 00142 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< Baudrate control equal to fPCLK/32 */ 00143 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< Baudrate control equal to fPCLK/64 */ 00144 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< Baudrate control equal to fPCLK/128 */ 00145 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baudrate control equal to fPCLK/256 */ 00146 /** 00147 * @} 00148 */ 00149 00150 /** @defgroup SPI_LL_EC_BIT_ORDER TRANSMISSION BIT ORDER 00151 * @{ 00152 */ 00153 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received withthe LSB first */ 00154 #define LL_SPI_MSB_FIRST ((uint32_t)0x00000000) /*!< Data is transmitted/received withthe MSB first */ 00155 /** 00156 * @} 00157 */ 00158 00159 /** @defgroup SPI_LL_EC_TRANSFER_MODE TRANSFER MODE 00160 * @{ 00161 */ 00162 #define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000) /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ 00163 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ 00164 #define LL_SPI_HALF_DUPLEX (SPI_CR1_BIDIMODE) /*!< Half-Duplex mode. Rx or Tx transfer on 1 line */ 00165 /** 00166 * @} 00167 */ 00168 00169 /** @defgroup SPI_LL_EC_DIRECTION_HALF_DUPLEX DIRECTION HALF DUPLEX 00170 * @{ 00171 */ 00172 #define LL_SPI_DIRECTION_HALF_DUPLEX_TX (SPI_CR1_BIDIOE) /*!< Tx transfer selection for Half-Duplex mode */ 00173 #define LL_SPI_DIRECTION_HALF_DUPLEX_RX (0x00000000) /*!< Rx transfer selection for Half-Duplex mode */ 00174 /** 00175 * @} 00176 */ 00177 00178 /** @defgroup SPI_LL_EC_DATAWIDTH DATAWIDTH 00179 * @{ 00180 */ 00181 #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */ 00182 #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */ 00183 #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */ 00184 #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */ 00185 #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */ 00186 #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */ 00187 #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */ 00188 #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */ 00189 #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */ 00190 #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */ 00191 #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */ 00192 #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */ 00193 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */ 00194 /** 00195 * @} 00196 */ 00197 00198 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO THRESHOLD 00199 * @{ 00200 */ 00201 #define LL_SPI_RX_FIFO_TH_HALF ((uint32_t)0x00000000) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ 00202 #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */ 00203 /** 00204 * @} 00205 */ 00206 00207 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC LENGTH 00208 * @{ 00209 */ 00210 #define LL_SPI_CRC_8BIT ((uint32_t)0x00000000) /*!< 8-bit CRC length */ 00211 #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ 00212 /** 00213 * @} 00214 */ 00215 00216 /** @defgroup SPI_LL_EC_NSS_MODE NSS MODE 00217 * @{ 00218 */ 00219 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ 00220 #define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) /*!< NSS pin used in Input. Only used in Master mode */ 00221 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ 00222 /** 00223 * @} 00224 */ 00225 00226 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO LEVEL 00227 * @{ 00228 */ 00229 #define LL_SPI_RX_FIFO_EMPTY ((uint32_t)0x00000000) /*!< FIFO reception empty */ 00230 #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ 00231 #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ 00232 #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ 00233 /** 00234 * @} 00235 */ 00236 00237 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO LEVEL 00238 * @{ 00239 */ 00240 #define LL_SPI_TX_FIFO_EMPTY ((uint32_t)0x00000000) /*!< FIFO transmission empty */ 00241 #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ 00242 #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ 00243 #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ 00244 /** 00245 * @} 00246 */ 00247 00248 /** @defgroup SPI_LL_EC_DMA_PARITY DMA PARITY 00249 * @{ 00250 */ 00251 #define LL_SPI_DMA_PARITY_EVEN ((uint32_t)0x00000000) /*!< Select DMA parity Even */ 00252 #define LL_SPI_DMA_PARITY_ODD ((uint32_t)0x00000001) /*!< Select DMA parity Odd */ 00253 00254 /** 00255 * @} 00256 */ 00257 00258 /** 00259 * @} 00260 */ 00261 00262 /* Exported macro ------------------------------------------------------------*/ 00263 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros 00264 * @{ 00265 */ 00266 00267 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros 00268 * @{ 00269 */ 00270 00271 /** 00272 * @brief Write a value in SPI register 00273 * @param __INSTANCE__ SPI Instance 00274 * @param __REG__ Register to be written 00275 * @param __VALUE__ Value to be written in the register 00276 * @retval None 00277 */ 00278 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00279 00280 /** 00281 * @brief Read a value in SPI register 00282 * @param __INSTANCE__ SPI Instance 00283 * @param __REG__ Register to be read 00284 * @retval Register value 00285 */ 00286 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00287 /** 00288 * @} 00289 */ 00290 00291 /** 00292 * @} 00293 */ 00294 00295 /* Exported functions --------------------------------------------------------*/ 00296 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions 00297 * @{ 00298 */ 00299 00300 /** @defgroup SPI_LL_EF_Configuration Configuration 00301 * @{ 00302 */ 00303 00304 /** 00305 * @brief Enable SPI peripheral 00306 * @rmtoll CR1 SPE LL_SPI_Enable 00307 * @param SPIx SPI Instance 00308 * @retval None 00309 */ 00310 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) 00311 { 00312 SET_BIT(SPIx->CR1, SPI_CR1_SPE); 00313 } 00314 00315 /** 00316 * @brief Disable SPI peripheral 00317 * @note When disabling the SPI, follow the procedure described in the Reference Manual. 00318 * @rmtoll CR1 SPE LL_SPI_Disable 00319 * @param SPIx SPI Instance 00320 * @retval None 00321 */ 00322 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) 00323 { 00324 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 00325 } 00326 00327 /** 00328 * @brief Check if SPI peripheral is enabled 00329 * @rmtoll CR1 SPE LL_SPI_IsEnabled 00330 * @param SPIx SPI Instance 00331 * @retval None 00332 */ 00333 __STATIC_INLINE void LL_SPI_IsEnabled(SPI_TypeDef *SPIx) 00334 { 00335 } 00336 00337 /** 00338 * @brief Set SPI Mode to Master or Slave 00339 * @note This bit should not be changed when communication is ongoing. 00340 * @rmtoll CR1 MSTR LL_SPI_SetMode\n 00341 * CR1 SSI LL_SPI_SetMode 00342 * @param SPIx SPI Instance 00343 * @param Mode This parameter can be one of the following values: 00344 * @arg @ref LL_SPI_MODE_MASTER 00345 * @arg @ref LL_SPI_MODE_SLAVE 00346 * @retval None 00347 */ 00348 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) 00349 { 00350 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); 00351 } 00352 00353 /** 00354 * @brief Get SPI Mode (Master or Slave) 00355 * @rmtoll CR1 MSTR LL_SPI_GetMode\n 00356 * CR1 SSI LL_SPI_GetMode 00357 * @param SPIx SPI Instance 00358 * @retval Returned value can be one of the following values: 00359 * @arg @ref LL_SPI_MODE_MASTER 00360 * @arg @ref LL_SPI_MODE_SLAVE 00361 */ 00362 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) 00363 { 00364 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); 00365 } 00366 00367 /** 00368 * @brief Set Serial protocol used 00369 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00370 * @rmtoll CR2 FRF LL_SPI_SetStandard 00371 * @param SPIx SPI Instance 00372 * @param Standard This parameter can be one of the following values: 00373 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 00374 * @arg @ref LL_SPI_PROTOCOL_TI 00375 * @retval None 00376 */ 00377 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) 00378 { 00379 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); 00380 } 00381 00382 /** 00383 * @brief Set Serial protocol used 00384 * @rmtoll CR2 FRF LL_SPI_GetStandard 00385 * @param SPIx SPI Instance 00386 * @retval Returned value can be one of the following values: 00387 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 00388 * @arg @ref LL_SPI_PROTOCOL_TI 00389 */ 00390 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) 00391 { 00392 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); 00393 } 00394 00395 /** 00396 * @brief Set Clock phase 00397 * @note This bit should not be changed when communication is ongoing. 00398 * This bit is not used in SPI TI mode. 00399 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase 00400 * @param SPIx SPI Instance 00401 * @param ClockPhase This parameter can be one of the following values: 00402 * @arg @ref LL_SPI_PHASE_1EDGE 00403 * @arg @ref LL_SPI_PHASE_2EDGE 00404 * @retval None 00405 */ 00406 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) 00407 { 00408 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); 00409 } 00410 00411 /** 00412 * @brief Get Clock phase 00413 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase 00414 * @param SPIx SPI Instance 00415 * @retval Returned value can be one of the following values: 00416 * @arg @ref LL_SPI_PHASE_1EDGE 00417 * @arg @ref LL_SPI_PHASE_2EDGE 00418 */ 00419 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) 00420 { 00421 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); 00422 } 00423 00424 /** 00425 * @brief Set Clock polarity 00426 * @note This bit should not be changed when communication is ongoing. 00427 * This bit is not used in SPI TI mode. 00428 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity 00429 * @param SPIx SPI Instance 00430 * @param ClockPolarity This parameter can be one of the following values: 00431 * @arg @ref LL_SPI_POLARITY_LOW 00432 * @arg @ref LL_SPI_POLARITY_HIGH 00433 * @retval None 00434 */ 00435 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) 00436 { 00437 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); 00438 } 00439 00440 /** 00441 * @brief Get Clock polarity 00442 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity 00443 * @param SPIx SPI Instance 00444 * @retval Returned value can be one of the following values: 00445 * @arg @ref LL_SPI_POLARITY_LOW 00446 * @arg @ref LL_SPI_POLARITY_HIGH 00447 */ 00448 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) 00449 { 00450 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); 00451 } 00452 00453 /** 00454 * @brief Set Baudrate Prescaler 00455 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Pescaler. 00456 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler 00457 * @param SPIx SPI Instance 00458 * @param Baudrate This parameter can be one of the following values: 00459 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 00460 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 00461 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 00462 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 00463 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 00464 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 00465 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 00466 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 00467 * @retval None 00468 */ 00469 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate) 00470 { 00471 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, Baudrate); 00472 } 00473 00474 /** 00475 * @brief Get Baudrate Prescaler 00476 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler 00477 * @param SPIx SPI Instance 00478 * @retval Returned value can be one of the following values: 00479 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 00480 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 00481 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 00482 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 00483 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 00484 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 00485 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 00486 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 00487 */ 00488 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) 00489 { 00490 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); 00491 } 00492 00493 /** 00494 * @brief Set Transfer Bit Order 00495 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00496 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder 00497 * @param SPIx SPI Instance 00498 * @param BitOrder This parameter can be one of the following values: 00499 * @arg @ref LL_SPI_LSB_FIRST 00500 * @arg @ref LL_SPI_MSB_FIRST 00501 * @retval None 00502 */ 00503 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) 00504 { 00505 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); 00506 } 00507 00508 /** 00509 * @brief Get Transfer Bit Order 00510 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder 00511 * @param SPIx SPI Instance 00512 * @retval Returned value can be one of the following values: 00513 * @arg @ref LL_SPI_LSB_FIRST 00514 * @arg @ref LL_SPI_MSB_FIRST 00515 */ 00516 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) 00517 { 00518 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); 00519 } 00520 00521 /** 00522 * @brief Set Transfer Direction Mode 00523 * @note For Half-Duplex mode, Rx Direction is set by default. 00524 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. 00525 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n 00526 * CR1 BIDIMODE LL_SPI_SetTransferDirection 00527 * @param SPIx SPI Instance 00528 * @param TransferDirection This parameter can be one of the following values: 00529 * @arg @ref LL_SPI_FULL_DUPLEX 00530 * @arg @ref LL_SPI_SIMPLEX_RX 00531 * @arg @ref LL_SPI_HALF_DUPLEX 00532 * @retval None 00533 */ 00534 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) 00535 { 00536 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE, TransferDirection); 00537 } 00538 00539 /** 00540 * @brief Get Transfer Direction Mode 00541 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n 00542 * CR1 BIDIMODE LL_SPI_GetTransferDirection 00543 * @param SPIx SPI Instance 00544 * @retval Returned value can be one of the following values: 00545 * @arg @ref LL_SPI_FULL_DUPLEX 00546 * @arg @ref LL_SPI_SIMPLEX_RX 00547 * @arg @ref LL_SPI_HALF_DUPLEX 00548 */ 00549 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) 00550 { 00551 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)); 00552 } 00553 00554 /** 00555 * @brief Set direction for Half-Duplex Mode 00556 * @note In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. 00557 * @rmtoll CR1 BIDIOE LL_SPI_SetHalfDuplexDirection 00558 * @param SPIx SPI Instance 00559 * @param HalfDuplexDirection This parameter can be one of the following values: 00560 * @arg @ref LL_SPI_DIRECTION_HALF_DUPLEX_TX 00561 * @arg @ref LL_SPI_DIRECTION_HALF_DUPLEX_RX 00562 * @retval None 00563 */ 00564 __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection) 00565 { 00566 MODIFY_REG(SPIx->CR1, SPI_CR1_BIDIOE, HalfDuplexDirection); 00567 } 00568 00569 /** 00570 * @brief Get direction for Half-Duplex Mode 00571 * @note In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. 00572 * @rmtoll CR1 BIDIOE LL_SPI_GetHalfDuplexDirection 00573 * @param SPIx SPI Instance 00574 * @retval Returned value can be one of the following values: 00575 * @arg @ref LL_SPI_DIRECTION_HALF_DUPLEX_TX 00576 * @arg @ref LL_SPI_DIRECTION_HALF_DUPLEX_RX 00577 */ 00578 __STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx) 00579 { 00580 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BIDIOE)); 00581 } 00582 00583 /** 00584 * @brief Set Frame Data Size 00585 * @rmtoll CR2 DS LL_SPI_SetDataWidth 00586 * @param SPIx SPI Instance 00587 * @param DataWidth This parameter can be one of the following values: 00588 * @arg @ref LL_SPI_DATAWIDTH_4BIT 00589 * @arg @ref LL_SPI_DATAWIDTH_5BIT 00590 * @arg @ref LL_SPI_DATAWIDTH_6BIT 00591 * @arg @ref LL_SPI_DATAWIDTH_7BIT 00592 * @arg @ref LL_SPI_DATAWIDTH_8BIT 00593 * @arg @ref LL_SPI_DATAWIDTH_9BIT 00594 * @arg @ref LL_SPI_DATAWIDTH_10BIT 00595 * @arg @ref LL_SPI_DATAWIDTH_11BIT 00596 * @arg @ref LL_SPI_DATAWIDTH_12BIT 00597 * @arg @ref LL_SPI_DATAWIDTH_13BIT 00598 * @arg @ref LL_SPI_DATAWIDTH_14BIT 00599 * @arg @ref LL_SPI_DATAWIDTH_15BIT 00600 * @arg @ref LL_SPI_DATAWIDTH_16BIT 00601 * @retval None 00602 */ 00603 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) 00604 { 00605 MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); 00606 } 00607 00608 /** 00609 * @brief Get Frame Data Size 00610 * @rmtoll CR2 DS LL_SPI_GetDataWidth 00611 * @param SPIx SPI Instance 00612 * @retval Returned value can be one of the following values: 00613 * @arg @ref LL_SPI_DATAWIDTH_4BIT 00614 * @arg @ref LL_SPI_DATAWIDTH_5BIT 00615 * @arg @ref LL_SPI_DATAWIDTH_6BIT 00616 * @arg @ref LL_SPI_DATAWIDTH_7BIT 00617 * @arg @ref LL_SPI_DATAWIDTH_8BIT 00618 * @arg @ref LL_SPI_DATAWIDTH_9BIT 00619 * @arg @ref LL_SPI_DATAWIDTH_10BIT 00620 * @arg @ref LL_SPI_DATAWIDTH_11BIT 00621 * @arg @ref LL_SPI_DATAWIDTH_12BIT 00622 * @arg @ref LL_SPI_DATAWIDTH_13BIT 00623 * @arg @ref LL_SPI_DATAWIDTH_14BIT 00624 * @arg @ref LL_SPI_DATAWIDTH_15BIT 00625 * @arg @ref LL_SPI_DATAWIDTH_16BIT 00626 */ 00627 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) 00628 { 00629 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); 00630 } 00631 00632 /** 00633 * @brief Set threshold of RXFIFO that triggers an RXNE event 00634 * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold 00635 * @param SPIx SPI Instance 00636 * @param Threshold This parameter can be one of the following values: 00637 * @arg @ref LL_SPI_RX_FIFO_TH_HALF 00638 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 00639 * @retval None 00640 */ 00641 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) 00642 { 00643 MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); 00644 } 00645 00646 /** 00647 * @brief Get threshold of RXFIFO that triggers an RXNE event 00648 * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold 00649 * @param SPIx SPI Instance 00650 * @retval Returned value can be one of the following values: 00651 * @arg @ref LL_SPI_RX_FIFO_TH_HALF 00652 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 00653 */ 00654 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) 00655 { 00656 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); 00657 } 00658 00659 /** 00660 * @} 00661 */ 00662 00663 /** @defgroup SPI_EF_CRC_Management CRC_Management 00664 * @{ 00665 */ 00666 00667 /** 00668 * @brief Enable CRC 00669 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00670 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC 00671 * @param SPIx SPI Instance 00672 * @retval None 00673 */ 00674 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) 00675 { 00676 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); 00677 } 00678 00679 /** 00680 * @brief Disable CRC 00681 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00682 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC 00683 * @param SPIx SPI Instance 00684 * @retval None 00685 */ 00686 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) 00687 { 00688 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); 00689 } 00690 00691 /** 00692 * @brief Check if CRC is enabled 00693 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00694 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC 00695 * @param SPIx SPI Instance 00696 * @retval None 00697 */ 00698 __STATIC_INLINE void LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) 00699 { 00700 } 00701 00702 /** 00703 * @brief Set CRC Length 00704 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00705 * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth 00706 * @param SPIx SPI Instance 00707 * @param CRCLength This parameter can be one of the following values: 00708 * @arg @ref LL_SPI_CRC_8BIT 00709 * @arg @ref LL_SPI_CRC_16BIT 00710 * @retval None 00711 */ 00712 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) 00713 { 00714 MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); 00715 } 00716 00717 /** 00718 * @brief Get CRC Length 00719 * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth 00720 * @param SPIx SPI Instance 00721 * @retval Returned value can be one of the following values: 00722 * @arg @ref LL_SPI_CRC_8BIT 00723 * @arg @ref LL_SPI_CRC_16BIT 00724 */ 00725 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) 00726 { 00727 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); 00728 } 00729 00730 /** 00731 * @brief Set CRCNext to transfer CRC on the line 00732 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. 00733 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext 00734 * @param SPIx SPI Instance 00735 * @retval None 00736 */ 00737 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) 00738 { 00739 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); 00740 } 00741 00742 /** 00743 * @brief Set polynomial for CRC calculation 00744 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial 00745 * @param SPIx SPI Instance 00746 * @param CRCPoly 0..0xFFFF 00747 * @retval None 00748 */ 00749 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) 00750 { 00751 MODIFY_REG(SPIx->CRCPR, SPI_CRCPR_CRCPOLY, CRCPoly); 00752 } 00753 00754 /** 00755 * @brief Get polynomial for CRC calculation 00756 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial 00757 * @param SPIx SPI Instance 00758 * @retval 0..0xFFFF 00759 */ 00760 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) 00761 { 00762 return (uint32_t)(READ_REG(SPIx->CRCPR)); 00763 } 00764 00765 /** 00766 * @brief Get Rx CRC 00767 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC 00768 * @param SPIx SPI Instance 00769 * @retval 0..0xFFFF 00770 */ 00771 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) 00772 { 00773 return (uint32_t)(READ_REG(SPIx->RXCRCR)); 00774 } 00775 00776 /** 00777 * @brief Get Tx CRC 00778 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC 00779 * @param SPIx SPI Instance 00780 * @retval 0..0xFFFF 00781 */ 00782 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) 00783 { 00784 return (uint32_t)(READ_REG(SPIx->TXCRCR)); 00785 } 00786 00787 /** 00788 * @} 00789 */ 00790 00791 /** @defgroup SPI_EF_NSS_Management NSS_Management 00792 * @{ 00793 */ 00794 00795 /** 00796 * @brief Set NSS Mode 00797 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. 00798 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n 00799 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode 00800 * @param SPIx SPI Instance 00801 * @param NSS This parameter can be one of the following values: 00802 * @arg @ref LL_SPI_NSS_SOFT 00803 * @arg @ref LL_SPI_NSS_HARD_INPUT 00804 * @arg @ref LL_SPI_NSS_HARD_OUTPUT 00805 * @retval None 00806 */ 00807 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) 00808 { 00809 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); 00810 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16))); 00811 } 00812 00813 /** 00814 * @brief Get NSS Mode 00815 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n 00816 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode 00817 * @param SPIx SPI Instance 00818 * @retval Returned value can be one of the following values: 00819 * @arg @ref LL_SPI_NSS_SOFT 00820 * @arg @ref LL_SPI_NSS_HARD_INPUT 00821 * @arg @ref LL_SPI_NSS_HARD_OUTPUT 00822 */ 00823 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) 00824 { 00825 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); 00826 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16); 00827 return (Ssm | Ssoe); 00828 } 00829 00830 /** 00831 * @brief Enable NSS pulse mgt 00832 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00833 * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt 00834 * @param SPIx SPI Instance 00835 * @retval None 00836 */ 00837 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) 00838 { 00839 SET_BIT(SPIx->CR2, SPI_CR2_NSSP); 00840 } 00841 00842 /** 00843 * @brief Disable NSS pulse mgt 00844 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00845 * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt 00846 * @param SPIx SPI Instance 00847 * @retval None 00848 */ 00849 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) 00850 { 00851 CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); 00852 } 00853 00854 /** 00855 * @brief Check if NSS pulse is enabled 00856 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00857 * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse 00858 * @param SPIx SPI Instance 00859 * @retval None 00860 */ 00861 __STATIC_INLINE void LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) 00862 { 00863 } 00864 00865 /** 00866 * @} 00867 */ 00868 00869 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management 00870 * @{ 00871 */ 00872 00873 /** 00874 * @brief Check if Rx buffer is not empty 00875 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE 00876 * @param SPIx SPI Instance 00877 * @retval State of bit (1 or 0). 00878 */ 00879 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) 00880 { 00881 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)); 00882 } 00883 00884 /** 00885 * @brief Check if Tx buffer is empty 00886 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE 00887 * @param SPIx SPI Instance 00888 * @retval State of bit (1 or 0). 00889 */ 00890 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) 00891 { 00892 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)); 00893 } 00894 00895 /** 00896 * @brief Get Underrun error flag 00897 * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR 00898 * @param SPIx SPI Instance 00899 * @retval State of bit (1 or 0). 00900 */ 00901 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx) 00902 { 00903 return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)); 00904 } 00905 00906 /** 00907 * @brief Get CRC error flag 00908 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR 00909 * @param SPIx SPI Instance 00910 * @retval State of bit (1 or 0). 00911 */ 00912 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) 00913 { 00914 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)); 00915 } 00916 00917 /** 00918 * @brief Get Mode fault error flag 00919 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF 00920 * @param SPIx SPI Instance 00921 * @retval State of bit (1 or 0). 00922 */ 00923 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) 00924 { 00925 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)); 00926 } 00927 00928 /** 00929 * @brief Get Overrun error flag 00930 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR 00931 * @param SPIx SPI Instance 00932 * @retval State of bit (1 or 0). 00933 */ 00934 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) 00935 { 00936 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)); 00937 } 00938 00939 /** 00940 * @brief Get Busy flag 00941 * @note The BSY flag is cleared under any one of the following conditions: 00942 * -When the SPI is correctly disabled 00943 * -When a fault is detected in Master mode (MODF bit set to 1) 00944 * -In Master mode, when it finishes a data transmission and no new data is ready to be 00945 * sent 00946 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between 00947 * each data transfer. 00948 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY 00949 * @param SPIx SPI Instance 00950 * @retval State of bit (1 or 0). 00951 */ 00952 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) 00953 { 00954 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)); 00955 } 00956 00957 /** 00958 * @brief Get Frame format error flag 00959 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE 00960 * @param SPIx SPI Instance 00961 * @retval State of bit (1 or 0). 00962 */ 00963 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) 00964 { 00965 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)); 00966 } 00967 00968 /** 00969 * @brief Get FIFO reception Level 00970 * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel 00971 * @param SPIx SPI Instance 00972 * @retval Returned value can be one of the following values: 00973 * @arg @ref LL_SPI_RX_FIFO_EMPTY 00974 * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL 00975 * @arg @ref LL_SPI_RX_FIFO_HALF_FULL 00976 * @arg @ref LL_SPI_RX_FIFO_FULL 00977 */ 00978 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) 00979 { 00980 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); 00981 } 00982 00983 /** 00984 * @brief Get FIFO Transmission Level 00985 * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel 00986 * @param SPIx SPI Instance 00987 * @retval Returned value can be one of the following values: 00988 * @arg @ref LL_SPI_TX_FIFO_EMPTY 00989 * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL 00990 * @arg @ref LL_SPI_TX_FIFO_HALF_FULL 00991 * @arg @ref LL_SPI_TX_FIFO_FULL 00992 */ 00993 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) 00994 { 00995 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); 00996 } 00997 00998 /** 00999 * @brief Clear Underrun error flag 01000 * @rmtoll SR UDR LL_SPI_ClearFlag_UDR 01001 * @param SPIx SPI Instance 01002 * @retval None 01003 */ 01004 __STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx) 01005 { 01006 __IO uint32_t tmpreg; 01007 tmpreg = SPIx->SR; 01008 (void) tmpreg; 01009 } 01010 01011 /** 01012 * @brief Clear CRC error flag 01013 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR 01014 * @param SPIx SPI Instance 01015 * @retval None 01016 */ 01017 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) 01018 { 01019 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); 01020 } 01021 01022 /** 01023 * @brief Clear Mode fault error flag 01024 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF 01025 * @param SPIx SPI Instance 01026 * @retval None 01027 */ 01028 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) 01029 { 01030 __IO uint32_t tmpreg; 01031 tmpreg = SPIx->SR; 01032 (void) tmpreg; 01033 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 01034 (void) tmpreg; 01035 } 01036 01037 /** 01038 * @brief Clear Overrun error flag 01039 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR 01040 * @param SPIx SPI Instance 01041 * @retval None 01042 */ 01043 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) 01044 { 01045 __IO uint32_t tmpreg; 01046 tmpreg = SPIx->DR; 01047 (void) tmpreg; 01048 tmpreg = SPIx->SR; 01049 (void) tmpreg; 01050 } 01051 01052 /** 01053 * @brief Clear Frame format error flag 01054 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE 01055 * @param SPIx SPI Instance 01056 * @retval None 01057 */ 01058 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) 01059 { 01060 __IO uint32_t tmpreg; 01061 tmpreg = SPIx->SR; 01062 (void) tmpreg; 01063 } 01064 01065 /** 01066 * @} 01067 */ 01068 01069 /** @defgroup SPI_LL_EF_IT_Management IT_Management 01070 * @{ 01071 */ 01072 01073 /** 01074 * @brief Enable Error IT 01075 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR,OVR, MODF in SPI mode, FRE at TI mode). 01076 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR 01077 * @param SPIx SPI Instance 01078 * @retval None 01079 */ 01080 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) 01081 { 01082 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); 01083 } 01084 01085 /** 01086 * @brief Enable Rx buffer not empty IT 01087 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE 01088 * @param SPIx SPI Instance 01089 * @retval None 01090 */ 01091 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) 01092 { 01093 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 01094 } 01095 01096 /** 01097 * @brief Enable Tx buffer empty IT 01098 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE 01099 * @param SPIx SPI Instance 01100 * @retval None 01101 */ 01102 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) 01103 { 01104 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); 01105 } 01106 01107 /** 01108 * @brief Disable Error IT 01109 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). 01110 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR 01111 * @param SPIx SPI Instance 01112 * @retval None 01113 */ 01114 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) 01115 { 01116 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); 01117 } 01118 01119 /** 01120 * @brief Disable Rx buffer not empty IT 01121 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE 01122 * @param SPIx SPI Instance 01123 * @retval None 01124 */ 01125 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) 01126 { 01127 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 01128 } 01129 01130 /** 01131 * @brief Disable Tx buffer empty IT 01132 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE 01133 * @param SPIx SPI Instance 01134 * @retval None 01135 */ 01136 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) 01137 { 01138 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); 01139 } 01140 01141 /** 01142 * @brief Check if ERR IT is enabled 01143 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR 01144 * @param SPIx SPI Instance 01145 * @retval State of bit (1 or 0). 01146 */ 01147 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) 01148 { 01149 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)); 01150 } 01151 01152 /** 01153 * @brief Check if RXNE IT is enabled 01154 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE 01155 * @param SPIx SPI Instance 01156 * @retval State of bit (1 or 0). 01157 */ 01158 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) 01159 { 01160 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)); 01161 } 01162 01163 /** 01164 * @brief Check if TXE IT is enabled 01165 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE 01166 * @param SPIx SPI Instance 01167 * @retval State of bit (1 or 0). 01168 */ 01169 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) 01170 { 01171 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)); 01172 } 01173 01174 /** 01175 * @} 01176 */ 01177 01178 /** @defgroup SPI_LL_EF_DMA_Management DMA_Management 01179 * @{ 01180 */ 01181 01182 /** 01183 * @brief Enable DMA Rx 01184 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX 01185 * @param SPIx SPI Instance 01186 * @retval None 01187 */ 01188 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) 01189 { 01190 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 01191 } 01192 01193 /** 01194 * @brief Disable DMA Rx 01195 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX 01196 * @param SPIx SPI Instance 01197 * @retval None 01198 */ 01199 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) 01200 { 01201 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 01202 } 01203 01204 /** 01205 * @brief Check if DMA Rx is enabled 01206 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX 01207 * @param SPIx SPI Instance 01208 * @retval State of bit (1 or 0). 01209 */ 01210 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) 01211 { 01212 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)); 01213 } 01214 01215 /** 01216 * @brief Enable DMA Tx 01217 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX 01218 * @param SPIx SPI Instance 01219 * @retval None 01220 */ 01221 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) 01222 { 01223 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 01224 } 01225 01226 /** 01227 * @brief Disable DMA Tx 01228 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX 01229 * @param SPIx SPI Instance 01230 * @retval None 01231 */ 01232 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) 01233 { 01234 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 01235 } 01236 01237 /** 01238 * @brief Check if DMA Tx is enabled 01239 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX 01240 * @param SPIx SPI Instance 01241 * @retval State of bit (1 or 0). 01242 */ 01243 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) 01244 { 01245 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)); 01246 } 01247 01248 /** 01249 * @brief Set parity of Last DMA reception 01250 * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX 01251 * @param SPIx SPI Instance 01252 * @param Parity This parameter can be one of the following values: 01253 * @arg @ref LL_SPI_DMA_PARITY_ODD 01254 * @arg @ref LL_SPI_DMA_PARITY_EVEN 01255 * @retval None 01256 */ 01257 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) 01258 { 01259 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << POSITION_VAL(SPI_CR2_LDMARX))); 01260 } 01261 01262 /** 01263 * @brief Get parity configuration for Last DMA reception 01264 * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX 01265 * @param SPIx SPI Instance 01266 * @retval Returned value can be one of the following values: 01267 * @arg @ref LL_SPI_DMA_PARITY_ODD 01268 * @arg @ref LL_SPI_DMA_PARITY_EVEN 01269 */ 01270 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) 01271 { 01272 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> POSITION_VAL(SPI_CR2_LDMARX)); 01273 } 01274 01275 /** 01276 * @brief Set parity of Last DMA transmission 01277 * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX 01278 * @param SPIx SPI Instance 01279 * @param Parity This parameter can be one of the following values: 01280 * @arg @ref LL_SPI_DMA_PARITY_ODD 01281 * @arg @ref LL_SPI_DMA_PARITY_EVEN 01282 * @retval None 01283 */ 01284 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) 01285 { 01286 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << POSITION_VAL(SPI_CR2_LDMATX))); 01287 } 01288 01289 /** 01290 * @brief Get parity configuration for Last DMA transmission 01291 * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX 01292 * @param SPIx SPI Instance 01293 * @retval Returned value can be one of the following values: 01294 * @arg @ref LL_SPI_DMA_PARITY_ODD 01295 * @arg @ref LL_SPI_DMA_PARITY_EVEN 01296 */ 01297 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) 01298 { 01299 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> POSITION_VAL(SPI_CR2_LDMATX)); 01300 } 01301 01302 /** 01303 * @brief Get the data register address used for DMA transfer 01304 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr 01305 * @param SPIx SPI Instance 01306 * @retval Address of data register 01307 */ 01308 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) 01309 { 01310 return (uint32_t)&(SPIx->DR); 01311 } 01312 01313 /** 01314 * @} 01315 */ 01316 01317 /** @defgroup SPI_LL_EF_DATA_Management DATA_Management 01318 * @{ 01319 */ 01320 01321 /** 01322 * @brief Read 8-Bits in the Data Register 01323 * @rmtoll DR DR LL_SPI_ReceiveData8 01324 * @param SPIx SPI Instance 01325 * @retval RxData 0..0xFF 01326 */ 01327 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) 01328 { 01329 return (uint8_t)(READ_REG(SPIx->DR)); 01330 } 01331 01332 /** 01333 * @brief Read 16-Bits in the Data Register 01334 * @rmtoll DR DR LL_SPI_ReceiveData16 01335 * @param SPIx SPI Instance 01336 * @retval RxData 0..0xFFFF 01337 */ 01338 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) 01339 { 01340 return (uint16_t)(READ_REG(SPIx->DR)); 01341 } 01342 01343 /** 01344 * @brief Write 8-Bits in the Data Register 01345 * @rmtoll DR DR LL_SPI_TransmitData8 01346 * @param SPIx SPI Instance 01347 * @param TxData 0..0xFF 01348 * @retval None 01349 */ 01350 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) 01351 { 01352 *((__IO uint8_t*)&SPIx->DR) = TxData; 01353 } 01354 01355 /** 01356 * @brief Write 16-Bits in the Data Register 01357 * @rmtoll DR DR LL_SPI_TransmitData16 01358 * @param SPIx SPI Instance 01359 * @param TxData 0..0xFFFF 01360 * @retval None 01361 */ 01362 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) 01363 { 01364 *((__IO uint16_t*)&SPIx->DR) = TxData; 01365 } 01366 01367 /** 01368 * @} 01369 */ 01370 01371 /** 01372 * @} 01373 */ 01374 01375 /** 01376 * @} 01377 */ 01378 01379 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */ 01380 01381 /** 01382 * @} 01383 */ 01384 01385 #ifdef __cplusplus 01386 } 01387 #endif 01388 01389 #endif /* __STM32L4xx_LL_SPI_H */ 01390 01391 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01392
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