Eric Lewiston
Hal Drivers for L4
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stm32l4xx_ll_pwr.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_pwr.h 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief Header file of PWR LL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_LL_PWR_H 00040 #define __STM32L4xx_LL_PWR_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx.h" 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined(PWR) 00054 00055 /** @defgroup PWR_LL PWR 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 00062 /* Private constants ---------------------------------------------------------*/ 00063 00064 /* Private macros ------------------------------------------------------------*/ 00065 00066 /* Exported types ------------------------------------------------------------*/ 00067 /* Exported constants --------------------------------------------------------*/ 00068 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants 00069 * @{ 00070 */ 00071 00072 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines 00073 * @brief Flags defines which can be used with LL_PWR_WriteReg function 00074 * @{ 00075 */ 00076 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF 00077 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF 00078 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5 00079 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4 00080 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 00081 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 00082 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 00083 /** 00084 * @} 00085 */ 00086 00087 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines 00088 * @brief Flags defines which can be used with LL_PWR_ReadReg function 00089 * @{ 00090 */ 00091 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI 00092 #define LL_PWR_SR1_SBF PWR_SR1_SBF 00093 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 00094 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 00095 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 00096 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 00097 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 00098 #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4 00099 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3 00100 #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2 00101 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1 00102 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO 00103 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF 00104 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF 00105 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS 00106 /** 00107 * @} 00108 */ 00109 00110 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE 00111 * @{ 00112 */ 00113 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) 00114 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) 00115 /** 00116 * @} 00117 */ 00118 00119 /** @defgroup PWR_LL_EC_MODE_STOP1_MAIN MODE STOP1 MAIN 00120 * @{ 00121 */ 00122 #define LL_PWR_MODE_STOP1_MAIN_REGU (PWR_CR1_LPMS_STOP1MR) 00123 #define LL_PWR_MODE_STOP1_LP_REGU (PWR_CR1_LPMS_STOP1LPR) 00124 #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2) 00125 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY) 00126 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN) 00127 /** 00128 * @} 00129 */ 00130 00131 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 PVM VDDUSB 1 00132 * @{ 00133 */ 00134 #if defined(USB_OTG_FS) 00135 #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */ 00136 #endif /* USB_OTG_FS */ 00137 #define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */ 00138 #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */ 00139 #define LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */ 00140 /** 00141 * @} 00142 */ 00143 00144 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL 00145 * @{ 00146 */ 00147 #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */ 00148 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */ 00149 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */ 00150 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */ 00151 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */ 00152 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */ 00153 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */ 00154 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */ 00155 /** 00156 * @} 00157 */ 00158 00159 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP 00160 * @{ 00161 */ 00162 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1) 00163 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) 00164 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) 00165 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4) 00166 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5) 00167 /** 00168 * @} 00169 */ 00170 00171 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR 00172 * @{ 00173 */ 00174 #define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000) 00175 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS) 00176 /** 00177 * @} 00178 */ 00179 00180 /** @defgroup PWR_LL_EC_GPIO GPIO 00181 * @{ 00182 */ 00183 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA))) 00184 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB))) 00185 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC))) 00186 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD))) 00187 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE))) 00188 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF))) 00189 #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG))) 00190 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH))) 00191 /** 00192 * @} 00193 */ 00194 00195 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT 00196 * @{ 00197 */ 00198 #define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001) 00199 #define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002) 00200 #define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004) 00201 #define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008) 00202 #define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010) 00203 #define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020) 00204 #define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040) 00205 #define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080) 00206 #define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100) 00207 #define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200) 00208 #define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400) 00209 #define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800) 00210 #define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000) 00211 #define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000) 00212 #define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000) 00213 #define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000) 00214 /** 00215 * @} 00216 */ 00217 00218 /** 00219 * @} 00220 */ 00221 00222 /* Exported macro ------------------------------------------------------------*/ 00223 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros 00224 * @{ 00225 */ 00226 00227 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros 00228 * @{ 00229 */ 00230 00231 /** 00232 * @brief Write a value in PWR register 00233 * @param __REG__ Register to be written 00234 * @param __VALUE__ Value to be written in the register 00235 * @retval None 00236 */ 00237 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) 00238 00239 /** 00240 * @brief Read a value in PWR register 00241 * @param __REG__ Register to be read 00242 * @retval Register value 00243 */ 00244 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) 00245 /** 00246 * @} 00247 */ 00248 00249 /** 00250 * @} 00251 */ 00252 00253 00254 /* Exported functions --------------------------------------------------------*/ 00255 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions 00256 * @{ 00257 */ 00258 00259 /** @defgroup PWR_LL_EF_Configuration Configuration 00260 * @{ 00261 */ 00262 00263 /** 00264 * @brief Switch the regulator from main mode to low-power mode 00265 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode 00266 * @retval None 00267 */ 00268 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) 00269 { 00270 SET_BIT(PWR->CR1, PWR_CR1_LPR); 00271 } 00272 00273 /** 00274 * @brief Switch the regulator from low-power mode to main mode 00275 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode 00276 * @retval None 00277 */ 00278 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) 00279 { 00280 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); 00281 } 00282 00283 /** 00284 * @brief Check if the regulator is in low-power mode 00285 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode 00286 * @retval State of bit (1 or 0). 00287 */ 00288 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) 00289 { 00290 return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)); 00291 } 00292 00293 /** 00294 * @brief Set the main internal regulator output voltage 00295 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling 00296 * @param VoltageScaling This parameter can be one of the following values: 00297 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 00298 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 00299 * @retval None 00300 */ 00301 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) 00302 { 00303 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); 00304 } 00305 00306 /** 00307 * @brief Get the main internal regulator output voltage 00308 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling 00309 * @retval Returned value can be one of the following values: 00310 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 00311 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 00312 */ 00313 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) 00314 { 00315 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); 00316 } 00317 00318 /** 00319 * @brief Enable access to the backup domain 00320 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess 00321 * @retval None 00322 */ 00323 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) 00324 { 00325 SET_BIT(PWR->CR1, PWR_CR1_DBP); 00326 } 00327 00328 /** 00329 * @brief Disable access to the backup domain 00330 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess 00331 * @retval None 00332 */ 00333 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) 00334 { 00335 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); 00336 } 00337 00338 /** 00339 * @brief Check if the backup domain is enabled 00340 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess 00341 * @retval State of bit (1 or 0). 00342 */ 00343 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) 00344 { 00345 return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)); 00346 } 00347 00348 /** 00349 * @brief Set Low-Power mode 00350 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode 00351 * @param LowPowerMode This parameter can be one of the following values: 00352 * @arg @ref LL_PWR_MODE_STOP1_MAIN_REGU 00353 * @arg @ref LL_PWR_MODE_STOP1_LP_REGU 00354 * @arg @ref LL_PWR_MODE_STOP2 00355 * @arg @ref LL_PWR_MODE_STANDBY 00356 * @arg @ref LL_PWR_MODE_SHUTDOWN 00357 * @retval None 00358 */ 00359 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) 00360 { 00361 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); 00362 } 00363 00364 /** 00365 * @brief Get Low-Power mode 00366 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode 00367 * @retval Returned value can be one of the following values: 00368 * @arg @ref LL_PWR_MODE_STOP1_MAIN_REGU 00369 * @arg @ref LL_PWR_MODE_STOP1_LP_REGU 00370 * @arg @ref LL_PWR_MODE_STOP2 00371 * @arg @ref LL_PWR_MODE_STANDBY 00372 * @arg @ref LL_PWR_MODE_SHUTDOWN 00373 */ 00374 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) 00375 { 00376 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); 00377 } 00378 00379 #if defined(USB_OTG_FS) 00380 /** 00381 * @brief Enable VDDUSB supply 00382 * @rmtoll CR2 USV LL_PWR_EnableVddUSB 00383 * @retval None 00384 */ 00385 __STATIC_INLINE void LL_PWR_EnableVddUSB(void) 00386 { 00387 SET_BIT(PWR->CR2, PWR_CR2_USV); 00388 } 00389 #endif /* USB_OTG_FS */ 00390 00391 #if defined(USB_OTG_FS) 00392 /** 00393 * @brief Disable VDDUSB supply 00394 * @rmtoll CR2 USV LL_PWR_DisableVddUSB 00395 * @retval None 00396 */ 00397 __STATIC_INLINE void LL_PWR_DisableVddUSB(void) 00398 { 00399 CLEAR_BIT(PWR->CR2, PWR_CR2_USV); 00400 } 00401 #endif /* USB_OTG_FS */ 00402 00403 #if defined(USB_OTG_FS) 00404 /** 00405 * @brief Check if VDDUSB supply is enabled 00406 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB 00407 * @retval State of bit (1 or 0). 00408 */ 00409 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) 00410 { 00411 return (READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)); 00412 } 00413 #endif /* USB_OTG_FS */ 00414 00415 /** 00416 * @brief Enable VDDIO2 supply 00417 * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2 00418 * @retval None 00419 */ 00420 __STATIC_INLINE void LL_PWR_EnableVddIO2(void) 00421 { 00422 SET_BIT(PWR->CR2, PWR_CR2_IOSV); 00423 } 00424 00425 /** 00426 * @brief Disable VDDIO2 supply 00427 * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2 00428 * @retval None 00429 */ 00430 __STATIC_INLINE void LL_PWR_DisableVddIO2(void) 00431 { 00432 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); 00433 } 00434 00435 /** 00436 * @brief Check if VDDIO2 supply is enabled 00437 * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2 00438 * @retval State of bit (1 or 0). 00439 */ 00440 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) 00441 { 00442 return (READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)); 00443 } 00444 00445 /** 00446 * @brief Enable the Power Voltage Monitoring on a peripheral 00447 * CR2 PVME1 LL_PWR_EnablePVM\n 00448 * CR2 PVME2 LL_PWR_EnablePVM\n 00449 * CR2 PVME3 LL_PWR_EnablePVM\n 00450 * CR2 PVME4 LL_PWR_EnablePVM 00451 * @param PeriphVoltage This parameter can be one of the following values: 00452 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) 00453 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V 00454 * @arg @ref LL_PWR_PVM_VDDA_1_62V 00455 * @arg @ref LL_PWR_PVM_VDDA_2_2V 00456 * (*) value not defined in all devices. 00457 * @retval None 00458 */ 00459 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) 00460 { 00461 SET_BIT(PWR->CR2, PeriphVoltage); 00462 } 00463 00464 /** 00465 * @brief Disable the Power Voltage Monitoring on a peripheral 00466 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n 00467 * CR2 PVME2 LL_PWR_DisablePVM\n 00468 * CR2 PVME3 LL_PWR_DisablePVM\n 00469 * CR2 PVME4 LL_PWR_DisablePVM 00470 * @param PeriphVoltage This parameter can be one of the following values: 00471 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) 00472 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V 00473 * @arg @ref LL_PWR_PVM_VDDA_1_62V 00474 * @arg @ref LL_PWR_PVM_VDDA_2_2V 00475 * (*) value not defined in all devices. 00476 * @retval None 00477 */ 00478 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) 00479 { 00480 CLEAR_BIT(PWR->CR2, PeriphVoltage); 00481 } 00482 00483 /** 00484 * @brief Check if Power Voltage Monitoring is enabled on a peripheral 00485 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n 00486 * CR2 PVME2 LL_PWR_IsEnabledPVM\n 00487 * CR2 PVME3 LL_PWR_IsEnabledPVM\n 00488 * CR2 PVME4 LL_PWR_IsEnabledPVM 00489 * @param PeriphVoltage This parameter can be one of the following values: 00490 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) 00491 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V 00492 * @arg @ref LL_PWR_PVM_VDDA_1_62V 00493 * @arg @ref LL_PWR_PVM_VDDA_2_2V 00494 * (*) value not defined in all devices. 00495 * @retval State of bit (1 or 0). 00496 */ 00497 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) 00498 { 00499 return (READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)); 00500 } 00501 00502 /** 00503 * @brief Configure the voltage threshold detected by the Power Voltage Detector 00504 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel 00505 * @param PVDLevel This parameter can be one of the following values: 00506 * @arg @ref LL_PWR_PVDLEVEL_0 00507 * @arg @ref LL_PWR_PVDLEVEL_1 00508 * @arg @ref LL_PWR_PVDLEVEL_2 00509 * @arg @ref LL_PWR_PVDLEVEL_3 00510 * @arg @ref LL_PWR_PVDLEVEL_4 00511 * @arg @ref LL_PWR_PVDLEVEL_5 00512 * @arg @ref LL_PWR_PVDLEVEL_6 00513 * @arg @ref LL_PWR_PVDLEVEL_7 00514 * @retval None 00515 */ 00516 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) 00517 { 00518 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel); 00519 } 00520 00521 /** 00522 * @brief Get the voltage threshold detection 00523 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel 00524 * @retval Returned value can be one of the following values: 00525 * @arg @ref LL_PWR_PVDLEVEL_0 00526 * @arg @ref LL_PWR_PVDLEVEL_1 00527 * @arg @ref LL_PWR_PVDLEVEL_2 00528 * @arg @ref LL_PWR_PVDLEVEL_3 00529 * @arg @ref LL_PWR_PVDLEVEL_4 00530 * @arg @ref LL_PWR_PVDLEVEL_5 00531 * @arg @ref LL_PWR_PVDLEVEL_6 00532 * @arg @ref LL_PWR_PVDLEVEL_7 00533 */ 00534 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) 00535 { 00536 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS)); 00537 } 00538 00539 /** 00540 * @brief Enable Power Voltage Detector 00541 * @rmtoll CR2 PVDE LL_PWR_EnablePVD 00542 * @retval None 00543 */ 00544 __STATIC_INLINE void LL_PWR_EnablePVD(void) 00545 { 00546 SET_BIT(PWR->CR2, PWR_CR2_PVDE); 00547 } 00548 00549 /** 00550 * @brief Disable Power Voltage Detector 00551 * @rmtoll CR2 PVDE LL_PWR_DisablePVD 00552 * @retval None 00553 */ 00554 __STATIC_INLINE void LL_PWR_DisablePVD(void) 00555 { 00556 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); 00557 } 00558 00559 /** 00560 * @brief Check if Power Voltage Detector is enabled 00561 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD 00562 * @retval State of bit (1 or 0). 00563 */ 00564 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) 00565 { 00566 return (READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)); 00567 } 00568 00569 /** 00570 * @brief Enable Internal Wake-up line 00571 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU 00572 * @retval None 00573 */ 00574 __STATIC_INLINE void LL_PWR_EnableInternWU(void) 00575 { 00576 SET_BIT(PWR->CR3, PWR_CR3_EIWF); 00577 } 00578 00579 /** 00580 * @brief Disable Internal Wake-up line 00581 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU 00582 * @retval None 00583 */ 00584 __STATIC_INLINE void LL_PWR_DisableInternWU(void) 00585 { 00586 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); 00587 } 00588 00589 /** 00590 * @brief Check if Internal Wake-up line is enabled 00591 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU 00592 * @retval State of bit (1 or 0). 00593 */ 00594 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) 00595 { 00596 return (READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)); 00597 } 00598 00599 /** 00600 * @brief Enable pull-up and pull-down configuration 00601 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg 00602 * @retval None 00603 */ 00604 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void) 00605 { 00606 SET_BIT(PWR->CR3, PWR_CR3_APC); 00607 } 00608 00609 /** 00610 * @brief Disable pull-up and pull-down configuration 00611 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg 00612 * @retval None 00613 */ 00614 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) 00615 { 00616 CLEAR_BIT(PWR->CR3, PWR_CR3_APC); 00617 } 00618 00619 /** 00620 * @brief Check if pull-up and pull-down configuration is enabled 00621 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg 00622 * @retval State of bit (1 or 0). 00623 */ 00624 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) 00625 { 00626 return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)); 00627 } 00628 00629 /** 00630 * @brief Enable SRAM2 content retention in Standby mode 00631 * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention 00632 * @retval None 00633 */ 00634 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void) 00635 { 00636 SET_BIT(PWR->CR3, PWR_CR3_RRS); 00637 } 00638 00639 /** 00640 * @brief Disable SRAM2 content retention in Standby mode 00641 * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention 00642 * @retval None 00643 */ 00644 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) 00645 { 00646 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); 00647 } 00648 00649 /** 00650 * @brief Check if SRAM2 content retention in Standby mode is enabled 00651 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention 00652 * @retval State of bit (1 or 0). 00653 */ 00654 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) 00655 { 00656 return (READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)); 00657 } 00658 00659 /** 00660 * @brief Enable the WakeUp PINx functionality 00661 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n 00662 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n 00663 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n 00664 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n 00665 * CR3 EWUP5 LL_PWR_EnableWakeUpPin 00666 * @param WakeUpPin This parameter can be one of the following values: 00667 * @arg @ref LL_PWR_WAKEUP_PIN1 00668 * @arg @ref LL_PWR_WAKEUP_PIN2 00669 * @arg @ref LL_PWR_WAKEUP_PIN3 00670 * @arg @ref LL_PWR_WAKEUP_PIN4 00671 * @arg @ref LL_PWR_WAKEUP_PIN5 00672 * @retval None 00673 */ 00674 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) 00675 { 00676 SET_BIT(PWR->CR3, WakeUpPin); 00677 } 00678 00679 /** 00680 * @brief Disable the WakeUp PINx functionality 00681 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n 00682 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n 00683 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n 00684 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n 00685 * CR3 EWUP5 LL_PWR_DisableWakeUpPin 00686 * @param WakeUpPin This parameter can be one of the following values: 00687 * @arg @ref LL_PWR_WAKEUP_PIN1 00688 * @arg @ref LL_PWR_WAKEUP_PIN2 00689 * @arg @ref LL_PWR_WAKEUP_PIN3 00690 * @arg @ref LL_PWR_WAKEUP_PIN4 00691 * @arg @ref LL_PWR_WAKEUP_PIN5 00692 * @retval None 00693 */ 00694 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) 00695 { 00696 CLEAR_BIT(PWR->CR3, WakeUpPin); 00697 } 00698 00699 /** 00700 * @brief Check if the WakeUp PINx functionality is enabled 00701 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n 00702 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n 00703 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n 00704 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n 00705 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin 00706 * @param WakeUpPin This parameter can be one of the following values: 00707 * @arg @ref LL_PWR_WAKEUP_PIN1 00708 * @arg @ref LL_PWR_WAKEUP_PIN2 00709 * @arg @ref LL_PWR_WAKEUP_PIN3 00710 * @arg @ref LL_PWR_WAKEUP_PIN4 00711 * @arg @ref LL_PWR_WAKEUP_PIN5 00712 * @retval State of bit (1 or 0). 00713 */ 00714 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) 00715 { 00716 return (READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)); 00717 } 00718 00719 /** 00720 * @brief Set the resistor impedance 00721 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor 00722 * @param Resistor This parameter can be one of the following values: 00723 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K 00724 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K 00725 * @retval None 00726 */ 00727 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) 00728 { 00729 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); 00730 } 00731 00732 /** 00733 * @brief Get the resistor impedance 00734 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor 00735 * @retval Returned value can be one of the following values: 00736 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K 00737 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K 00738 */ 00739 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) 00740 { 00741 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); 00742 } 00743 00744 /** 00745 * @brief Enable battery charging 00746 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging 00747 * @retval None 00748 */ 00749 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) 00750 { 00751 SET_BIT(PWR->CR4, PWR_CR4_VBE); 00752 } 00753 00754 /** 00755 * @brief Disable battery charging 00756 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging 00757 * @retval None 00758 */ 00759 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) 00760 { 00761 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); 00762 } 00763 00764 /** 00765 * @brief Check if battery charging is enabled 00766 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging 00767 * @retval State of bit (1 or 0). 00768 */ 00769 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) 00770 { 00771 return (READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)); 00772 } 00773 00774 /** 00775 * @brief Set the Wake-Up pin polarity low for the event detection 00776 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n 00777 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n 00778 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n 00779 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n 00780 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow 00781 * @param WakeUpPin This parameter can be one of the following values: 00782 * @arg @ref LL_PWR_WAKEUP_PIN1 00783 * @arg @ref LL_PWR_WAKEUP_PIN2 00784 * @arg @ref LL_PWR_WAKEUP_PIN3 00785 * @arg @ref LL_PWR_WAKEUP_PIN4 00786 * @arg @ref LL_PWR_WAKEUP_PIN5 00787 * @retval None 00788 */ 00789 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) 00790 { 00791 SET_BIT(PWR->CR4, WakeUpPin); 00792 } 00793 00794 /** 00795 * @brief Set the Wake-Up pin polarity high for the event detection 00796 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n 00797 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n 00798 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n 00799 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n 00800 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh 00801 * @param WakeUpPin This parameter can be one of the following values: 00802 * @arg @ref LL_PWR_WAKEUP_PIN1 00803 * @arg @ref LL_PWR_WAKEUP_PIN2 00804 * @arg @ref LL_PWR_WAKEUP_PIN3 00805 * @arg @ref LL_PWR_WAKEUP_PIN4 00806 * @arg @ref LL_PWR_WAKEUP_PIN5 00807 * @retval None 00808 */ 00809 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) 00810 { 00811 CLEAR_BIT(PWR->CR4, WakeUpPin); 00812 } 00813 00814 /** 00815 * @brief Get the Wake-Up pin polarity for the event detection 00816 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n 00817 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n 00818 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n 00819 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n 00820 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow 00821 * @param WakeUpPin This parameter can be one of the following values: 00822 * @arg @ref LL_PWR_WAKEUP_PIN1 00823 * @arg @ref LL_PWR_WAKEUP_PIN2 00824 * @arg @ref LL_PWR_WAKEUP_PIN3 00825 * @arg @ref LL_PWR_WAKEUP_PIN4 00826 * @arg @ref LL_PWR_WAKEUP_PIN5 00827 * @retval State of bit (1 or 0). 00828 */ 00829 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) 00830 { 00831 return (READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)); 00832 } 00833 00834 /** 00835 * @brief Enable GPIO pull-up state in Standby and Shutdown modes 00836 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n 00837 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n 00838 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n 00839 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n 00840 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n 00841 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n 00842 * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n 00843 * PUCRH PU0-1 LL_PWR_EnableGPIOPullUp 00844 * @param GPIO This parameter can be one of the following values: 00845 * @arg @ref LL_PWR_GPIO_A 00846 * @arg @ref LL_PWR_GPIO_B 00847 * @arg @ref LL_PWR_GPIO_C 00848 * @arg @ref LL_PWR_GPIO_D 00849 * @arg @ref LL_PWR_GPIO_E 00850 * @arg @ref LL_PWR_GPIO_F 00851 * @arg @ref LL_PWR_GPIO_G 00852 * @arg @ref LL_PWR_GPIO_H 00853 * @param GPIONumber This parameter can be one of the following values: 00854 * @arg @ref LL_PWR_GPIO_BIT_0 00855 * @arg @ref LL_PWR_GPIO_BIT_1 00856 * @arg @ref LL_PWR_GPIO_BIT_2 00857 * @arg @ref LL_PWR_GPIO_BIT_3 00858 * @arg @ref LL_PWR_GPIO_BIT_4 00859 * @arg @ref LL_PWR_GPIO_BIT_5 00860 * @arg @ref LL_PWR_GPIO_BIT_6 00861 * @arg @ref LL_PWR_GPIO_BIT_7 00862 * @arg @ref LL_PWR_GPIO_BIT_8 00863 * @arg @ref LL_PWR_GPIO_BIT_9 00864 * @arg @ref LL_PWR_GPIO_BIT_10 00865 * @arg @ref LL_PWR_GPIO_BIT_11 00866 * @arg @ref LL_PWR_GPIO_BIT_12 00867 * @arg @ref LL_PWR_GPIO_BIT_13 00868 * @arg @ref LL_PWR_GPIO_BIT_14 00869 * @arg @ref LL_PWR_GPIO_BIT_15 00870 * @retval None 00871 */ 00872 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 00873 { 00874 SET_BIT(*((uint32_t*)GPIO), GPIONumber); 00875 } 00876 00877 /** 00878 * @brief Disable GPIO pull-up state in Standby and Shutdown modes 00879 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n 00880 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n 00881 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n 00882 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n 00883 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n 00884 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n 00885 * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n 00886 * PUCRH PU0-1 LL_PWR_DisableGPIOPullUp 00887 * @param GPIO This parameter can be one of the following values: 00888 * @arg @ref LL_PWR_GPIO_A 00889 * @arg @ref LL_PWR_GPIO_B 00890 * @arg @ref LL_PWR_GPIO_C 00891 * @arg @ref LL_PWR_GPIO_D 00892 * @arg @ref LL_PWR_GPIO_E 00893 * @arg @ref LL_PWR_GPIO_F 00894 * @arg @ref LL_PWR_GPIO_G 00895 * @arg @ref LL_PWR_GPIO_H 00896 * @param GPIONumber This parameter can be one of the following values: 00897 * @arg @ref LL_PWR_GPIO_BIT_0 00898 * @arg @ref LL_PWR_GPIO_BIT_1 00899 * @arg @ref LL_PWR_GPIO_BIT_2 00900 * @arg @ref LL_PWR_GPIO_BIT_3 00901 * @arg @ref LL_PWR_GPIO_BIT_4 00902 * @arg @ref LL_PWR_GPIO_BIT_5 00903 * @arg @ref LL_PWR_GPIO_BIT_6 00904 * @arg @ref LL_PWR_GPIO_BIT_7 00905 * @arg @ref LL_PWR_GPIO_BIT_8 00906 * @arg @ref LL_PWR_GPIO_BIT_9 00907 * @arg @ref LL_PWR_GPIO_BIT_10 00908 * @arg @ref LL_PWR_GPIO_BIT_11 00909 * @arg @ref LL_PWR_GPIO_BIT_12 00910 * @arg @ref LL_PWR_GPIO_BIT_13 00911 * @arg @ref LL_PWR_GPIO_BIT_14 00912 * @arg @ref LL_PWR_GPIO_BIT_15 00913 * @retval None 00914 */ 00915 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 00916 { 00917 CLEAR_BIT(*((uint32_t*)GPIO), GPIONumber); 00918 } 00919 00920 /** 00921 * @brief Check if GPIO pull-up state is enabled 00922 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00923 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00924 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00925 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00926 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00927 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00928 * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00929 * PUCRH PU0-1 LL_PWR_IsEnabledGPIOPullUp 00930 * @param GPIO This parameter can be one of the following values: 00931 * @arg @ref LL_PWR_GPIO_A 00932 * @arg @ref LL_PWR_GPIO_B 00933 * @arg @ref LL_PWR_GPIO_C 00934 * @arg @ref LL_PWR_GPIO_D 00935 * @arg @ref LL_PWR_GPIO_E 00936 * @arg @ref LL_PWR_GPIO_F 00937 * @arg @ref LL_PWR_GPIO_G 00938 * @arg @ref LL_PWR_GPIO_H 00939 * @param GPIONumber This parameter can be one of the following values: 00940 * @arg @ref LL_PWR_GPIO_BIT_0 00941 * @arg @ref LL_PWR_GPIO_BIT_1 00942 * @arg @ref LL_PWR_GPIO_BIT_2 00943 * @arg @ref LL_PWR_GPIO_BIT_3 00944 * @arg @ref LL_PWR_GPIO_BIT_4 00945 * @arg @ref LL_PWR_GPIO_BIT_5 00946 * @arg @ref LL_PWR_GPIO_BIT_6 00947 * @arg @ref LL_PWR_GPIO_BIT_7 00948 * @arg @ref LL_PWR_GPIO_BIT_8 00949 * @arg @ref LL_PWR_GPIO_BIT_9 00950 * @arg @ref LL_PWR_GPIO_BIT_10 00951 * @arg @ref LL_PWR_GPIO_BIT_11 00952 * @arg @ref LL_PWR_GPIO_BIT_12 00953 * @arg @ref LL_PWR_GPIO_BIT_13 00954 * @arg @ref LL_PWR_GPIO_BIT_14 00955 * @arg @ref LL_PWR_GPIO_BIT_15 00956 * @retval State of bit (1 or 0). 00957 */ 00958 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 00959 { 00960 return(READ_BIT(*((uint32_t*)(GPIO)), GPIONumber) == (GPIONumber)); 00961 } 00962 00963 /** 00964 * @brief Enable GPIO pull-down state in Standby and Shutdown modes 00965 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n 00966 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n 00967 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n 00968 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n 00969 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n 00970 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n 00971 * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n 00972 * PDCRH PD0-1 LL_PWR_EnableGPIOPullDown 00973 * @param GPIO This parameter can be one of the following values: 00974 * @arg @ref LL_PWR_GPIO_A 00975 * @arg @ref LL_PWR_GPIO_B 00976 * @arg @ref LL_PWR_GPIO_C 00977 * @arg @ref LL_PWR_GPIO_D 00978 * @arg @ref LL_PWR_GPIO_E 00979 * @arg @ref LL_PWR_GPIO_F 00980 * @arg @ref LL_PWR_GPIO_G 00981 * @arg @ref LL_PWR_GPIO_H 00982 * @param GPIONumber This parameter can be one of the following values: 00983 * @arg @ref LL_PWR_GPIO_BIT_0 00984 * @arg @ref LL_PWR_GPIO_BIT_1 00985 * @arg @ref LL_PWR_GPIO_BIT_2 00986 * @arg @ref LL_PWR_GPIO_BIT_3 00987 * @arg @ref LL_PWR_GPIO_BIT_4 00988 * @arg @ref LL_PWR_GPIO_BIT_5 00989 * @arg @ref LL_PWR_GPIO_BIT_6 00990 * @arg @ref LL_PWR_GPIO_BIT_7 00991 * @arg @ref LL_PWR_GPIO_BIT_8 00992 * @arg @ref LL_PWR_GPIO_BIT_9 00993 * @arg @ref LL_PWR_GPIO_BIT_10 00994 * @arg @ref LL_PWR_GPIO_BIT_11 00995 * @arg @ref LL_PWR_GPIO_BIT_12 00996 * @arg @ref LL_PWR_GPIO_BIT_13 00997 * @arg @ref LL_PWR_GPIO_BIT_14 00998 * @arg @ref LL_PWR_GPIO_BIT_15 00999 * @retval None 01000 */ 01001 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 01002 { 01003 register uint32_t temp = (uint32_t)(GPIO) + 4; 01004 SET_BIT(*((uint32_t*)(temp)), GPIONumber); 01005 } 01006 01007 /** 01008 * @brief Disable GPIO pull-down state in Standby and Shutdown modes 01009 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n 01010 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n 01011 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n 01012 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n 01013 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n 01014 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n 01015 * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n 01016 * PDCRH PD0-1 LL_PWR_DisableGPIOPullDown 01017 * @param GPIO This parameter can be one of the following values: 01018 * @arg @ref LL_PWR_GPIO_A 01019 * @arg @ref LL_PWR_GPIO_B 01020 * @arg @ref LL_PWR_GPIO_C 01021 * @arg @ref LL_PWR_GPIO_D 01022 * @arg @ref LL_PWR_GPIO_E 01023 * @arg @ref LL_PWR_GPIO_F 01024 * @arg @ref LL_PWR_GPIO_G 01025 * @arg @ref LL_PWR_GPIO_H 01026 * @param GPIONumber This parameter can be one of the following values: 01027 * @arg @ref LL_PWR_GPIO_BIT_0 01028 * @arg @ref LL_PWR_GPIO_BIT_1 01029 * @arg @ref LL_PWR_GPIO_BIT_2 01030 * @arg @ref LL_PWR_GPIO_BIT_3 01031 * @arg @ref LL_PWR_GPIO_BIT_4 01032 * @arg @ref LL_PWR_GPIO_BIT_5 01033 * @arg @ref LL_PWR_GPIO_BIT_6 01034 * @arg @ref LL_PWR_GPIO_BIT_7 01035 * @arg @ref LL_PWR_GPIO_BIT_8 01036 * @arg @ref LL_PWR_GPIO_BIT_9 01037 * @arg @ref LL_PWR_GPIO_BIT_10 01038 * @arg @ref LL_PWR_GPIO_BIT_11 01039 * @arg @ref LL_PWR_GPIO_BIT_12 01040 * @arg @ref LL_PWR_GPIO_BIT_13 01041 * @arg @ref LL_PWR_GPIO_BIT_14 01042 * @arg @ref LL_PWR_GPIO_BIT_15 01043 * @retval None 01044 */ 01045 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 01046 { 01047 register uint32_t temp = (uint32_t)(GPIO) + 4; 01048 CLEAR_BIT(*((uint32_t*)(temp)), GPIONumber); 01049 } 01050 01051 /** 01052 * @brief Check if GPIO pull-down state is enabled 01053 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01054 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01055 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01056 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01057 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01058 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01059 * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01060 * PDCRH PD0-1 LL_PWR_IsEnabledGPIOPullDown 01061 * @param GPIO This parameter can be one of the following values: 01062 * @arg @ref LL_PWR_GPIO_A 01063 * @arg @ref LL_PWR_GPIO_B 01064 * @arg @ref LL_PWR_GPIO_C 01065 * @arg @ref LL_PWR_GPIO_D 01066 * @arg @ref LL_PWR_GPIO_E 01067 * @arg @ref LL_PWR_GPIO_F 01068 * @arg @ref LL_PWR_GPIO_G 01069 * @arg @ref LL_PWR_GPIO_H 01070 * @param GPIONumber This parameter can be one of the following values: 01071 * @arg @ref LL_PWR_GPIO_BIT_0 01072 * @arg @ref LL_PWR_GPIO_BIT_1 01073 * @arg @ref LL_PWR_GPIO_BIT_2 01074 * @arg @ref LL_PWR_GPIO_BIT_3 01075 * @arg @ref LL_PWR_GPIO_BIT_4 01076 * @arg @ref LL_PWR_GPIO_BIT_5 01077 * @arg @ref LL_PWR_GPIO_BIT_6 01078 * @arg @ref LL_PWR_GPIO_BIT_7 01079 * @arg @ref LL_PWR_GPIO_BIT_8 01080 * @arg @ref LL_PWR_GPIO_BIT_9 01081 * @arg @ref LL_PWR_GPIO_BIT_10 01082 * @arg @ref LL_PWR_GPIO_BIT_11 01083 * @arg @ref LL_PWR_GPIO_BIT_12 01084 * @arg @ref LL_PWR_GPIO_BIT_13 01085 * @arg @ref LL_PWR_GPIO_BIT_14 01086 * @arg @ref LL_PWR_GPIO_BIT_15 01087 * @retval State of bit (1 or 0). 01088 */ 01089 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 01090 { 01091 register uint32_t temp = (uint32_t)(GPIO) + 4; 01092 return(READ_BIT(*((uint32_t*)(temp)), GPIONumber) == (GPIONumber)); 01093 } 01094 01095 /** 01096 * @} 01097 */ 01098 01099 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management 01100 * @{ 01101 */ 01102 01103 /** 01104 * @brief Get Internal Wake-up line Flag 01105 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU 01106 * @retval State of bit (1 or 0). 01107 */ 01108 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) 01109 { 01110 return (READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)); 01111 } 01112 01113 /** 01114 * @brief Get Stand-By Flag 01115 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB 01116 * @retval State of bit (1 or 0). 01117 */ 01118 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) 01119 { 01120 return (READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)); 01121 } 01122 01123 /** 01124 * @brief Get Wake-up Flag 5 01125 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5 01126 * @retval State of bit (1 or 0). 01127 */ 01128 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) 01129 { 01130 return (READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)); 01131 } 01132 01133 /** 01134 * @brief Get Wake-up Flag 4 01135 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4 01136 * @retval State of bit (1 or 0). 01137 */ 01138 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) 01139 { 01140 return (READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)); 01141 } 01142 01143 /** 01144 * @brief Get Wake-up Flag 3 01145 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3 01146 * @retval State of bit (1 or 0). 01147 */ 01148 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) 01149 { 01150 return (READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)); 01151 } 01152 01153 /** 01154 * @brief Get Wake-up Flag 2 01155 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2 01156 * @retval State of bit (1 or 0). 01157 */ 01158 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) 01159 { 01160 return (READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)); 01161 } 01162 01163 /** 01164 * @brief Get Wake-up Flag 1 01165 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1 01166 * @retval State of bit (1 or 0). 01167 */ 01168 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) 01169 { 01170 return (READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)); 01171 } 01172 01173 /** 01174 * @brief Clear Stand-By Flag 01175 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB 01176 * @retval None 01177 */ 01178 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) 01179 { 01180 WRITE_REG(PWR->SCR, PWR_SCR_CSBF); 01181 } 01182 01183 /** 01184 * @brief Clear Wake-up Flags 01185 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU 01186 * @retval None 01187 */ 01188 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) 01189 { 01190 WRITE_REG(PWR->SCR, PWR_SCR_CWUF); 01191 } 01192 01193 /** 01194 * @brief Clear Wake-up Flag 5 01195 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5 01196 * @retval None 01197 */ 01198 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) 01199 { 01200 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); 01201 } 01202 01203 /** 01204 * @brief Clear Wake-up Flag 4 01205 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4 01206 * @retval None 01207 */ 01208 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) 01209 { 01210 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); 01211 } 01212 01213 /** 01214 * @brief Clear Wake-up Flag 3 01215 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3 01216 * @retval None 01217 */ 01218 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) 01219 { 01220 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); 01221 } 01222 01223 /** 01224 * @brief Clear Wake-up Flag 2 01225 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2 01226 * @retval None 01227 */ 01228 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) 01229 { 01230 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); 01231 } 01232 01233 /** 01234 * @brief Clear Wake-up Flag 1 01235 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1 01236 * @retval None 01237 */ 01238 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) 01239 { 01240 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); 01241 } 01242 01243 /** 01244 * @brief Indicate whether VDDA voltage is below or above PVM4 threshold 01245 * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4 01246 * @retval State of bit (1 or 0). 01247 */ 01248 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4 (void) 01249 { 01250 return (READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)); 01251 } 01252 01253 /** 01254 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold 01255 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3 01256 * @retval State of bit (1 or 0). 01257 */ 01258 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3 (void) 01259 { 01260 return (READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)); 01261 } 01262 01263 /** 01264 * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold 01265 * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2 01266 * @retval State of bit (1 or 0). 01267 */ 01268 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2 (void) 01269 { 01270 return (READ_BIT(PWR->SR2, PWR_SR2_PVMO2 ) == (PWR_SR2_PVMO2 )); 01271 } 01272 01273 #if defined(USB_OTG_FS) 01274 /** 01275 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold 01276 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1 01277 * @retval State of bit (1 or 0). 01278 */ 01279 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1 (void) 01280 { 01281 return (READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)); 01282 } 01283 #endif /* USB_OTG_FS */ 01284 01285 /** 01286 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold 01287 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO 01288 * @retval State of bit (1 or 0). 01289 */ 01290 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO (void) 01291 { 01292 return (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)); 01293 } 01294 01295 /** 01296 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level 01297 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOSF 01298 * @retval State of bit (1 or 0). 01299 */ 01300 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSF (void) 01301 { 01302 return (READ_BIT(PWR->SR2, PWR_SR2_VOSF ) == (PWR_SR2_VOSF )); 01303 } 01304 01305 /** 01306 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode 01307 * @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. 01308 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF 01309 * @retval State of bit (1 or 0). 01310 */ 01311 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) 01312 { 01313 return (READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)); 01314 } 01315 01316 /** 01317 * @brief Indicate whether or not the low-power regulator is ready 01318 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS 01319 * @retval State of bit (1 or 0). 01320 */ 01321 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void) 01322 { 01323 return (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)); 01324 } 01325 01326 /** 01327 * @} 01328 */ 01329 01330 01331 /** 01332 * @} 01333 */ 01334 01335 /** 01336 * @} 01337 */ 01338 01339 #endif /* defined(PWR) */ 01340 01341 /** 01342 * @} 01343 */ 01344 01345 #ifdef __cplusplus 01346 } 01347 #endif 01348 01349 #endif /* __STM32L4xx_LL_PWR_H */ 01350 01351 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01352
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