Eric Lewiston
Hal Drivers for L4
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stm32l4xx_hal_dfsdm.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_dfsdm.h 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief Header file of DFSDM HAL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_HAL_DFSDM_H 00040 #define __STM32L4xx_HAL_DFSDM_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx_hal_def.h" 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup DFSDM 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types 00059 * @{ 00060 */ 00061 00062 /** 00063 * @brief HAL DFSDM Channel states definition 00064 */ 00065 typedef enum 00066 { 00067 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00, /*!< DFSDM channel not initialized */ 00068 HAL_DFSDM_CHANNEL_STATE_READY = 0x01, /*!< DFSDM channel initialized and ready for use */ 00069 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFF /*!< DFSDM channel state error */ 00070 }HAL_DFSDM_Channel_StateTypeDef; 00071 00072 /** 00073 * @brief DFSDM channel output clock structure definition 00074 */ 00075 typedef struct 00076 { 00077 FunctionalState Activation; /*!< Output clock enable/disable */ 00078 uint32_t Selection; /*!< Output clock is system clock or audio clock. 00079 This parameter can be a value of @ref DFSDM_Channel_OuputClock */ 00080 uint32_t Divider; /*!< Output clock divider. 00081 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ 00082 }DFSDM_Channel_OutputClockTypeDef; 00083 00084 /** 00085 * @brief DFSDM channel input structure definition 00086 */ 00087 typedef struct 00088 { 00089 uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. 00090 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ 00091 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. 00092 This parameter can be a value of @ref DFSDM_Channel_DataPacking */ 00093 uint32_t Pins; /*!< Input pins are taken from same or following channel. 00094 This parameter can be a value of @ref DFSDM_Channel_InputPins */ 00095 }DFSDM_Channel_InputTypeDef; 00096 00097 /** 00098 * @brief DFSDM channel serial interface structure definition 00099 */ 00100 typedef struct 00101 { 00102 uint32_t Type; /*!< SPI or Manchester modes. 00103 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ 00104 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). 00105 This parameter can be a value of @ref DFSDM_Channel_SpiClock */ 00106 }DFSDM_Channel_SerialInterfaceTypeDef; 00107 00108 /** 00109 * @brief DFSDM channel analog watchdog structure definition 00110 */ 00111 typedef struct 00112 { 00113 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. 00114 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ 00115 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. 00116 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 00117 }DFSDM_Channel_AwdTypeDef; 00118 00119 /** 00120 * @brief DFSDM channel init structure definition 00121 */ 00122 typedef struct 00123 { 00124 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ 00125 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ 00126 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ 00127 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ 00128 int32_t Offset; /*!< DFSDM channel offset. 00129 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 00130 uint32_t RightBitShift; /*!< DFSDM channel right bit shift. 00131 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 00132 }DFSDM_Channel_InitTypeDef; 00133 00134 /** 00135 * @brief DFSDM channel handle structure definition 00136 */ 00137 typedef struct 00138 { 00139 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ 00140 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ 00141 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ 00142 }DFSDM_Channel_HandleTypeDef; 00143 00144 /** 00145 * @brief HAL DFSDM Filter states definition 00146 */ 00147 typedef enum 00148 { 00149 HAL_DFSDM_FILTER_STATE_RESET = 0x00, /*!< DFSDM filter not initialized */ 00150 HAL_DFSDM_FILTER_STATE_READY = 0x01, /*!< DFSDM filter initialized and ready for use */ 00151 HAL_DFSDM_FILTER_STATE_REG = 0x02, /*!< DFSDM filter regular conversion in progress */ 00152 HAL_DFSDM_FILTER_STATE_INJ = 0x03, /*!< DFSDM filter injected conversion in progress */ 00153 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04, /*!< DFSDM filter regular and injected conversions in progress */ 00154 HAL_DFSDM_FILTER_STATE_ERROR = 0xFF /*!< DFSDM filter state error */ 00155 }HAL_DFSDM_Filter_StateTypeDef; 00156 00157 /** 00158 * @brief DFSDM filter regular conversion parameters structure definition 00159 */ 00160 typedef struct 00161 { 00162 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. 00163 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 00164 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ 00165 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ 00166 }DFSDM_Filter_RegularParamTypeDef; 00167 00168 /** 00169 * @brief DFSDM filter injected conversion parameters structure definition 00170 */ 00171 typedef struct 00172 { 00173 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. 00174 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 00175 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ 00176 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ 00177 uint32_t ExtTrigger; /*!< External trigger. 00178 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ 00179 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. 00180 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ 00181 }DFSDM_Filter_InjectedParamTypeDef; 00182 00183 /** 00184 * @brief DFSDM filter parameters structure definition 00185 */ 00186 typedef struct 00187 { 00188 uint32_t SincOrder; /*!< Sinc filter order. 00189 This parameter can be a value of @ref DFSDM_Filter_SincOrder */ 00190 uint32_t Oversampling; /*!< Filter oversampling ratio. 00191 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ 00192 uint32_t IntOversampling; /*!< Integrator oversampling ratio. 00193 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ 00194 }DFSDM_Filter_FilterParamTypeDef; 00195 00196 /** 00197 * @brief DFSDM filter init structure definition 00198 */ 00199 typedef struct 00200 { 00201 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ 00202 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ 00203 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ 00204 }DFSDM_Filter_InitTypeDef; 00205 00206 /** 00207 * @brief DFSDM filter handle structure definition 00208 */ 00209 typedef struct 00210 { 00211 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ 00212 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ 00213 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ 00214 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ 00215 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ 00216 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ 00217 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ 00218 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ 00219 FunctionalState InjectedScanMode; /*!< Injected scanning mode */ 00220 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ 00221 uint32_t InjConvRemaining; /*!< Injected conversions remaining */ 00222 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ 00223 uint32_t ErrorCode; /*!< DFSDM filter error code */ 00224 }DFSDM_Filter_HandleTypeDef; 00225 00226 /** 00227 * @brief DFSDM filter analog watchdog parameters structure definition 00228 */ 00229 typedef struct 00230 { 00231 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. 00232 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ 00233 uint32_t Channel; /*!< Analog watchdog channel selection. 00234 This parameter can be a values combination of @ref DFSDM_Channel_Selection */ 00235 int32_t HighThreshold; /*!< High threshold for the analog watchdog. 00236 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 00237 int32_t LowThreshold; /*!< Low threshold for the analog watchdog. 00238 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 00239 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. 00240 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 00241 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. 00242 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 00243 }DFSDM_Filter_AwdParamTypeDef; 00244 00245 /** 00246 * @} 00247 */ 00248 /* End of exported types -----------------------------------------------------*/ 00249 00250 /* Exported constants --------------------------------------------------------*/ 00251 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants 00252 * @{ 00253 */ 00254 00255 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection 00256 * @{ 00257 */ 00258 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000) /*!< Source for ouput clock is system clock */ 00259 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ 00260 /** 00261 * @} 00262 */ 00263 00264 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer 00265 * @{ 00266 */ 00267 #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000) /*!< Data are taken from external inputs */ 00268 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ 00269 /** 00270 * @} 00271 */ 00272 00273 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing 00274 * @{ 00275 */ 00276 #define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000) /*!< Standard data packing mode */ 00277 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ 00278 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ 00279 /** 00280 * @} 00281 */ 00282 00283 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins 00284 * @{ 00285 */ 00286 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000) /*!< Input from pins on same channel */ 00287 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ 00288 /** 00289 * @} 00290 */ 00291 00292 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type 00293 * @{ 00294 */ 00295 #define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000) /*!< SPI with rising edge */ 00296 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ 00297 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ 00298 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ 00299 /** 00300 * @} 00301 */ 00302 00303 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection 00304 * @{ 00305 */ 00306 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000) /*!< External SPI clock */ 00307 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ 00308 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ 00309 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ 00310 /** 00311 * @} 00312 */ 00313 00314 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order 00315 * @{ 00316 */ 00317 #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000) /*!< FastSinc filter type */ 00318 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_AWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ 00319 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_AWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ 00320 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_AWSCDR_AWFORD /*!< Sinc 3 filter type */ 00321 /** 00322 * @} 00323 */ 00324 00325 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger 00326 * @{ 00327 */ 00328 #define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000) /*!< Software trigger */ 00329 #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001) /*!< Synchronous with DFSDM0 */ 00330 #define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002) /*!< External trigger (only for injected conversion) */ 00331 /** 00332 * @} 00333 */ 00334 00335 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger 00336 * @{ 00337 */ 00338 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000) /*!< For DFSDM 0, 1, 2 and 3 */ 00339 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_CR1_JEXTSEL_0 /*!< For DFSDM 0, 1, 2 and 3 */ 00340 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_CR1_JEXTSEL_1 /*!< For DFSDM 0, 1, 2 and 3 */ 00341 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_CR1_JEXTSEL_0 | DFSDM_CR1_JEXTSEL_1) /*!< For DFSDM 0, 1 and 2 */ 00342 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_CR1_JEXTSEL_0 | DFSDM_CR1_JEXTSEL_1) /*!< For DFSDM 3 */ 00343 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_CR1_JEXTSEL_2 /*!< For DFSDM 0, 1 and 2 */ 00344 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_CR1_JEXTSEL_2 /*!< For DFSDM 3 */ 00345 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_CR1_JEXTSEL_0 | DFSDM_CR1_JEXTSEL_2) /*!< For DFSDM 0 and 1 */ 00346 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_CR1_JEXTSEL_0 | DFSDM_CR1_JEXTSEL_2) /*!< For DFSDM 2 and 3 */ 00347 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_CR1_JEXTSEL_1 | DFSDM_CR1_JEXTSEL_2) /*!< For DFSDM 0, 1, 2 and 3 */ 00348 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_CR1_JEXTSEL /*!< For DFSDM 0, 1, 2 and 3 */ 00349 /** 00350 * @} 00351 */ 00352 00353 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge 00354 * @{ 00355 */ 00356 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_CR1_JEXTEN_0 /*!< External rising edge */ 00357 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_CR1_JEXTEN_1 /*!< External falling edge */ 00358 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_CR1_JEXTEN /*!< External rising and falling edges */ 00359 /** 00360 * @} 00361 */ 00362 00363 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order 00364 * @{ 00365 */ 00366 #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000) /*!< FastSinc filter type */ 00367 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FCR_FORD_0 /*!< Sinc 1 filter type */ 00368 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FCR_FORD_1 /*!< Sinc 2 filter type */ 00369 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FCR_FORD_0 | DFSDM_FCR_FORD_1) /*!< Sinc 3 filter type */ 00370 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FCR_FORD_2 /*!< Sinc 4 filter type */ 00371 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FCR_FORD_0 | DFSDM_FCR_FORD_2) /*!< Sinc 5 filter type */ 00372 /** 00373 * @} 00374 */ 00375 00376 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source 00377 * @{ 00378 */ 00379 #define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000) /*!< From digital filter */ 00380 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_CR1_AWFSEL /*!< From analog watchdog channel */ 00381 /** 00382 * @} 00383 */ 00384 00385 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code 00386 * @{ 00387 */ 00388 #define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ 00389 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001) /*!< Overrun occurs during regular conversion */ 00390 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002) /*!< Overrun occurs during injected conversion */ 00391 #define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003) /*!< DMA error occurs */ 00392 /** 00393 * @} 00394 */ 00395 00396 /** @defgroup DFSDM_BreakSignals DFSDM break signals 00397 * @{ 00398 */ 00399 #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000) /*!< No break signal */ 00400 #define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001) /*!< Break signal 0 */ 00401 #define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002) /*!< Break signal 1 */ 00402 #define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004) /*!< Break signal 2 */ 00403 #define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008) /*!< Break signal 3 */ 00404 /** 00405 * @} 00406 */ 00407 00408 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection 00409 * @{ 00410 */ 00411 /* DFSDM Channels ------------------------------------------------------------*/ 00412 /* The DFSDM channels are defined as follows: 00413 - in 16-bit LSB the channel mask is set 00414 - in 16-bit MSB the channel number is set 00415 e.g. for channel 5 definition: 00416 - the channel mask is 0x00000020 (bit 5 is set) 00417 - the channel number 5 is 0x00050000 00418 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ 00419 #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001) 00420 #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002) 00421 #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004) 00422 #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008) 00423 #define DFSDM_CHANNEL_4 ((uint32_t)0x00040010) 00424 #define DFSDM_CHANNEL_5 ((uint32_t)0x00050020) 00425 #define DFSDM_CHANNEL_6 ((uint32_t)0x00060040) 00426 #define DFSDM_CHANNEL_7 ((uint32_t)0x00070080) 00427 /** 00428 * @} 00429 */ 00430 00431 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode 00432 * @{ 00433 */ 00434 #define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000) /*!< Conversion are not continuous */ 00435 #define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001) /*!< Conversion are continuous */ 00436 /** 00437 * @} 00438 */ 00439 00440 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold 00441 * @{ 00442 */ 00443 #define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000) /*!< Analog watchdog high threshold */ 00444 #define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001) /*!< Analog watchdog low threshold */ 00445 /** 00446 * @} 00447 */ 00448 00449 /** 00450 * @} 00451 */ 00452 /* End of exported constants -------------------------------------------------*/ 00453 00454 /* Exported macros -----------------------------------------------------------*/ 00455 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros 00456 * @{ 00457 */ 00458 00459 /** @brief Reset DFSDM channel handle state. 00460 * @param __HANDLE__: DFSDM channel handle. 00461 * @retval None 00462 */ 00463 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) 00464 00465 /** @brief Reset DFSDM filter handle state. 00466 * @param __HANDLE__: DFSDM filter handle. 00467 * @retval None 00468 */ 00469 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) 00470 00471 /** 00472 * @} 00473 */ 00474 /* End of exported macros ----------------------------------------------------*/ 00475 00476 /* Exported functions --------------------------------------------------------*/ 00477 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions 00478 * @{ 00479 */ 00480 00481 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions 00482 * @{ 00483 */ 00484 /* Channel initialization and de-initialization functions *********************/ 00485 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00486 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00487 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00488 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00489 /** 00490 * @} 00491 */ 00492 00493 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions 00494 * @{ 00495 */ 00496 /* Channel operation functions ************************************************/ 00497 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00498 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00499 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00500 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00501 00502 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 00503 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 00504 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00505 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00506 00507 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00508 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); 00509 00510 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 00511 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 00512 00513 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00514 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00515 /** 00516 * @} 00517 */ 00518 00519 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function 00520 * @{ 00521 */ 00522 /* Channel state function *****************************************************/ 00523 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00524 /** 00525 * @} 00526 */ 00527 00528 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions 00529 * @{ 00530 */ 00531 /* Filter initialization and de-initialization functions *********************/ 00532 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00533 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00534 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00535 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00536 /** 00537 * @} 00538 */ 00539 00540 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions 00541 * @{ 00542 */ 00543 /* Filter control functions *********************/ 00544 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00545 uint32_t Channel, 00546 uint32_t ContinuousMode); 00547 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00548 uint32_t Channel); 00549 /** 00550 * @} 00551 */ 00552 00553 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions 00554 * @{ 00555 */ 00556 /* Filter operation functions *********************/ 00557 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00558 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00559 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 00560 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 00561 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00562 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00563 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00564 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00565 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00566 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 00567 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 00568 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00569 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00570 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00571 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00572 DFSDM_Filter_AwdParamTypeDef* awdParam); 00573 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00574 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); 00575 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00576 00577 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 00578 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 00579 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 00580 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 00581 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00582 00583 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00584 00585 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 00586 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 00587 00588 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00589 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00590 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00591 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00592 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 00593 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00594 /** 00595 * @} 00596 */ 00597 00598 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions 00599 * @{ 00600 */ 00601 /* Filter state functions *****************************************************/ 00602 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00603 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00604 /** 00605 * @} 00606 */ 00607 00608 /** 00609 * @} 00610 */ 00611 /* End of exported functions -------------------------------------------------*/ 00612 00613 /* Private macros ------------------------------------------------------------*/ 00614 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros 00615 * @{ 00616 */ 00617 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ 00618 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) 00619 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) 00620 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 00621 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 00622 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ 00623 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ 00624 ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) 00625 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ 00626 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) 00627 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ 00628 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ 00629 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ 00630 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) 00631 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ 00632 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ 00633 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ 00634 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) 00635 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ 00636 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ 00637 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ 00638 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) 00639 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32)) 00640 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 00641 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F) 00642 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF) 00643 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 00644 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) 00645 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 00646 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ 00647 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) 00648 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 00649 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 00650 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 00651 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ 00652 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 00653 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 00654 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 00655 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 00656 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 00657 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 00658 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 00659 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ 00660 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ 00661 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) 00662 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ 00663 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ 00664 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ 00665 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ 00666 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ 00667 ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) 00668 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024)) 00669 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256)) 00670 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ 00671 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) 00672 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 00673 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xF) 00674 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 00675 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 00676 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 00677 ((CHANNEL) == DFSDM_CHANNEL_3) || \ 00678 ((CHANNEL) == DFSDM_CHANNEL_4) || \ 00679 ((CHANNEL) == DFSDM_CHANNEL_5) || \ 00680 ((CHANNEL) == DFSDM_CHANNEL_6) || \ 00681 ((CHANNEL) == DFSDM_CHANNEL_7)) 00682 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FF)) 00683 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ 00684 ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) 00685 /** 00686 * @} 00687 */ 00688 /* End of private macros -----------------------------------------------------*/ 00689 00690 /** 00691 * @} 00692 */ 00693 00694 /** 00695 * @} 00696 */ 00697 00698 #ifdef __cplusplus 00699 } 00700 #endif 00701 00702 #endif /* __STM32L4xx_HAL_DFSDM_H */ 00703 00704 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 00705
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