RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.
Dependents: GR-PEACH_Azure_Speech ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample ... more
Fork of R_BSP by
dma_if.h
00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer* 00021 * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 00024 /**************************************************************************//** 00025 * @file dma_if.h 00026 * $Rev: 1318 $ 00027 * $Date:: 2014-12-04 10:45:12 +0900#$ 00028 * @brief DMA Driver interface headers 00029 ******************************************************************************/ 00030 00031 /***************************************************************************** 00032 * History : DD.MM.YYYY Version Description 00033 * : 15.01.2013 1.00 First Release 00034 ******************************************************************************/ 00035 00036 #ifndef DMA_IF_H 00037 #define DMA_IF_H 00038 00039 /****************************************************************************** 00040 Includes <System Includes> , "Project Includes" 00041 ******************************************************************************/ 00042 00043 #include "cmsis_os.h" 00044 #include "r_errno.h" 00045 #include "r_typedefs.h" 00046 #include "ioif_aio.h" 00047 00048 00049 #ifdef __cplusplus 00050 extern "C" 00051 { 00052 #endif /* __cplusplus */ 00053 00054 00055 /************************************************************************* 00056 User Includes 00057 *************************************************************************/ 00058 00059 /************************************************************************* 00060 Defines 00061 *************************************************************************/ 00062 00063 /* for searching free channel */ 00064 #define DMA_ALLOC_CH (-1) 00065 00066 /************************************************************************* 00067 Enumerated Types 00068 *************************************************************************/ 00069 00070 /* Number od DMA channel */ 00071 typedef enum 00072 { 00073 DMA_CH_0 = 0, 00074 DMA_CH_1 = 1, 00075 DMA_CH_2 = 2, 00076 DMA_CH_3 = 3, 00077 DMA_CH_4 = 4, 00078 DMA_CH_5 = 5, 00079 DMA_CH_6 = 6, 00080 DMA_CH_7 = 7, 00081 DMA_CH_8 = 8, 00082 DMA_CH_9 = 9, 00083 DMA_CH_10 = 10, 00084 DMA_CH_11 = 11, 00085 DMA_CH_12 = 12, 00086 DMA_CH_13 = 13, 00087 DMA_CH_14 = 14, 00088 DMA_CH_15 = 15, 00089 DMA_CH_NUM = 16 /* Number of DMA channel */ 00090 } dma_ch_num_t; 00091 00092 /* Unit Size of DMA transfer */ 00093 typedef enum 00094 { 00095 DMA_UNIT_MIN =(-1), 00096 DMA_UNIT_1 = 0, /* Unit Size of DMA transfer = 1byte */ 00097 DMA_UNIT_2 = 1, /* Unit Size of DMA transfer = 2byte */ 00098 DMA_UNIT_4 = 2, /* Unit Size of DMA transfer = 4byte */ 00099 DMA_UNIT_8 = 3, /* Unit Size of DMA transfer = 8byte */ 00100 DMA_UNIT_16 = 4, /* Unit Size of DMA transfer = 16byte */ 00101 DMA_UNIT_32 = 5, /* Unit Size of DMA transfer = 32byte */ 00102 DMA_UNIT_64 = 6, /* Unit Size of DMA transfer = 64byte */ 00103 DMA_UNIT_128 = 7, /* Unit Size of DMA transfer = 128byte */ 00104 DMA_UNIT_MAX = 8 00105 } dma_unit_size_t; 00106 00107 /* DMA transfer resource */ 00108 typedef enum 00109 { 00110 DMA_RS_OSTIM0 = 0x023, /* OS Timer ch0 */ 00111 DMA_RS_OSTIM1 = 0x027, /* OS Timer ch1 */ 00112 DMA_RS_TGI0A = 0x043, /* Multi Function Timer Pulse Unit2 ch0 */ 00113 DMA_RS_TGI1A = 0x047, /* Multi Function Timer Pulse Unit2 ch1 */ 00114 DMA_RS_TGI2A = 0x04B, /* Multi Function Timer Pulse Unit2 ch2 */ 00115 DMA_RS_TGI3A = 0x04F, /* Multi Function Timer Pulse Unit2 ch3 */ 00116 DMA_RS_TGI4A = 0x053, /* Multi Function Timer Pulse Unit2 ch4 */ 00117 DMA_RS_TXI0 = 0x061, /* FIFO Serial Communication Interface ch0 (TX) */ 00118 DMA_RS_RXI0 = 0x062, /* FIFO Serial Communication Interface ch0 (RX) */ 00119 DMA_RS_TXI1 = 0x065, /* FIFO Serial Communication Interface ch1 (TX) */ 00120 DMA_RS_RXI1 = 0x066, /* FIFO Serial Communication Interface ch1 (RX) */ 00121 DMA_RS_TXI2 = 0x069, /* FIFO Serial Communication Interface ch2 (TX) */ 00122 DMA_RS_RXI2 = 0x06A, /* FIFO Serial Communication Interface ch2 (RX) */ 00123 DMA_RS_TXI3 = 0x06D, /* FIFO Serial Communication Interface ch3 (TX) */ 00124 DMA_RS_RXI3 = 0x06E, /* FIFO Serial Communication Interface ch3 (RX) */ 00125 DMA_RS_TXI4 = 0x071, /* FIFO Serial Communication Interface ch4 (TX) */ 00126 DMA_RS_RXI4 = 0x072, /* FIFO Serial Communication Interface ch4 (RX) */ 00127 DMA_RS_TXI5 = 0x075, /* FIFO Serial Communication Interface ch5 (TX) */ 00128 DMA_RS_RXI5 = 0x076, /* FIFO Serial Communication Interface ch5 (RX) */ 00129 DMA_RS_TXI6 = 0x079, /* FIFO Serial Communication Interface ch6 (TX) */ 00130 DMA_RS_RXI6 = 0x07A, /* FIFO Serial Communication Interface ch6 (RX) */ 00131 DMA_RS_TXI7 = 0x07D, /* FIFO Serial Communication Interface ch7 (TX) */ 00132 DMA_RS_RXI7 = 0x07E, /* FIFO Serial Communication Interface ch7 (RX) */ 00133 DMA_RS_USB0_DMA0 = 0x083, /* USB Module0 ch0 */ 00134 DMA_RS_USB0_DMA1 = 0x087, /* USB Module0 ch1 */ 00135 DMA_RS_USB1_DMA0 = 0x08B, /* USB Module1 ch0 */ 00136 DMA_RS_USB1_DMA1 = 0x08F, /* USB Module1 ch1 */ 00137 DMA_RS_ADEND = 0x093, /* A/D Converter */ 00138 DMA_RS_IEBBTD = 0x0A3, /* IEBus Controller (Data interrupt) */ 00139 DMA_RS_IEBBTV = 0x0A7, /* IEBus Controller (Vector interrupt) */ 00140 DMA_RS_IREADY = 0x0AB, /* CD-Rom Decoder */ 00141 DMA_RS_FLDT = 0x0B3, /* NAND Memory Controller (Data) */ 00142 DMA_RS_SDHI_0T = 0x0C1, /* SD Host Interface0 (TX) */ 00143 DMA_RS_SDHI_0R = 0x0C2, /* SD Host Interface0 (RX) */ 00144 DMA_RS_SDHI_1T = 0x0C5, /* SD Host Interface1 (RX) */ 00145 DMA_RS_SDHI_1R = 0x0C6, /* SD Host Interface1 (TX) */ 00146 DMA_RS_MMCT = 0x0C9, /* MMC Host Interface (TX) */ 00147 DMA_RS_MMCR = 0x0CA, /* MMC Host Interface (RX) */ 00148 DMA_RS_SSITXI0 = 0x0E1, /* SSIF0 (TX) */ 00149 DMA_RS_SSIRXI0 = 0x0E2, /* SSIF0 (RX) */ 00150 DMA_RS_SSITXI1 = 0x0E5, /* SSIF1 (TX) */ 00151 DMA_RS_SSIRXI1 = 0x0E6, /* SSIF1 (RX) */ 00152 DMA_RS_SSIRTI2 = 0x0EB, /* SSIF2 (TX) */ 00153 DMA_RS_SSITXI3 = 0x0ED, /* SSIF2 (RTX) */ 00154 DMA_RS_SSIRXI3 = 0x0EE, /* SSIF3 (TX) */ 00155 DMA_RS_SSIRTI4 = 0x0F3, /* SSIF4 (RTX) */ 00156 DMA_RS_SSITXI5 = 0x0F5, /* SSIF5 (TX) */ 00157 DMA_RS_SSIRXI5 = 0x0F6, /* SSIF5 (RX) */ 00158 DMA_RS_SCUTXI0 = 0x101, /* SCUX (FFD0) */ 00159 DMA_RS_SCURXI0 = 0x102, /* SCUX (FFU0) */ 00160 DMA_RS_SCUTXI1 = 0x105, /* SCUX (FFD1) */ 00161 DMA_RS_SCURXI1 = 0x106, /* SCUX (FFU1) */ 00162 DMA_RS_SCUTXI2 = 0x109, /* SCUX (FFD2) */ 00163 DMA_RS_SCURXI2 = 0x10A, /* SCUX (FFU2) */ 00164 DMA_RS_SCUTXI3 = 0x10D, /* SCUX (FFD3) */ 00165 DMA_RS_SCURXI3 = 0x10E, /* SCUX (FFU3) */ 00166 DMA_RS_SPTI0 = 0x121, /* SPI0 (TX) */ 00167 DMA_RS_SPRI0 = 0x122, /* SPI0 (RX) */ 00168 DMA_RS_SPTI1 = 0x125, /* SPI1 (TX) */ 00169 DMA_RS_SPRI1 = 0x126, /* SPI1 (RX) */ 00170 DMA_RS_SPTI2 = 0x129, /* SPI2 (TX) */ 00171 DMA_RS_SPRI2 = 0x12A, /* SPI2 (RX) */ 00172 DMA_RS_SPTI3 = 0x12B, /* SPI3 (TX) */ 00173 DMA_RS_SPRI3 = 0x12E, /* SPI3 (RX) */ 00174 DMA_RS_SPTI4 = 0x131, /* SPI4 (TX) */ 00175 DMA_RS_SPRI4 = 0x132, /* SPI4 (RX) */ 00176 DMA_RS_SPDIFTXI = 0x141, /* SPDIF (TX) */ 00177 DMA_RS_SPDIFRXI = 0x142, /* SPDIF (RX) */ 00178 DMA_RS_CMI1 = 0x147, /* Motor Control PWM Timer ch1 */ 00179 DMA_RS_CMI2 = 0x14B, /* Motor Control PWM Timer ch2 */ 00180 DMA_RS_MLBCI = 0x14F, /* Media Local Bus */ 00181 DMA_RS_SGDEI0 = 0x153, /* Sound Generator0 */ 00182 DMA_RS_SGDEI1 = 0x157, /* Sound Generator1 */ 00183 DMA_RS_SGDEI2 = 0x15B, /* Sound Generator2 */ 00184 DMA_RS_SGDEI3 = 0x15F, /* Sound Generator3 */ 00185 DMA_RS_SCITXI0 = 0x169, /* Serial Communication Interface ch0 (TX) */ 00186 DMA_RS_SCIRXI0 = 0x16A, /* Serial Communication Interface ch0 (RX) */ 00187 DMA_RS_SCITXI1 = 0x16D, /* Serial Communication Interface ch1 (TX) */ 00188 DMA_RS_SCIRXI1 = 0x16E, /* Serial Communication Interface ch1 (RX) */ 00189 DMA_RS_TI0 = 0x181, /* IIC ch0 (TX) */ 00190 DMA_RS_RI0 = 0x182, /* IIC ch0 (RX) */ 00191 DMA_RS_TI1 = 0x185, /* IIC ch1 (TX) */ 00192 DMA_RS_RI1 = 0x186, /* IIC ch1 (RX) */ 00193 DMA_RS_TI2 = 0x189, /* IIC ch2 (TX) */ 00194 DMA_RS_RI2 = 0x18A, /* IIC ch2 (RX) */ 00195 DMA_RS_TI3 = 0x18D, /* IIC ch3 (TX) */ 00196 DMA_RS_RI3 = 0x18E, /* IIC ch3 (RX) */ 00197 DMA_RS_LIN0_INT_T = 0x1A1, /* LIN0 (TX) */ 00198 DMA_RS_LIN0_INT_R = 0x1A2, /* LIN0 (RX) */ 00199 DMA_RS_LIN1_INT_T = 0x1A5, /* LIN1 (TX) */ 00200 DMA_RS_LIN1_INT_R = 0x1A6, /* LIN1 (RX) */ 00201 DMA_RS_IFEI0 = 0x1B1, /* Pixel Format Converter ch0 (TX) */ 00202 DMA_RS_OFFI0 = 0x1B2, /* Pixel Format Converter ch0 (TX) */ 00203 DMA_RS_IFEI1 = 0x1B5, /* Pixel Format Converter ch1 (RX) */ 00204 DMA_RS_OFFI1 = 0x1B6 /* Pixel Format Converter ch1 (TX) */ 00205 } dma_res_select_t; 00206 00207 /* DMA transfer direction */ 00208 typedef enum 00209 { 00210 DMA_REQ_MIN =(-1), 00211 DMA_REQ_SRC = 0, /* Read DMA */ 00212 DMA_REQ_DES = 1, /* Write DMA */ 00213 DMA_REQ_MAX = 2 00214 } dma_req_dir_t; 00215 00216 /* Address count direction */ 00217 typedef enum 00218 { 00219 DMA_ADDR_MIN = (-1), 00220 DMA_ADDR_INCREMENT = 0, /* Address Count Increment */ 00221 DMA_ADDR_FIX = 1, /* Address Count Fix */ 00222 DMA_ADDR_MAX = 2 00223 } dma_addr_cnt_t; 00224 00225 00226 /************************************************************************* 00227 Structures 00228 *************************************************************************/ 00229 00230 /* DMA Init Parameter */ 00231 typedef struct 00232 { 00233 bool_t channel[DMA_CH_NUM]; /* Set enable channel */ 00234 AIOCB *p_aio; /* set callback function (DMA error interrupt) */ 00235 }dma_drv_init_t; 00236 00237 /* DMA Setup Parameter */ 00238 typedef struct 00239 { 00240 dma_res_select_t resource; /* DMA Transfer Resource */ 00241 dma_req_dir_t direction; /* DMA Transfer Direction */ 00242 dma_unit_size_t dst_width; /* DMA Transfer Unit Size (Destination) */ 00243 dma_unit_size_t src_width; /* DMA Transfer Unit Size (Source) */ 00244 dma_addr_cnt_t dst_cnt; /* DMA Address Count (Destination) */ 00245 dma_addr_cnt_t src_cnt; /* DMA Address Count (Source) */ 00246 AIOCB *p_aio; /* set callback function (DMA end interrupt) */ 00247 } dma_ch_setup_t; 00248 00249 /* DMA Transfer Paramter */ 00250 typedef struct 00251 { 00252 void *src_addr; /* Sorce Address */ 00253 void *dst_addr; /* Destination Address */ 00254 uint32_t count; /* DMA Transfer Size */ 00255 } dma_trans_data_t; 00256 00257 /*********************************************************************************** 00258 Function Prototypes 00259 ***********************************************************************************/ 00260 00261 /*********************************************************************************** 00262 * ingroup API 00263 * This function initializes the driver and must be called at system start 00264 * up, prior to any required DMA functionality being available. This function 00265 * also sets the enable or disable for each DMA channel and DMA error call back 00266 * function. 00267 * 00268 * param [in] p_dma_init_param - parameter of ch enable and DMA error callback function. 00269 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.) 00270 * 00271 * retval ESUCCESS - successfully initialized. 00272 * retval -1 - error occured. 00273 ***********************************************************************************/ 00274 00275 extern int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno); 00276 00277 /*********************************************************************************** 00278 * ingroup API 00279 * This function shutdown the driver, making DMA functionality is no longer available. 00280 * It can be carried out only in calse of all channel free. 00281 * 00282 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.) 00283 * 00284 * retval ESUCCESS - successfully uninitialized. 00285 * retval -1 - error occured. 00286 ***********************************************************************************/ 00287 00288 extern int_t R_DMA_UnInit(int32_t * const p_errno); 00289 00290 /*********************************************************************************** 00291 * ingroup API 00292 * This function allocates a DMA channel. 00293 * When channel is (-1), it looking for a free channel 00294 * When set channel to DMA channel number, a set channel is allocated 00295 * 00296 * param [in] channel - allocate channel. (when channel is (-1), it looking for a 00297 * free channel.) 00298 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.) 00299 * 00300 * retval channel number - successfully allocated. 00301 * retval -1 - error occured. 00302 ***********************************************************************************/ 00303 00304 extern int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno); 00305 00306 /*********************************************************************************** 00307 * ingroup API 00308 * This function close a DMA channel. 00309 * 00310 * param [in] channel - close channel. 00311 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.) 00312 * 00313 * retval ESUCCESS - successfully allocate. 00314 * retval -1 - error occured. 00315 ***********************************************************************************/ 00316 00317 extern int_t R_DMA_Free(const int_t channel, int32_t * const p_errno); 00318 00319 /*********************************************************************************** 00320 * ingroup API 00321 * This function set up a DMA transfer parameter. 00322 * before calling R_DMA_Start(), please carry out this function. 00323 * 00324 * param [in] channel - set up channel. 00325 * param [in] p_ch_setup - DMA transfer parameters. 00326 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.) 00327 * 00328 * retval ESUCCESS - successfully setup. 00329 * retval -1 - error occured. 00330 ***********************************************************************************/ 00331 00332 extern int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup, 00333 int32_t * const p_errno); 00334 00335 /*********************************************************************************** 00336 * ingroup API 00337 * This function set up a DMA transfer address and start DMA. 00338 * 00339 * param [in] channel - DMA start channel. 00340 * param [in] p_ch_setup - DMA address parameters. 00341 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.) 00342 * 00343 * retval ESUCCESS - successfully DMA start. 00344 * retval -1 - error occured. 00345 ***********************************************************************************/ 00346 00347 extern int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data, 00348 int32_t * const p_errno); 00349 00350 /*********************************************************************************** 00351 * ingroup API 00352 * This function set up a continous DMA transfer address and start continuous DMA. 00353 * 00354 * param [in] channel - continuous DMA start channel. 00355 * param [in] p_ch_setup - continuous DMA address parameters. 00356 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.) 00357 * 00358 * retval ESUCCESS - successfully continuous DMA start. 00359 * retval -1 - error occured. 00360 ***********************************************************************************/ 00361 00362 extern int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data, 00363 int32_t * const p_errno); 00364 00365 /*********************************************************************************** 00366 * ingroup API 00367 * This function cancel DMA transfer. 00368 * Continous DMA also stops at the same time. 00369 * Please call this function during DMA transfer. 00370 * 00371 * param [in] channel - chancel DMA start channel. 00372 * param [out] p_remain - remain sizei of DMA transfer. 00373 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.) 00374 * 00375 * retval ESUCCESS - successfully cancel. 00376 * retval -1 - error occured. 00377 ***********************************************************************************/ 00378 00379 extern int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno); 00380 00381 00382 /*********************************************************************************** 00383 * ingroup API 00384 * This function get DMA driver version. 00385 * 00386 * param none 00387 * 00388 * retval driver version 00389 ***********************************************************************************/ 00390 00391 extern uint16_t R_DMA_GetVersion(void); 00392 00393 #ifdef __cplusplus 00394 } 00395 #endif /* __cplusplus */ 00396 00397 #endif /* DMA_IF_H */
Generated on Tue Jul 12 2022 20:43:58 by 1.7.2