dma.h

00001 /*******************************************************************************
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00021 * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
00022 *******************************************************************************/
00023 
00024 /**************************************************************************//**
00025 * @file         dma.h
00026 * $Rev: 1616 $
00027 * $Date:: 2015-04-21 19:00:08 +0900#$
00028 * @brief        DMA Driver internal headers
00029 ******************************************************************************/
00030 
00031 /*****************************************************************************
00032 * History : DD.MM.YYYY Version Description
00033 * : 15.01.2013 1.00 First Release
00034 ******************************************************************************/
00035 
00036 #ifndef DMA_H
00037 #define DMA_H
00038 
00039 /******************************************************************************
00040 Includes <System Includes>, "Project Includes"
00041 ******************************************************************************/
00042 
00043 #include "dma_if.h" 
00044 #include "Renesas_RZ_A1.h"
00045 #include "bsp_drv_cmn.h"
00046 
00047 /******************************************************************************
00048 Macro definitions
00049 ******************************************************************************/
00050 
00051 /* Number of channel configure table */
00052 #define DMA_CH_CONFIG_TABLE_NUM  (95U)
00053 
00054 /* Magic Number */
00055 #define SHIFT_DMARS_EVEN_CH      (0U)  /* Shift Value for DMARS Register access in Even ch */
00056 #define SHIFT_DMARS_ODD_CH       (16U) /* Shift Value for DMARS Register access in Odd ch */
00057 #define MASK_DMARS_EVEN_CH       (0xFFFF0000U) /* Mask value for DMARS Register in Even ch */
00058 #define MASK_DMARS_ODD_CH        (0x0000FFFFU) /* Mask value for DMARS Register in Odd ch */
00059 #define HIGH_COMMON_REG_OFFSET   (8)  /* for Common Register Access in ch 0-8 */
00060 #define CHECK_ODD_EVEN_MASK      (0x00000001U)  /* for check value of odd or even */
00061 #define DMA_STOP_WAIT_MAX_CNT    (10U) /* Loop count for DMA stop (usually, a count is set to 0 or 1) */
00062 
00063 /* Register Set Value */
00064 /* Init Value */
00065 #define N0SA_INIT_VALUE      (0U)          /* HW init value */
00066 #define N1SA_INIT_VALUE      (0U)          /* HW init value */
00067 #define N0DA_INIT_VALUE      (0U)          /* HW init value */
00068 #define N1DA_INIT_VALUE      (0U)          /* HW init value */
00069 #define N0TB_INIT_VALUE      (0U)          /* HW init value */
00070 #define N1TB_INIT_VALUE      (0U)          /* HW init value */
00071 #define CHCTRL_INIT_VALUE    (0U)          /* HW init value */
00072 #define CHCFG_INIT_VALUE     (0x01000000U) /* interrupt disable */
00073 #define CHITVL_INIT_VALUE    (0U)          /* DMA interval = 0 */
00074 #define CHEXT_INIT_VALUE     (0U)          /* HW init value */
00075 #define NXLA_INIT_VALUE      (0U)          /* HW init value */
00076 #define DCTRL_INIT_VALUE     (0x00000001U) /* interrupt output : pulse, round robin mode */
00077 #define DMARS_INIT_VALUE     (0U)          /* HW init value */
00078 /* Fixed Setting for CHCFG */
00079 #define CHCFG_FIXED_VALUE    (0x00000020U) /* register mode, not buffer sweep, interrupt detect when high pulse */
00080 
00081 /* Bit Value & Mask */
00082 /* CHSTAT */
00083 #define CHSTAT_MASK_SR         (0x00000080U)
00084 #define CHSTAT_MASK_END        (0x00000020U)
00085 #define CHSTAT_MASK_ER         (0x00000010U)
00086 #define CHSTAT_MASK_TACT       (0x00000004U)
00087 #define CHSTAT_MASK_EN         (0x00000001U)
00088 /* CHCTRL */
00089 #define CHCTRL_SET_CLRTC       (0x00000040U)
00090 #define CHCTRL_SET_CLREND      (0x00000020U)
00091 #define CHCTRL_SET_SWRST       (0x00000008U)
00092 #define CHCTRL_SET_CLREN       (0x00000002U)
00093 #define CHCTRL_SET_SETEN       (0x00000001U)
00094 /* CHCFG */
00095 #define CHCFG_SET_REN          (0x40000000U)
00096 #define CHCFG_MASK_REN         (0x40000000U)
00097 #define CHCFG_SET_RSW          (0x20000000U)
00098 #define CHCFG_MASK_RSW         (0x20000000U)
00099 #define CHCFG_SET_RSEL         (0x10000000U)
00100 #define CHCFG_MASK_RSEL        (0x10000000U)
00101 #define CHCFG_SET_DEM          (0x01000000U)
00102 #define CHCFG_MASK_DEM         (0x01000000U)
00103 #define CHCFG_MASK_DAD         (0x00200000U)
00104 #define CHCFG_MASK_SAD         (0x00100000U)
00105 #define CHCFG_MASK_DDS         (0x000f0000U)
00106 #define CHCFG_MASK_SDS         (0x0000f000U)
00107 #define CHCFG_SET_AM_LEVEL     (0x00000100U)
00108 #define CHCFG_SET_AM_BUS_CYCLE (0x00000200U)
00109 #define CHCFG_MASK_AM          (0x00000700U)
00110 #define CHCFG_SET_LVL_EDGE     (0x00000000U)
00111 #define CHCFG_SET_LVL_LEVEL    (0x00000040U)
00112 #define CHCFG_MASK_LVL         (0x00000040U)
00113 #define CHCFG_SET_REQD_SRC     (0x00000000U)
00114 #define CHCFG_SET_REQD_DST     (0x00000008U)
00115 #define CHCFG_MASK_REQD        (0x00000008U)
00116 #define CHCFG_SHIFT_DAD        (21U)
00117 #define CHCFG_SHIFT_SAD        (20U)
00118 #define CHCFG_SHIFT_DDS        (16U)
00119 #define CHCFG_SHIFT_SDS        (12U)
00120 /* CHEXT */
00121 #define CHEXT_SET_DCA_NORMAL      (0x00003000U)
00122 #define CHEXT_SET_DCA_STRONG      (0x00000000U)
00123 #define CHEXT_SET_DPR_NON_SECURE  (0x00000200U)
00124 #define CHEXT_SET_SCA_NORMAL      (0x00000030U)
00125 #define CHEXT_SET_SCA_STRONG      (0x00000000U)
00126 #define CHEXT_SET_SPR_NON_SECURE  (0x00000002U)
00127 
00128 
00129 /* REQD value in CHCFG is undecided on config table */
00130 /* used case of a resource is the same and two or more direction value exists.  */
00131 #define CHCFG_REQD_UNDEFINED   DMA_REQ_MAX
00132 
00133 /* Address of area which is the target of setting change */
00134 #define DMA_EXTERNAL_BUS_START         (0x00000000U)
00135 #define DMA_EXTERNAL_BUS_END           (0x1FFFFFFFU)
00136 #define DMA_EXTERNAL_BUS_MIRROR_START  (0x40000000U)
00137 #define DMA_EXTERNAL_BUS_MIRROR_END    (0x5FFFFFFFU)
00138 
00139 /*************************************************************************
00140  Enumerated Types
00141 *************************************************************************/
00142 
00143 /* DRV Status */
00144 typedef enum
00145 {
00146     DMA_DRV_UNINIT = 0,   /* Uninit */
00147     DMA_DRV_INIT   = 1    /* Init */
00148 } dma_stat_drv_t;
00149 
00150 /* Channel Status */
00151 typedef enum
00152 {
00153     DMA_CH_UNINIT   = 0,   /* Uninit */
00154     DMA_CH_INIT     = 1,   /* Init */
00155     DMA_CH_OPEN     = 2,   /* Open */
00156     DMA_CH_TRANSFER = 4    /* Transfer */
00157 } dma_stat_ch_t;
00158 
00159 /*************************************************************************
00160  Structures
00161 *************************************************************************/
00162 
00163 /* DMA Register (Common) */
00164 typedef struct
00165 {
00166     volatile uint32_t  dctrl;            
00167     volatile uint32_t  dstat_en;         
00168     volatile uint32_t  dstat_er;         
00169     volatile uint32_t  dstat_end;        
00170     volatile uint32_t  dstat_tc;         
00171     volatile uint32_t  dstat_sus;        
00172 } dma_reg_common_t;
00173 
00174 /* DMA Register (every Channel) */
00175 typedef struct
00176 {
00177     volatile uint32_t  n0sa;        
00178     volatile uint32_t  n0da;         
00179     volatile uint32_t  n0tb;         
00180     volatile uint32_t  n1sa;         
00181     volatile uint32_t  n1da;         
00182     volatile uint32_t  n1tb;         
00183     volatile uint32_t  crsa;         
00184     volatile uint32_t  crda;         
00185     volatile uint32_t  crtb;         
00186     volatile uint32_t  chstat;       
00187     volatile uint32_t  chctrl;       
00188     volatile uint32_t  chcfg;        
00189     volatile uint32_t  chitvl;       
00190     volatile uint32_t  chext;        
00191     volatile uint32_t  nxla;        
00192     volatile uint32_t  crla;         
00193 } dma_reg_ch_t;
00194 
00195 /* Information of Channel */
00196 typedef struct
00197 {
00198     int_t              ch;                /* Channel Number */
00199     dma_stat_ch_t      ch_stat;           /* Channel Status */
00200     dma_res_select_t   resource;          /* DMA Transfer Resource */
00201     dma_req_dir_t      direction;         /* DMA Transfer Direction */
00202     dma_unit_size_t    src_width;         /* DMA Transfer Unit Size (Source) */
00203     dma_addr_cnt_t     src_cnt;           /* DMA Address Count (Source) */
00204     dma_unit_size_t    dst_width;         /* DMA Transfer Unit Size (Destination) */
00205     dma_addr_cnt_t     dst_cnt;           /* DMA Address Count (Destination) */
00206     void               *src_addr0;        /* Sorce Address (Next Register Set 0)*/
00207     void               *dst_addr0;        /* Destination Address (Next Register Set 0)*/
00208     uint32_t           count0;            /* DMA Transfer Size (Next Register Set 0)*/
00209     void               *src_addr1;        /* Sorce Address (Next Register Set 1)*/
00210     void               *dst_addr1;        /* Destination Address (Next Register Set 1)*/
00211     uint32_t           count1;            /* DMA Transfer Size (Next Register Set 1)*/
00212     IRQn_Type          end_irq_num;       /* DMA end interrupt number */
00213     AIOCB              *p_end_aio;        /* set callback function (DMA end interrupt) */
00214     bool_t             next_dma_flag;     /* Setting Flag of Continous DMA */
00215     uint32_t           shift_dmars;       /* set SHIFT_DMARS_ODD_CH or SHIFT_DMARS_EVEN_CH */
00216     uint32_t           mask_dmars;        /* set MASK_DMA_ODD_CH or MASK_DMARS_EVEN_CH */
00217     bool_t             setup_flag;        /* incdicate called DMA_Setup() flag */
00218     volatile struct st_dmac_n       *p_dma_ch_reg;     /* DMA Register for every channel */
00219     volatile struct st_dmaccommon_n *p_dma_common_reg; /* DMA Register for common */
00220     volatile uint32_t           *p_dma_dmars_reg;  /* DMARS Regsiter */
00221 } dma_info_ch_t;
00222 
00223 /* Information of Driver */
00224 typedef struct
00225 {
00226     dma_stat_drv_t  drv_stat;            /* DRV Status */
00227     AIOCB           *p_err_aio;          /* set callback function (DMA error interrupt) */
00228     IRQn_Type       err_irq_num;         /* DMA error interrupt number */
00229     dma_info_ch_t   info_ch[DMA_CH_NUM]; /* Enable Channel */
00230 } dma_info_drv_t;
00231 
00232 /* DMA Channel Configure Table */
00233 typedef struct
00234 {
00235     dma_res_select_t   dmars;             /* Set Value for DMARS Register */
00236     uint32_t           tm;                /* Set Value for TM Bit (CHCFG Register) */
00237     uint32_t           lvl;               /* Set Value for LVL Bit (CHCFG Register) */
00238     uint32_t           reqd;              /* Set Value for REQD (CHCFG Register) */
00239 } dma_ch_cfg_t;
00240 
00241 /***********************************************************************************
00242  Function Prototypes
00243 ***********************************************************************************/
00244 
00245 dma_info_drv_t *DMA_GetDrvInstance(void);
00246 dma_info_ch_t  *DMA_GetDrvChInfo(const int_t channel);
00247 int_t DMA_Initialize(const dma_drv_init_t * const p_dma_init_param);
00248 int_t DMA_UnInitialize(void);
00249 int_t DMA_GetFreeChannel(void);
00250 int_t DMA_GetFixedChannel(const int_t channel);
00251 void  DMA_CloseChannel(const int_t channel);
00252 void  DMA_SetParam(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
00253                    const dma_ch_cfg_t * const p_ch_cfg, const uint32_t reqd);
00254 void  DMA_BusParam(const int_t channel, const dma_trans_data_t * const p_dma_data);
00255 void  DMA_SetData(const int_t channel, const dma_trans_data_t * const p_dma_data, 
00256                  const uint32_t next_register_set);
00257 void  DMA_SetNextData(const int_t channel, const dma_trans_data_t * const p_dma_data);
00258 void  DMA_Start(const int_t channel, const bool_t restart_flag);
00259 void  DMA_Stop(const int_t channel, uint32_t * const p_remain);
00260 void  DMA_SetErrCode(const int_t error_code, int32_t * const p_errno);
00261 
00262 #endif /* DMA_H */