3 months, 3 weeks ago.

GR-Peach schematic errors

I have noticed several places on Page 6 of the GR-Peach schematic where pin functions are mislabeled (schematic document number X28A-M01-C dated 9 Feb 2015). Can anyone confirm these, and maybe provide others that you have found?

1. The pin function names for JP4 and JP5 appear to be reversed. Jumping JP5 puts P8_8-TIOC1A on CN9 Pin 7, not Pin 8. Pin 8 still functions as SPI0/SSL with JP5 shorted.

2. CN14 Pin 7 (P2_14) should be IRQ0, not IRQ1.

3. CN14 Pin 8 (P2_15) should be IRQ1, not IRQ0.

In addition, several alternate functions are left off of the schematic, but would be nice to use as a reference without going to the big CPU book. The most useful might be that the "User Button" (SW0) on P6_0 can also be TIOC1A, IRQ5, and RxD3. Also, CN13 Pin 2 (P8_1) can fill in for MOSI0 if you took P10_14 away with JP5. It could also be TxD5.

Question relating to:

GR-PEACH from Renesas is an mbed enabled platform which combines the advantages of the mbed ecosystem and Arduino form factor
Comment on this question

1 Answer

3 months, 3 weeks ago.

Thank you for pointing out. I confirmed it as a mistake. I will correct the circuit diagram.

To post an answer, please log in.