Cortex-M0 Instruction Set Summary

The Cortex M0 processor implements a version of the Thumb instruction set. Table 1 lists the supported instructions.

Note

In Table 1:

• angle brackets, <>, enclose alternative forms of the operand
• braces, {}, enclose optional operands and mnemonic parts
• the Operands column is not exhaustive.

For more information on the instructions and operands, see the instruction descriptions.

Table 1 Cortex-M0 instructions

Mnemonic	Operands	Brief description	Flags	See
ADCS	{Rd,} Rn, Rm	Add with Carry	N,Z,C,V	ADC, ADD, RSB, SBC, and SUB
ADD{S}	{Rd,} Rn, <Rm|#imm>	Add	N,Z,C,V	ADC, ADD, RSB, SBC, and SUB
ADR	Rd, label	PC-relative Address to Register	-	ADR
ANDS	{Rd,} Rn, Rm	Bitwise AND	N,Z	ADC, ADD, RSB, SBC, and SUB
ASRS	{Rd,} Rm, <Rs|#imm>	Arithmetic Shift Right	N,Z,C	ASR, LSL, LSR, and ROR
B{cc}	label	Branch {conditionally}	-	B, BL, BX, and BLX
BICS	{Rd,} Rn, Rm	Bit Clear	N,Z	AND, ORR, EOR, and BIC
BKPT	#imm	Breakpoint	-	BKPT
BL	label	Branch with Link	-	B, BL, BX, and BLX
BLX	Rm	Branch indirect with Link	-	B, BL, BX, and BLX
BX	Rm	Branch indirect	-	B, BL, BX, and BLX
CMN	Rn, Rm	Compare Negative	N,Z,C,V	CMP and CMN
CMP	Rn, <Rm|#imm>	Compare	N,Z,C,V	CMP and CMN
CPSID	i	Change Processor State, Disable Interrupts	-	CPS
CPSIE	i	Change Processor State, Enable Interrupts	-	CPS
DMB	-	Data Memory Barrier	-	DMB
DSB	-	Data Synchronization Barrier	-	DSB
EORS	{Rd,} Rn, Rm	Exclusive OR	N,Z	AND, ORR, EOR, and BIC
ISB	-	Instruction Synchronization Barrier	-	ISB
LDM	Rn{!}, reglist	Load Multiple registers, increment after	-	LDM and STM
LDR	Rt, label	Load Register from PC-relative address	-	Memory access instructions
LDR	Rt, [Rn, <Rm|#imm>]	Load Register with word	-	Memory access instructions
LDRB	Rt, [Rn, <Rm|#imm>]	Load Register with byte	-	Memory access instructions
LDRH	Rt, [Rn, <Rm|#imm>]	Load Register with halfword	-	Memory access instructions
LDRSB	Rt, [Rn, <Rm|#imm>]	Load Register with signed byte	-	Memory access instructions
LDRSH	Rt, [Rn, <Rm|#imm>]	Load Register with signed halfword	-	Memory access instructions
LSLS	{Rd,} Rn, <Rs|#imm>	Logical Shift Left	N,Z,C	ASR, LSL, LSR, and ROR
LSRS	{Rd,} Rn, <Rs|#imm>	Logical Shift Right	N,Z,C	ASR, LSL, LSR, and ROR
MOV{S}	Rd, Rm	Move	N,Z	MOV and MVN
MRS	Rd, spec_reg	Move to general register from special register	-	MRS
MSR	spec_reg, Rm	Move to special register from general register	N,Z,C,V	MSR
MULS	Rd, Rn, Rm	Multiply, 32-bit result	N,Z	MULS
MVNS	Rd, Rm	Bitwise NOT	N,Z	MOV and MVN
NOP	-	No Operation	-	NOP
ORRS	{Rd,} Rn, Rm	Logical OR	N,Z	AND, ORR, EOR, and BIC
POP	reglist	Pop registers from stack	-	PUSH and POP
PUSH	reglist	Push registers onto stack	-	PUSH and POP
REV	Rd, Rm	Byte-Reverse word	-	REV, REV16, and REVSH
REV16	Rd, Rm	Byte-Reverse packed halfwords	-	REV, REV16, and REVSH
REVSH	Rd, Rm	Byte-Reverse signed halfword	-	REV, REV16, and REVSH
RORS	{Rd,} Rn, Rs	Rotate Right	N,Z,C	ASR, LSL, LSR, and ROR
RSBS	{Rd,} Rn, #0	Reverse Subtract	N,Z,C,V	ADC, ADD, RSB, SBC, and SUB
SBCS	{Rd,} Rn, Rm	Subtract with Carry	N,Z,C,V	ADC, ADD, RSB, SBC, and SUB
SEV	-	Send Event	-	SEV
STM	Rn!, reglist	Store Multiple registers, increment after	-	LDM and STM
STR	Rt, [Rn, <Rm|#imm>]	Store Register as word	-	Memory access instructions
STRB	Rt, [Rn, <Rm|#imm>]	Store Register as byte	-	Memory access instructions
STRH	Rt, [Rn, <Rm|#imm>]	Store Register as halfword	-	Memory access instructions
SUB{S}	{Rd,} Rn, <Rm|#imm>	Subtract	N,Z,C,V	ADC, ADD, RSB, SBC, and SUB
SVC	#imm	Supervisor Call	-	SVC
SXTB	Rd, Rm	Sign extend byte	-	SXT and UXT
SXTH	Rd, Rm	Sign extend halfword	-	SXT and UXT
TST	Rn, Rm	Logical AND based test	N,Z	TST
UXTB	Rd, Rm	Zero extend a byte	-	SXT and UXT
UXTH	Rd, Rm	Zero extend a halfword	-	SXT and UXT
WFE	-	Wait For Event	-	WFE
WFI	-	Wait For Interrupt	-	WFI