usbreg.h

00001 /*----------------------------------------------------------------------------
00002  *      U S B  -  K e r n e l
00003  *----------------------------------------------------------------------------
00004  *      Name:    USBREG.H
00005  *      Purpose: USB Hardware Layer Definitions for NXP Semiconductors LPC 
00006  *      family MCUs
00007  *      Version: V1.10
00008  *----------------------------------------------------------------------------
00009  *      This software is supplied "AS IS" without any warranties, express,
00010  *      implied or statutory, including but not limited to the implied
00011  *      warranties of fitness for purpose, satisfactory quality and
00012  *      noninfringement. Keil extends you a royalty-free right to reproduce
00013  *      and distribute executable files created using this software for use
00014  *      on NXP Semiconductors LPC family microcontroller devices only. Nothing 
00015  *      else gives you the right to use this software.
00016  *
00017  *      Copyright (c) 2005-2009 Keil Software.
00018  *---------------------------------------------------------------------------*/
00019 
00020 #ifndef __USBREG_H
00021 #define __USBREG_H
00022 
00023 /* Device Interrupt Bit Definitions */
00024 #define FRAME_INT           0x00000001
00025 #define EP_FAST_INT         0x00000002
00026 #define EP_SLOW_INT         0x00000004
00027 #define DEV_STAT_INT        0x00000008
00028 #define CCEMTY_INT          0x00000010
00029 #define CDFULL_INT          0x00000020
00030 #define RxENDPKT_INT        0x00000040
00031 #define TxENDPKT_INT        0x00000080
00032 #define EP_RLZED_INT        0x00000100
00033 #define ERR_INT             0x00000200
00034 
00035 /* Rx & Tx Packet Length Definitions */
00036 #define PKT_LNGTH_MASK      0x000003FF
00037 #define PKT_DV              0x00000400
00038 #define PKT_RDY             0x00000800
00039 
00040 /* USB Control Definitions */
00041 #define CTRL_RD_EN          0x00000001
00042 #define CTRL_WR_EN          0x00000002
00043 
00044 /* Command Codes */
00045 #define CMD_SET_ADDR        0x00D00500
00046 #define CMD_CFG_DEV         0x00D80500
00047 #define CMD_SET_MODE        0x00F30500
00048 #define CMD_RD_FRAME        0x00F50500
00049 #define DAT_RD_FRAME        0x00F50200
00050 #define CMD_RD_TEST         0x00FD0500
00051 #define DAT_RD_TEST         0x00FD0200
00052 #define CMD_SET_DEV_STAT    0x00FE0500
00053 #define CMD_GET_DEV_STAT    0x00FE0500
00054 #define DAT_GET_DEV_STAT    0x00FE0200
00055 #define CMD_GET_ERR_CODE    0x00FF0500
00056 #define DAT_GET_ERR_CODE    0x00FF0200
00057 #define CMD_RD_ERR_STAT     0x00FB0500
00058 #define DAT_RD_ERR_STAT     0x00FB0200
00059 #define DAT_WR_BYTE(x)     (0x00000100 | ((x) << 16))
00060 #define CMD_SEL_EP(x)      (0x00000500 | ((x) << 16))
00061 #define DAT_SEL_EP(x)      (0x00000200 | ((x) << 16))
00062 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
00063 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
00064 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
00065 #define CMD_CLR_BUF         0x00F20500
00066 #define DAT_CLR_BUF         0x00F20200
00067 #define CMD_VALID_BUF       0x00FA0500
00068 
00069 /* Device Address Register Definitions */
00070 #define DEV_ADDR_MASK       0x7F
00071 #define DEV_EN              0x80
00072 
00073 /* Device Configure Register Definitions */
00074 #define CONF_DVICE          0x01
00075 
00076 /* Device Mode Register Definitions */
00077 #define AP_CLK              0x01
00078 #define INAK_CI             0x02
00079 #define INAK_CO             0x04
00080 #define INAK_II             0x08
00081 #define INAK_IO             0x10
00082 #define INAK_BI             0x20
00083 #define INAK_BO             0x40
00084 
00085 /* Device Status Register Definitions */
00086 #define DEV_CON             0x01
00087 #define DEV_CON_CH          0x02
00088 #define DEV_SUS             0x04
00089 #define DEV_SUS_CH          0x08
00090 #define DEV_RST             0x10
00091 
00092 /* Error Code Register Definitions */
00093 #define ERR_EC_MASK         0x0F
00094 #define ERR_EA              0x10
00095 
00096 /* Error Status Register Definitions */
00097 #define ERR_PID             0x01
00098 #define ERR_UEPKT           0x02
00099 #define ERR_DCRC            0x04
00100 #define ERR_TIMOUT          0x08
00101 #define ERR_EOP             0x10
00102 #define ERR_B_OVRN          0x20
00103 #define ERR_BTSTF           0x40
00104 #define ERR_TGL             0x80
00105 
00106 /* Endpoint Select Register Definitions */
00107 #define EP_SEL_F            0x01
00108 #define EP_SEL_ST           0x02
00109 #define EP_SEL_STP          0x04
00110 #define EP_SEL_PO           0x08
00111 #define EP_SEL_EPN          0x10
00112 #define EP_SEL_B_1_FULL     0x20
00113 #define EP_SEL_B_2_FULL     0x40
00114 
00115 /* Endpoint Status Register Definitions */
00116 #define EP_STAT_ST          0x01
00117 #define EP_STAT_DA          0x20
00118 #define EP_STAT_RF_MO       0x40
00119 #define EP_STAT_CND_ST      0x80
00120 
00121 /* Clear Buffer Register Definitions */
00122 #define CLR_BUF_PO          0x01
00123 
00124 
00125 /* DMA Interrupt Bit Definitions */
00126 #define EOT_INT             0x01
00127 #define NDD_REQ_INT         0x02
00128 #define SYS_ERR_INT         0x04
00129 
00130 
00131 #endif  /* __USBREG_H */