These are the examples provided for [[/users/frank26080115/libraries/LPC1700CMSIS_Lib/]] Note, the entire "program" is not compilable!
usbreg.h
00001 /*---------------------------------------------------------------------------- 00002 * U S B - K e r n e l 00003 *---------------------------------------------------------------------------- 00004 * Name: usbreg.h 00005 * Purpose: USB Hardware Layer Definitions for NXP LPC Family MCUs 00006 * Version: V1.20 00007 *---------------------------------------------------------------------------- 00008 * This software is supplied "AS IS" without any warranties, express, 00009 * implied or statutory, including but not limited to the implied 00010 * warranties of fitness for purpose, satisfactory quality and 00011 * noninfringement. Keil extends you a royalty-free right to reproduce 00012 * and distribute executable files created using this software for use 00013 * on NXP Semiconductors LPC family microcontroller devices only. Nothing 00014 * else gives you the right to use this software. 00015 * 00016 * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. 00017 *---------------------------------------------------------------------------*/ 00018 00019 #ifndef __USBREG_H 00020 #define __USBREG_H 00021 00022 /* Device Interrupt Bit Definitions */ 00023 #define FRAME_INT 0x00000001 00024 #define EP_FAST_INT 0x00000002 00025 #define EP_SLOW_INT 0x00000004 00026 #define DEV_STAT_INT 0x00000008 00027 #define CCEMTY_INT 0x00000010 00028 #define CDFULL_INT 0x00000020 00029 #define RxENDPKT_INT 0x00000040 00030 #define TxENDPKT_INT 0x00000080 00031 #define EP_RLZED_INT 0x00000100 00032 #define ERR_INT 0x00000200 00033 00034 /* Rx & Tx Packet Length Definitions */ 00035 #define PKT_LNGTH_MASK 0x000003FF 00036 #define PKT_DV 0x00000400 00037 #define PKT_RDY 0x00000800 00038 00039 /* USB Control Definitions */ 00040 #define CTRL_RD_EN 0x00000001 00041 #define CTRL_WR_EN 0x00000002 00042 00043 /* Command Codes */ 00044 #define CMD_SET_ADDR 0x00D00500 00045 #define CMD_CFG_DEV 0x00D80500 00046 #define CMD_SET_MODE 0x00F30500 00047 #define CMD_RD_FRAME 0x00F50500 00048 #define DAT_RD_FRAME 0x00F50200 00049 #define CMD_RD_TEST 0x00FD0500 00050 #define DAT_RD_TEST 0x00FD0200 00051 #define CMD_SET_DEV_STAT 0x00FE0500 00052 #define CMD_GET_DEV_STAT 0x00FE0500 00053 #define DAT_GET_DEV_STAT 0x00FE0200 00054 #define CMD_GET_ERR_CODE 0x00FF0500 00055 #define DAT_GET_ERR_CODE 0x00FF0200 00056 #define CMD_RD_ERR_STAT 0x00FB0500 00057 #define DAT_RD_ERR_STAT 0x00FB0200 00058 #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) 00059 #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) 00060 #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) 00061 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) 00062 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) 00063 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) 00064 #define CMD_CLR_BUF 0x00F20500 00065 #define DAT_CLR_BUF 0x00F20200 00066 #define CMD_VALID_BUF 0x00FA0500 00067 00068 /* Device Address Register Definitions */ 00069 #define DEV_ADDR_MASK 0x7F 00070 #define DEV_EN 0x80 00071 00072 /* Device Configure Register Definitions */ 00073 #define CONF_DVICE 0x01 00074 00075 /* Device Mode Register Definitions */ 00076 #define AP_CLK 0x01 00077 #define INAK_CI 0x02 00078 #define INAK_CO 0x04 00079 #define INAK_II 0x08 00080 #define INAK_IO 0x10 00081 #define INAK_BI 0x20 00082 #define INAK_BO 0x40 00083 00084 /* Device Status Register Definitions */ 00085 #define DEV_CON 0x01 00086 #define DEV_CON_CH 0x02 00087 #define DEV_SUS 0x04 00088 #define DEV_SUS_CH 0x08 00089 #define DEV_RST 0x10 00090 00091 /* Error Code Register Definitions */ 00092 #define ERR_EC_MASK 0x0F 00093 #define ERR_EA 0x10 00094 00095 /* Error Status Register Definitions */ 00096 #define ERR_PID 0x01 00097 #define ERR_UEPKT 0x02 00098 #define ERR_DCRC 0x04 00099 #define ERR_TIMOUT 0x08 00100 #define ERR_EOP 0x10 00101 #define ERR_B_OVRN 0x20 00102 #define ERR_BTSTF 0x40 00103 #define ERR_TGL 0x80 00104 00105 /* Endpoint Select Register Definitions */ 00106 #define EP_SEL_F 0x01 00107 #define EP_SEL_ST 0x02 00108 #define EP_SEL_STP 0x04 00109 #define EP_SEL_PO 0x08 00110 #define EP_SEL_EPN 0x10 00111 #define EP_SEL_B_1_FULL 0x20 00112 #define EP_SEL_B_2_FULL 0x40 00113 00114 /* Endpoint Status Register Definitions */ 00115 #define EP_STAT_ST 0x01 00116 #define EP_STAT_DA 0x20 00117 #define EP_STAT_RF_MO 0x40 00118 #define EP_STAT_CND_ST 0x80 00119 00120 /* Clear Buffer Register Definitions */ 00121 #define CLR_BUF_PO 0x01 00122 00123 00124 /* DMA Interrupt Bit Definitions */ 00125 #define EOT_INT 0x01 00126 #define NDD_REQ_INT 0x02 00127 #define SYS_ERR_INT 0x04 00128 00129 00130 #endif /* __USBREG_H */
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